TWI615926B - Electronic package and method for fabricating the same - Google Patents

Abstract

An electronic package and a method for manufacturing the same, wherein an electronic component and a supplementary component are disposed on an interposer, and the electronic component and the supplementary component are covered by an encapsulation layer to reduce the package by the supplemental component being disposed on the interposer The amount of layer used, which in turn reduces the chance of warping of the interposer.

Description

Electronic package and its manufacturing method

The present invention relates to a semiconductor process, and more particularly to an electronic package and a method of fabricating the same.

At present, there are many technologies applied in the field of chip packaging, such as Chip Scale Package (CSP), Direct Chip Attached (DCA) or Multi-Chip Module (referred to as Multi-Chip Module). MCM) and other flip-chip package modules, or three-dimensional stacking of wafers into a three-dimensional integrated circuit (3D IC) wafer stacking technology.

1 is a schematic cross-sectional view of a semiconductor package 1 of a conventional 3D IC wafer stack. As shown in FIG. 1, the semiconductor package 1 is first provided with a through silicon interposer (TSI) 10 having an opposite crystal side 10b and a transfer side 10a. A plurality of conductive-silicon vias (TSVs) 100 are connected to the crystallized side 10b and the transfer side 10a, and the crystallized side 10b has a circuit redistribution layer electrically connected to the conductive vias 100. (Redistribution laver, referred to as RDL) 101; then, will be half-guided The body wafer 11 is electrically bonded to the circuit redistribution layer 101 by a plurality of solder bumps 111 with a small pitch of the electrode pads 110, and an underfill is filled between the semiconductor wafer 11 and the germanium interposer 10. 12 to cover the solder bumps 111, and then form an encapsulant 13 on the germanium interposer 10 to cover the semiconductor wafer 11 and the underfill 12 to form a package structure 1a; thereafter, a package substrate The conductive pad 15 having a relatively large pitch is electrically coupled to the conductive via hole 100 of the package structure 1a by a plurality of conductive members 15 such as solder bumps or copper pillars, and the germane interposer 10 and the package substrate A further adhesive 12' is filled between the 14 to cover the conductive elements 15; finally, a plurality of solder balls 16 are connected to the bottom side of the package substrate 14 to be connected to a circuit board (not shown).

However, in the fabrication process of the conventional semiconductor package 1, only the semiconductor wafer 11 is disposed on the crystallizing side 10b of the germanium interposer 10, as shown in FIG. 1 and the semiconductor wafer 11 is not filled with the crystal. The entire area of the side 10b is such that when the encapsulant 13 is formed, the long side and the short side encapsulant 13 of the interposer 10 are unevenly distributed, and the coefficient of thermal expansion of the interposer 10 and the encapsulant 13 (Coefficient) The difference in thermal expansion (CTE) is too large, that is, mismatch, causing severe warpage at the edge of the package structure 1a during thermal cycle (such as thermal curing of the encapsulant 13). As a result, bridging occurs between the conductive elements 15 located at the edge of the package structure 1a, thereby causing a short circuit, which in turn causes a problem of a decrease in assembly yield and a decrease in reliability quality.

Therefore, how to overcome the problems of the above-mentioned prior art has become a problem that is currently being solved.

In view of the above-mentioned various deficiencies of the prior art, the present invention provides an electronic package comprising: an interposer having opposite first and second sides; and an electronic component disposed on the second side of the interposer And electrically connecting the interposer; the replenishing member is disposed on the second side of the interposer and is not electrically connected to the interposer; and the encapsulation layer is formed on the second side of the interposer and is covered Electronic components and supplements.

The present invention further provides an electronic package comprising: an interposer having a crystallographic region defined thereon and an opposite idle region; an electronic component disposed in the crystallographic region and electrically connected to the interposer; The component is disposed in the idle area and is not electrically connected to the interposer; the encapsulation layer is formed on the interposer and covers the electronic component and the supplement.

The invention also provides a method for manufacturing an electronic package, comprising: providing an interposer having opposite first and second sides; and disposing at least one electronic component and at least one complementary component on the second side of the interposer The electronic component is electrically connected to the interposer, and the replenishing member is not electrically connected to the interposer; and an encapsulation layer is formed on the second side of the interposer to cover the electronic component and the supplement.

In the above electronic package and method of manufacturing the same, the package substrate is disposed on the first side of the interposer, and the package substrate is electrically connected to the interposer.

In the above electronic package and method of manufacturing the same, the sides of the periphery of the area occupied by the electronic component and the supplement are substantially equal to the distance from the edge of the interposer.

In the above electronic package and method of manufacturing the same, a plurality of conductive vias are formed in the interposer, and a line redistribution structure electrically connecting the conductive vias is formed on the interposer.

In the above electronic package and the method of manufacturing the same, the material forming the supplement is a semiconductor material.

In the above electronic package and method of manufacturing the same, the upper surface of the electronic component and the upper surface of the complementary component expose the encapsulation layer.

In the above electronic package and the method of manufacturing the same, the material forming the supplement has a thermal expansion coefficient of 2 to 5.

It can be seen from the above that the electronic package of the present invention and the method for manufacturing the same are provided by adding a supplement to the idle area on the interposer to reduce the amount of use of the encapsulation layer, thereby reducing the probability of warpage of the interposer and avoiding the yield. Low quality and poor product reliability.

1‧‧‧Semiconductor package

1a‧‧‧Package structure

10‧‧‧矽Intermediary board

10a‧‧‧Transfer side

10b‧‧‧The crystal side

100‧‧‧ Conductive piercing

101‧‧‧Line redistribution

11‧‧‧Semiconductor wafer

110,210‧‧‧electrode pads

111‧‧‧ solder bumps

12,12’,22,22’‧‧‧Bottom

13‧‧‧Package colloid

14,24‧‧‧Package substrate

140,240‧‧‧ solder pads

15,25‧‧‧ conductive elements

16,26‧‧‧ solder balls

2‧‧‧Electronic package

20‧‧‧Intermediary board

20a‧‧‧ first side

20b‧‧‧ second side

200‧‧‧Electrical perforation

201‧‧‧Line redistribution structure

201a‧‧‧Line layer

201b‧‧‧ dielectric layer

21‧‧‧Electronic components

21a‧‧‧Action surface

21b‧‧‧Non-active surface

211‧‧‧Electrical bumps

23‧‧‧Encapsulation layer

241‧‧‧Ball mat

27‧‧‧Replenishment

A‧‧‧ crystal zone

B‧‧‧ vacant area

C‧‧‧ periphery

D‧‧‧distance

1 is a schematic cross-sectional view of a conventional semiconductor package; FIG. 1A is a partial top view of FIG. 1; FIGS. 2A to 2D are schematic cross-sectional views showing a method of manufacturing an electronic component of the present invention; and 2B' And the 2B" diagram is a partial top view of the different aspects of Figure 2B.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.

2A to 2D are schematic cross-sectional views showing the manufacturing method of the electronic package 2 of the present invention.

As shown in FIG. 2A, an interposer 20 is defined. The interposer 20 defines an opposite first side 20a and a second side 20b, and the interposer 20 has a plurality of first and second sides 20a, 20b. (ie, through the interposer 20) conductive vias 200.

In this embodiment, the interposer 20 is a ruthenium-containing plate, such as a Twisted Silicon Interposer (TSI) or a glass substrate, and the conductive via 200 is a through-silicon via. The conductive via 200 is a copper pillar and an insulating material surrounding the copper pillar. However, the conductive via 200 is manufactured in a variety of manners and is not particularly limited, and thus will not be described herein.

Furthermore, the two ends of the conductive via 200 are flushed with the interposer respectively The first side 20a and the second side 20b of 20.

Moreover, a circuit redistribution layer (RDL) process may be selectively performed on the second side 20b of the interposer 20 to form a line redistribution structure 201, and the circuit redistribution structure 201 is electrically connected. Each of the conductive vias 200. Specifically, the circuit redistribution structure 201 includes at least one dielectric layer 201b and at least one circuit layer 201a stacked, and the circuit layer 201a is electrically connected to the conductive via 200.

Alternatively, a plurality of conductive elements 25 may be selectively formed on the first side 20a of the interposer 20. Specifically, the conductive element 25 is a conductive bump. For example, the conductive bump includes a metal pillar (such as a copper pillar) and/or a solder material, and an under bump metallurgy (UBM) can be formed between the conductive bump and the interposer 20, wherein The structure and material of the metal layer under the bump are various and are not particularly limited, and thus will not be described again.

As shown in FIG. 2B and FIG. 2B, at least one electronic component 21 and at least one complementary component 27 are disposed on the second side 20b of the interposer 20, wherein the electronic component 21 is electrically connected to the conductive via of the interposer 20. 200, and the supplement 27 is not electrically connected to the interposer 20. That is, when the electronic component 21 is placed, the supplement 27 is placed around the electronic component 21 to reduce the amount of use of the subsequent package.

In this embodiment, the electronic component 21 is an active component, a passive component, or a combination thereof. The active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 21 has an opposing active surface 21a and an inactive surface 21b, and the effect The surface 21a has a plurality of electrode pads 210, and the electrode pads 210 are provided on the circuit redistribution structure 201 by a plurality of conductive bumps 211 such as solder materials, and are electrically connected to the circuit layer 201a. The glue 22 covers the conductive bumps 211.

Furthermore, as shown in FIG. 2B', the surface of the second side 20b of the interposer 20 is defined with a relative crystal zone A and an idle zone B, wherein the electronic component 21 is located in the crystal zone A, and The replenishing member 27 is located in the idle area B such that the sides of the periphery C of the area occupied by the electronic component 21 and the replenishing member 27 are close to each other (about equal) to the edge d of the interposer 20.

Moreover, the structural feature of the supplement 27 is not easily deformed (ie, non-deformable or high-strength), and its coefficient of thermal expansion (CTE) or Young's modulus needs to be close to the electronic component 21 (or coffin). The coefficient of thermal expansion or Young's modulus, wherein the thermal expansion coefficient of the coffin is 2.5 (at 10 ^-6 /K 20 ° C), so the material forming the supplement 27 has a thermal expansion coefficient of 2 to 5 (at 10 ^{- 6} / K 20 ° C), which may be a semiconductor material, for example, the supplement 27 may be a dummy silicon, a glass block, a dummy wafer or a die attach film (Die Attach Film, referred to as DAF) Structure of the attached wafer.

In addition, the number, shape, and relative position of the replenishing member 27 can be designed according to requirements. For example, the replenishing member 27 is disposed at at least two sides of the electronic component 21 or as shown in FIG. 2B. The replenishing member 27 is provided at one of the positions of the electronic component 21, and has a shape of a line shape or an I-like shape as shown in the second B' or 2B", or a ring-shaped, continuous line shape not shown. Or L-shaped, etc., so the structure of the supplement 27 is various. It is not limited to the above.

As shown in FIG. 2C, an encapsulation layer 23 is formed on the circuit redistribution structure 201 of the second side 20b of the interposer 20, so that the encapsulation layer 23 covers the electronic component 21, the primer 22 and the replenishing member 27, To form an electronic package 2.

In this embodiment, the material of the encapsulation layer 23 is made of polyimide, PI, dry film, epoxy or packaging material.

Furthermore, the non-active surface 21b of the electronic component 21 is exposed to the encapsulation layer 23. For example, the non-active surface 21b of the electronic component 21 is flush with the upper surface of the encapsulation layer 23.

Moreover, the replenishing member 27 can also be exposed to the encapsulating layer 23, for example, the upper surface of the replenishing member 27 is flush with the upper surface of the encapsulating layer 23. The height (or thickness) of the supplement 27 may be approximately the same as the height (or thickness) of the electronic component 21.

As shown in FIG. 2D, a package substrate 24 is disposed on the first side 20a of the interposer 20, and the package substrate 24 is electrically connected to the conductive vias 200 of the interposer 20.

In this embodiment, the package substrate 24 is electrically connected to the conductive vias 200 of the interposer 20 via the conductive pads 25, and forms another bottom between the interposer 20 and the package substrate 24. The glue 22' covers the conductive elements 25.

Furthermore, a plurality of solder balls 26 are connected to the ball pad 241 on the bottom side of the package substrate 24 to connect an electronic device such as a circuit board (not shown).

The electronic package 2 of the present invention is mainly formed by forming the encapsulation layer Before 23, a CTE is added to append the complementary component 27 of the electronic component 21 (or the germanium wafer) so that the supplemental component 27 is located on the interposer and is not occupied by the electronic component 21, and the electronic component 21 and The periphery C of the area occupied by the replenishing member 27 is spaced apart by a distance d around the interposer 20, thereby reducing the amount of use of the encapsulating layer 23 to reduce the probability of occurrence of warpage.

In other words, the warpage caused by the CTE mismatch between the encapsulating layer 23 and the electronic component 21 is suppressed by the replenishing member 27, that is, the stress in the encapsulating layer 23 can be dispersed to the replenishing member 27 to improve the The degree of warpage of the interposer 20, and the size or arrangement of the refill 27 can be adjusted for different electronic packages 2 to optimize the warpage value.

Therefore, compared with the prior art, the method of the present invention can reduce the probability of warpage of the electronic package 2, thereby avoiding the short circuit problem caused by bridging between the conductive members 25 at the edges, or at the edges. The problem that the conductive member 25 cannot be connected to the outside can avoid the problem of a decrease in the assembly yield and a decrease in the reliability quality.

The present invention further provides an electronic package 2 comprising: a package substrate 24, an interposer 20, at least one electronic component 21, at least one supplement 27, and an encapsulation layer 23.

The interposer 20 has a first side 20a and a second side 20b opposite to each other, and a plurality of conductive vias 200 communicating with the first side 20a and the second side 20b, wherein the interposer 20 has its first side 20a The package substrate 24 is electrically connected to the conductive via 200.

The electronic component 21 is disposed on the second side 20b of the interposer 20 and electrically connected to the conductive via 200.

The replenishing member 27 is disposed on the second side 20b of the interposer 20 and is not electrically connected to the interposer 20 .

The encapsulation layer 23 is formed on the second side 20b of the interposer 20 and covers the electronic component 21 and the replenishing member 27 to reduce the package by the replenishing member 27 being disposed on the second side 20b. The volume of layer 23 thus reduces the chance of warping of interposer 20.

In one embodiment, the interposer 20 is a slab containing enamel.

In an embodiment, the second side 20b of the interposer 20 defines a crystal zone A and an idle zone B, and the electronic component 21 is located in the crystal zone A, and the supplement 27 is located in the idle zone. B.

In an embodiment, the second side 20b of the interposer 20 is formed with a circuit redistribution structure 201 electrically connected to the conductive via 200, so that the electronic component 21 is bonded to the circuit redistribution structure 201 and electrically The line redistribution structure 201 is connected, and the line redistribution structure 201 is not electrically connected to the supplemental member 27.

In one embodiment, the material forming the supplement 27 is a semiconductor material.

In summary, the electronic package of the present invention and the method for manufacturing the same are designed to reduce the amount of use of the package layer, thereby reducing the probability of warping of the interposer, thereby improving product yield and Reliability.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as follows. Listed around.

2‧‧‧Electronic package

20‧‧‧Intermediary board

20a‧‧‧ first side

20b‧‧‧ second side

200‧‧‧Electrical perforation

201‧‧‧Line redistribution structure

21‧‧‧Electronic components

21b‧‧‧Non-active surface

22‧‧‧Bottom

23‧‧‧Encapsulation layer

25‧‧‧Conductive components

27‧‧‧Replenishment

Claims (16)

An electronic package comprising: an interposer having opposite first and second sides; an electronic component disposed on a second side of the interposer and electrically connected to the interposer; a strip is disposed on the second side of the interposer and is not electrically connected to the interposer; and an encapsulation layer is formed on the second side of the interposer and covers the electronic component and the replenishing member. An electronic package includes: an interposer having a crystallographic region and an opposite idle region defined on a surface thereof; an electronic component disposed in the crystallographic region and electrically connected to the interposer; And being disposed in the idle area and not electrically connected to the interposer; and an encapsulation layer formed on the interposer and covering the electronic component and the supplement. The electronic package according to claim 1 or 2, further comprising a package substrate on which the interposer is attached. The electronic package of claim 1 or 2, wherein each side of the periphery of the area occupied by the electronic component and the supplement is substantially equal to the distance from the edge of the interposer. The electronic package of claim 1 or 2, wherein A plurality of conductive vias are formed in the interposer, and a line redistribution structure electrically connecting the conductive vias is formed on the interposer. The electronic package of claim 1 or 2, wherein the material forming the supplement is a semiconductor material. The electronic package of claim 1 or 2, wherein the material forming the supplement has a thermal expansion coefficient of 2 to 5. The electronic package of claim 1 or 2, wherein the upper surface of the electronic component and the upper surface of the complementary component expose the encapsulation layer. An electronic package manufacturing method includes: providing an interposer having opposite first and second sides; and disposing at least one electronic component and at least one complementary component in a strip shape on the second side of the interposer The electronic component is electrically connected to the interposer, the replenishing member is not electrically connected to the interposer; and an encapsulation layer is formed on the second side of the interposer to encapsulate the electronic component and the replenishing member. The method for manufacturing an electronic package according to claim 9, further comprising: providing a package substrate on the first side of the interposer, and electrically connecting the package substrate to the interposer. The method of manufacturing the electronic package of claim 9, wherein the second side of the interposer defines a crystallographic region and an opposite idle region, wherein the electronic component is located in the crystallographic region, and the electronic component is located in the crystallographic region. The supplement is located in the free area. The method for manufacturing an electronic package according to claim 9 of the patent application, A plurality of conductive vias are formed in the interposer, and a line redistribution structure electrically connecting the conductive vias is formed on the interposer. The method of manufacturing an electronic package according to claim 9, wherein the material forming the supplement is a semiconductor material. The method of manufacturing an electronic package according to claim 9, wherein the upper surface of the electronic component and the upper surface of the complementary component expose the encapsulation layer. The method of manufacturing an electronic package according to claim 9, wherein each side of the periphery of the area occupied by the electronic component and the supplement is substantially equal to the distance from the edge of the interposer. The method of manufacturing an electronic package according to claim 9, wherein the material forming the supplement has a thermal expansion coefficient of 2 to 5.