TWM455255U - Package substrate having interposer and package structure having the substrate - Google Patents

Abstract

A package substrate having an interposer comprises a substrate body and an interposer, wherein the substrate has a plurality of first and second electrical contact pads formed thereon and first conducting pillars disposed on each of the second contact pad, the interposer includes an interposer body, a plurality of through via and second conducting pillars formed in each of the through vias. The second conducting pillars have protrusions which protrude from the bottom surface of the interposer body, thereby the interposer electrically connects to the first electrical contact pads. The second electrical contact pads locate at circumferential area of the interposer. A package structure having an interposer comprises the package substrate, a semiconductor chip connected to the interposer, and an encapsulant covering the package, semiconductor and the first conducting pillars, wherein the the end of the first conducting pillars are exposed.

Description

Package substrate with interposer and package structure thereof

The present invention relates to a package substrate and a package structure, and more particularly to a package substrate having an interposer and a package structure thereof.

As shown in FIG. 1A, it is a schematic cross-sectional view of a conventional flip-chip package structure. The process of the package structure first provides a bismaleimide having a core plate 102, a first surface 10a and a second surface 10b. a Bismaleimide-Triazine (BT) package substrate 10, and having a plurality of flip-chip pads 100 on the first surface 10a of the package substrate 10; and electrically connecting the electrodes of the semiconductor wafer 12 by the solder bumps 11 Pad 120; then, a primer 17 is formed between the first surface 10a of the package substrate 10 and the semiconductor wafer 12 to cover the solder bump 11; and the second surface 10b of the package substrate 10 has a plurality of implants. The ball pad 101 is electrically connected to another external electronic device such as a printed circuit board by solder balls 13 (not shown).

However, in order to improve the electrical performance of the semiconductor wafer 12, an ultra low-k dielectric (ELK) is generally used in the back-end of line (BEOL) of the semiconductor wafer 12. Or ultra low dielectric constant (Ultra low-k, ULK) dielectric material, but the low-k dielectric material is porous and brittle, so that when the flip chip is packaged, the reliability thermal cycle During the test, the difference in thermal expansion coefficient (CTE) between the package substrate 10 and the semiconductor wafer 12 is too large, resulting in the formation of the solder bumps 11. The contact is prone to breakage due to the inability to withstand thermal stress, and even causes damage to the semiconductor wafer 12, thereby reducing product reliability.

Furthermore, as the electronic products become more compact, shorter, and more functional, the wiring density of the semiconductor wafer 12 is higher and higher, and the pitch between the electrode pads 120 becomes the unit of the nanometer size. Smaller; however, the distance between the flip-chip pads 100 of the conventional package substrate 10 is in units of micrometers, and cannot be effectively reduced to the size of the corresponding electrode pads 120, resulting in a semiconductor wafer 12 having a high line density. However, there is no package substrate 10 that can be matched, so that the electronic product cannot be efficiently produced.

In addition, with the evolution of semiconductor packaging technology, semiconductor devices have developed different package types, and in order to improve electrical functions and save packaging space, a plurality of package structures are stacked to form a package on package (POP) structure. This kind of package can utilize the heterogeneous integration of system package (SiP), and can realize the system of the electronic components of different functions, such as memory, central processing unit, graphics processor, image application processor, etc. Integrated, suitable for a variety of thin and light electronic products.

As shown in FIG. 1B, the conventional package stack structure stacks the second package structure 2b on the first package structure 2a. The first package structure 2a includes a first substrate 21 having opposite first and second surfaces 21a, 21b, and a first electronic component 20 disposed on the first surface 21a and electrically connected to the first substrate 21. The second package structure 2b includes a second substrate 22 having opposite third and fourth surfaces 22a, 22b, and a second electronic component 25 disposed on the third surface 22a and electrically connected to the second substrate 22. Furthermore, a solder ball 210 is formed on the first surface 21a of the first substrate 21 to make the first The fourth surface 22b of the two substrates 22 is stacked on the solder ball 210 and electrically connected to the first substrate 21. Moreover, the second surface 21b of the first substrate 21 has a ball pad 212 for bonding the solder balls 24, and the first and second electronic components 20, 25 are active and/or passive components, and are flip chip The substrate is electrically connected to the substrate, and is filled between the first and second electronic components 20, 25 and the first substrate 21 and the second substrate 22 by a primer 23 to form a flip chip bond.

However, the conventional package stack structure is formed by stacking two package structures by solder balls, and the size variation of the solder balls is difficult to control, so that the two package structures are inclined to be tilted and have poor coplanarity, so that the connection is generated. Point offset and other issues. Furthermore, when the height of the stack needs to be increased, the diameter of the solder ball needs to be increased, resulting in an increase in the surface area of the package substrate occupied by the solder ball, thereby causing the space on the surface of the package substrate and the layout of the electronic component to be compressed to affect the stacking. The pitch of the pad (PoP pad) cannot be continuously reduced. Moreover, in this structure, the solder ball is increased in volume, and bridging is likely to occur. In addition, for the package substrate in which the semiconductor wafer is flip-chip mounted, the underfill is faced in the package process. The overflow glue easily contaminates the surface of the stacked pads, and the yield of the product is lost.

Therefore, how to overcome various problems in the prior art has become a problem that is currently being solved.

In view of the above-mentioned shortcomings of the prior art, a package substrate with an interposer and a package structure thereof disclosed in the present invention can achieve the goal of continuously reducing the line pitch and reducing the package stress.

The package substrate with the interposer of the present invention includes: a substrate body, The first surface has a plurality of first electrical contact pads, a plurality of second electrical contact pads, and a first conductive pillar disposed on each of the second electrical contact pads And an interposer comprising an interposer body having a top surface and a bottom surface, a circuit redistribution layer disposed on the top surface and having a plurality of electrical connection pads on the surface, and a plurality of through holes penetrating the top surface and the bottom surface of the interposer body; And a second conductive pillar disposed in each of the through holes, and the second conductive pillar has a convex portion protruding from a bottom surface of the intermediate layer body, and the intermediate layer is electrically connected to the first portion by the convex portion Electrical contact pads, the second electrical contact pads being located in a peripheral region of the interposer.

The substrate body includes an insulating protective layer disposed on the first surface of the substrate body and having an opening corresponding to the interposer; or the substrate body further includes an insulating protective layer disposed on the substrate body The first surface has an opening corresponding to the first electrical contact pad.

In the package substrate with the interposer of the present invention, a primer is further disposed between the interposer and the substrate body.

The package structure of the present invention includes: a substrate body having opposite first and second surfaces, the first surface having a plurality of first electrical contact pads and a plurality of second electrical contact pads, And a first conductive pillar disposed on each of the second electrical contact pads; the interposer comprises an interposer body having a top surface and a bottom surface, and a circuit re-distribution disposed on the top surface and having a plurality of electrical connection pads on the surface a layer, a plurality of through holes penetrating the top surface and the bottom surface of the interposer body, and a second conductive pillar disposed in each of the through holes, and the second conductive pillar has a convex portion protruding from a bottom surface of the interposer body, The interposer is electrically connected to the first electrical contact pad by the protrusion, and the second The electrical contact pad is located in a peripheral region of the interposer; the semiconductor wafer is connected to the plurality of electrical connection pads disposed on the interposer and electrically connected to the circuit redistribution layer of the interposer; and the encapsulant is coated The substrate body, the interposer, and the semiconductor wafer expose the ends of the first conductive pillars.

The package structure with the interposer includes an electronic component connected to the first conductive pillar, such as another package structure, and the package structure with the interposer is connected and electrically connected by the end of the first conductive pillar The other package structure is connected sexually.

Compared with the prior art, the package substrate with the interposer and the package structure thereof are provided by the interposer to solve the problem of the lack of a compatible package substrate, thereby further providing a package of the semiconductor chip conforming to the high line density. Substrate.

The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily appreciate other advantages and functions of the present invention from the disclosure of the present disclosure.

It is to be understood that the structure, the proportions, the size and the like of the drawings are only used in conjunction with the disclosure of the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effectiveness and the purpose of the creation. The technical content revealed by the creation can be covered. At the same time, the terms "one", "upper" and "lower" as quoted in this manual are for convenience only. It is not intended to limit the scope of the creation of the creation, and the change or adjustment of the relative relationship is considered to be within the scope of the creation of the creation without substantial changes in the technical content.

The implementation of the method for manufacturing the package substrate with the interposer can be divided into two stages. First, the interposer is prepared. Please refer to the 2A to 2G drawings, which are the interposer packages of the present creation. A cross-sectional view of an interposer of a substrate and a method of making the same.

As shown in FIG. 2A, an interposer body 30 having an opposite top surface 30a and a bottom surface 30b is prepared. The material of the interposer body 30 may be glass, single crystal germanium, polysilicon or other semiconductor material.

As shown in FIG. 2B, a protective layer 31 is formed on the bottom surface 30b.

As shown in FIG. 2C, a plurality of through holes 32 penetrating through the top surface 30a and the bottom surface 30b of the interposer body 30 are formed in the interposer body 30.

As shown in FIG. 2D, a second conductive pillar 33 is formed in each of the through holes 32. The second conductive pillar 33 may be made of copper or other conductive material, and the second conductive pillar 33 may be made of, for example, a copper paste. It is printed in each of the through holes 32 and cured.

As shown in FIG. 2E, a redistribution layer (RDL) 34 is formed on the top surface 30a, and a plurality of electrical connection pads 35 are disposed on the outermost layer of the circuit redistribution layer 34 for connection. The semiconductor wafer is electrically connected.

As shown in Fig. 2F, the cutting process is performed.

As shown in FIG. 2G, the protective layer 31 is removed, so that the second conductive pillar 33 has a convex portion 330 protruding from the bottom surface 30b, thereby completing the creation. Intermediary layer 3.

Next, the steps of fabricating the package substrate having the interposer of the present invention, refer to FIGS. 2H to 2I, which are cross-sectional views of the package substrate having the interposer and the method of manufacturing the same.

As shown in FIG. 2H, a substrate body 5 having an opposite first surface 5a and a second surface 5b is provided. The first surface 5a has a plurality of first electrical contact pads 5211 and a plurality of second electrical contact pads 5212. And the first conductive pillars 54 disposed on the second electrical contact pads 5212, and in the second embodiment, the second electrical contact pads 5212 are located on the first electrical contact pads 5211 of the substrate body 5. Peripheral area. In addition, a first insulating protective layer 53a is disposed on the first surface 5a and the second electrical contact pad 5212, and the first insulating protective layer 53a has a first surface 5a of the exposed portion of the opening 530a and all of the first surface An electrical contact pad 5211 for connecting and electrically connecting the convex portion 330 of the second conductive pillar 33 of the interposer 3, the second surface 5b having a plurality of third electrical contact pads 5213, and the second surface 5b There is a second insulating protective layer 53b, and the second insulating protective layer 53b has an opening 530b for exposing the third electrical contact pad 5213.

In addition, as shown in FIG. 2H, the substrate body 5 may include a core layer 51 including a core dielectric layer 510 having opposing top surfaces 510a and 510b, respectively formed on the top surface 510a and the bottom surface. The first circuit layer 511a and the second circuit layer 511b of 510b pass through the core dielectric layer 510 to connect the conductive vias 5101 of the first circuit layer 511a and the second circuit layer 511b. In addition, the substrate body 5 may include a first build-up layer formed on the top surface 510a of the first circuit layer 511a and the core dielectric layer 510. And a second build-up structure 52b formed on the bottom surface 510b of the second circuit layer 511b and the core dielectric layer 510, wherein the first build-up structure 52a includes at least one first dielectric layer 520a and is disposed on The first build-up circuit layer 521a on the first dielectric layer 520a, and the first build-up circuit layer 521a has the first electrical contact pad 5211 and the second electrical contact pad 5212, and the second increase The layer structure 52b includes at least one second dielectric layer 520b and a second build-up wiring layer 521b disposed on the second dielectric layer 520b, and the second build-up wiring layer 521b has the third electrical contact pad described above. 5213.

It should be noted that, at this time, the first insulating protective layer 53a of the substrate body 5 of the present invention may be in the following aspect as in the aspect of the above-mentioned FIG. 2H: as shown in FIG. 2H', The first insulating protective layer 53a' can cover all the first surfaces 5a of the substrate body 5, and has a plurality of openings 530a' corresponding to the first electrical contact pads 5211, respectively, for subsequent connection and power supply. The convex portion 330 of the second conductive pillar 33 of the interposer 3 is connected.

As shown in FIG. 2I, the convex portion 330 is electrically connected to the first electrical contact pad 5211 by using the solder bumps 55 to bond the interposer 3 to the substrate body 5, and each of the second electrical contacts The pad 5212 is located in the peripheral region of the interposer 3 to obtain the encapsulating substrate with the interposer of the present invention.

It should be noted that, at this time, the combination of the substrate body 5 of the present invention and the interposer 3 may be as follows, as shown in the second aspect of FIG. A primer 56 is disposed between the interposer 3 and the substrate body 5, that is, the underfill 56 is filled between the interposer body 30 and the first electrical contact pad 5211, and the interposer body 30 and Between a surface 5a.

In addition, please refer to FIGS. 2J to 2L, which are cross-sectional views of an application example of the package substrate having the interposer of the present invention.

As shown in FIG. 2J, the semiconductor wafer 4 is attached to the interposer 3, and the underlayer (not shown) may be filled between the semiconductor wafer 4 and the interposer 3, and then performed. Follow-up steps.

As shown in FIG. 2K, the interposer 3, the semiconductor wafer 4, and the substrate body 5 are encapsulated by the encapsulant 60 to form a package structure 6, which encapsulates the interposer 3 and the semiconductor wafer 4 and covers The first insulating protective layer 53a, the first electrical connection pad 5211, and the second electrical connection pad 5212 expose the end of the first conductive pillar 54.

As shown in FIG. 2L, the end of the first conductive pillar 54 is used to connect and electrically connect the electronic component, such as another package structure 7, to the package structure 6.

In addition, the present invention provides a package substrate having an interposer, as shown in FIG. 2I, comprising: a substrate body 5 having an opposite first surface 5a and a second surface 5b, the first surface 5a having a plurality of first electrical contact pads 5211, a plurality of second electrical contact pads 5212, and first conductive pillars 54 disposed on each of the second electrical contact pads 5212; and an interposer 3 comprising a top surface 30a and The interposer body 30 of the bottom surface 30b, the circuit redistribution layer 34 disposed on the top surface 30a and having a plurality of electrical connection pads 35, and the plurality of through holes 32 extending through the top surface 30a and the bottom surface 30b of the interposer body 30, and The second conductive pillar 33 is disposed in each of the through holes 32, and the second conductive pillar 33 has a convex portion 330 protruding from the bottom surface 30b of the interposer body 30. The interposer 3 is formed by the convex portion 330. Electrically connecting the first electric The second contact pads 5211 are located in the peripheral region of the interposer 3 .

In the above package substrate, the substrate body 5 further includes a first insulating protective layer 53a disposed on the first surface 5a of the substrate body 5 and having an opening 530a corresponding to the interposer 3, as shown in FIG. 2H. Shown. Alternatively, the substrate body 5 further includes a first insulating protective layer 53a' disposed on the first surface 5a of the substrate body 5 and having an opening 530a' corresponding to the first electrical contact pad 5211, such as Figure 2H' is shown.

In the above package substrate, a primer 56 is provided, and the primer 56 is disposed between the interposer 3 and the substrate body 5 as shown in FIG.

Furthermore, the present invention provides a package structure having an interposer, as shown in FIG. 2K, which includes a substrate body 5 having opposing first and second surfaces 5a and 5b, the first surface 5a being a plurality of first electrical contact pads 5211, a plurality of second electrical contact pads 5212, and a first conductive pillar 54 disposed on each of the second electrical contact pads 5212; the interposer 3 includes a top surface 30a and The interposer body 30 of the bottom surface 30b, the circuit redistribution layer 34 disposed on the top surface 30a and having a plurality of electrical connection pads 35, and the plurality of through holes 32 extending through the top surface 30a and the bottom surface 30b of the interposer body 30, and The second conductive pillar 33 is disposed in each of the through holes 32, and the second conductive pillar 33 has a convex portion 330 protruding from the bottom surface 30b of the interposer body 30. The interposer 3 is formed by the convex portion 330. The second electrical contact pads 5211 are electrically connected to the peripheral region of the interposer 3; the semiconductor wafer 4 is electrically connected to the interposer 3 and electrically connected to the interposer. The plurality of electrical connection pads of the layer redistribution layer 34 of layer 3 And the encapsulant 60 covers the substrate body 5, the interposer 3, and the semiconductor wafer 4, and exposes the end of the first conductive pillar 54.

In the foregoing package structure, as shown in FIGS. 2H and H′, the substrate body 5 may include an opening 530a disposed on the first surface 5a of the substrate body 5 and having an interposer 3 corresponding thereto. An insulating protective layer 53a, as shown in FIG. 2H, or the substrate body 5 may include an opening 530a' disposed on the first surface 5a of the substrate body 5 and corresponding to the first electrical contact pad 5211. The first insulating protective layer 53a' is as shown in FIG. 2H'.

In the above package structure, as shown in FIG. 2I, a primer 56 is provided, and the primer 56 is disposed between the interposer 3 and the substrate body 5.

In the above package structure, a primer (not shown) disposed between the semiconductor wafer 4 and the interposer 3 may be further included.

In the foregoing package structure, as shown in FIG. 2L, the electronic component is placed on the first conductive pillar, such as another package structure 7, and the package structure 6 utilizes the end of the first conductive pillar 54. The other package structure 7 is connected and electrically connected to the package structure 6.

It should be noted that although the embodiment is illustrated by a substrate having a core, the substrate body without a core can also be applied to the present invention, and is included in the patent application scope of the present application. In addition, although the figure shows the electrical connection between the interposer of the present creation and the substrate body, and the electrical connection between the interposer and the semiconductor wafer is by solder balls, the electrical connection can also be by other means. , not limited to solder balls.

In summary, the intervening package substrate of the present invention utilizes the The interposer connects the semiconductor wafer and the substrate body, thereby serving as a bridge between the signal connection and the stress buffer, and preventing cracking due to thermal stress between the semiconductor wafer and the substrate body. Secondly, the creation is located on the interposer body. The second conductive pillar in the hole protrudes from the bottom surface of the interposer body, and is electrically connected to the first electrical contact pad of the substrate body, and the second conductive pillar is configured to electrically connect the interposer to the substrate body; Furthermore, the first conductive pillar in the peripheral region of the interposer protrudes perpendicularly from the substrate body, so that the encapsulant can cover the end of the first conductive post after covering the semiconductor wafer, the interposer and the substrate body. To overlap with a package structure to form a package stack structure.

The above embodiments are intended to illustrate the principles of the present invention and its effects, and are not intended to limit the present invention. Anyone who is familiar with the art may modify the above embodiments without departing from the spirit and scope of the creation. Therefore, the scope of protection of this creation should be as listed in the scope of patent application described later.

10‧‧‧Package substrate

10a, 21a, 5a‧‧‧ first surface

10b, 21b, 5b‧‧‧ second surface

100‧‧‧Flip solder pad

101, 212‧‧‧ ball mat

102‧‧‧ core board

11, 55‧‧‧ solder bumps

12, 4‧‧‧ semiconductor wafer

120‧‧‧electrode pads

13, 210, 24‧‧ ‧ solder balls

17, 23, 56‧‧ ‧ primer

2a‧‧‧First package structure

2b‧‧‧Second package structure

20‧‧‧First electronic components

21‧‧‧First substrate

22‧‧‧second substrate

22a‧‧‧ third surface

22b‧‧‧Fourth surface

25‧‧‧Second electronic components

3‧‧‧Intermediary

30‧‧‧Intermediary layer ontology

30a, 510a‧‧‧ top

30b, 510b‧‧‧ bottom

32‧‧‧Tongkong

33‧‧‧Second conductive column

330‧‧‧ convex

34‧‧‧Line redistribution

35‧‧‧Electrical connection pads

5‧‧‧Substrate body

51‧‧‧ core layer

510‧‧‧core dielectric layer

5101‧‧‧Electrical through hole

511a‧‧‧First circuit layer

511b‧‧‧second circuit layer

52a‧‧‧First buildup structure

520a‧‧‧First dielectric layer

521a‧‧‧First build-up circuit layer

52b‧‧‧Second layered structure

520b‧‧‧Second dielectric layer

521b‧‧‧Second layered circuit layer

5211‧‧‧First electrical contact pad

5212‧‧‧Second electrical contact pads

5213‧‧‧ Third electrical contact pad

53a, 53a’‧‧‧ first insulating protective layer

530a‧‧‧ openings

530b, 530a’‧‧‧ openings

53b‧‧‧Second insulation protection layer

54‧‧‧First conductive column

60‧‧‧Package colloid

6, 7‧‧‧ package structure

1A is a cross-sectional view of a conventional flip-chip package structure; FIG. 1B is a cross-sectional view of a conventional package stack structure; and 2A to 2L are diagrams of a package substrate with an interposer and a method for fabricating the same and application thereof In the cross-sectional view of the example, the 2H' is a cross-sectional view of an embodiment of the 2Hth, and the 2I' is a cross-sectional view of an embodiment of the 2I.

3‧‧‧Intermediary

30‧‧‧Intermediary layer ontology

30a, 510a‧‧‧ top

30b, 510b‧‧‧ bottom

32‧‧‧Tongkong

33‧‧‧Second conductive column

330‧‧‧ convex

34‧‧‧Line redistribution

35‧‧‧Electrical connection pads

5‧‧‧Substrate body

5a‧‧‧ first surface

5b‧‧‧ second surface

51‧‧‧ core layer

510‧‧‧core dielectric layer

5101‧‧‧Electrical through hole

511a‧‧‧First circuit layer

511b‧‧‧second circuit layer

52a‧‧‧First buildup structure

520a‧‧‧First dielectric layer

521a‧‧‧First build-up circuit layer

52b‧‧‧Second layered structure

520b‧‧‧Second dielectric layer

521b‧‧‧Second layered circuit layer

5211‧‧‧First electrical contact pad

5212‧‧‧Second electrical contact pads

5213‧‧‧ Third electrical contact pad

53a‧‧‧First insulation protection layer

530a‧‧‧ openings

53b‧‧‧Second insulation protection layer

530b‧‧‧Opening

54‧‧‧First conductive column

55‧‧‧ solder bumps

Claims (10)

A package substrate with an interposer includes: a substrate body having opposite first and second surfaces, the first surface having a plurality of first electrical contact pads, a plurality of second electrical contact pads, and a setting a first conductive pillar on each of the second electrical contact pads; and an interposer comprising an interposer body having a top surface and a bottom surface, and a circuit redistribution layer disposed on the top surface and having a plurality of electrical connection pads on the surface a plurality of through holes penetrating the top surface and the bottom surface of the interposer body, and a second conductive post disposed in each of the through holes, and the second conductive post has a convex portion protruding from a bottom surface of the interposer body, The interposer is electrically connected to the first electrical contact pad by the protrusion, and the second electrical contact pads are located in a peripheral region of the interposer. The package substrate with an interposer as described in claim 1, wherein the substrate body further comprises an insulating protective layer disposed on the first surface of the substrate body and having an opening corresponding to the interposer. The package substrate of the interposer of claim 1, wherein the substrate body further comprises an insulating protective layer disposed on the first surface of the substrate body and having the corresponding first electrical property The opening of the contact pad. The package substrate with an interposer as described in claim 1 further comprises a primer disposed between the interposer and the substrate body. The package structure with an interposer includes: a substrate body having opposite first and second surfaces, The first surface has a plurality of first electrical contact pads, a plurality of second electrical contact pads, and a first conductive pillar disposed on each of the second electrical contact pads; the interposer includes an intermediary having a top surface and a bottom surface a layer body, a circuit redistribution layer disposed on the top surface and having a plurality of electrical connection pads on the surface, a plurality of through holes penetrating through the top surface and the bottom surface of the interposer body, and a second conductive column disposed in each of the through holes And the second conductive pillar has a convex portion protruding from a bottom surface of the interposer body, and the interposer is electrically connected to the first electrical contact pad by the convex portion, and the second electrical contact pads are a semiconductor wafer, a plurality of electrical connection pads disposed on the interposer and electrically connected to the circuit redistribution layer of the interposer; and an encapsulant that encapsulates the substrate body and the interposer a layer and a semiconductor wafer, and exposing an end of the first conductive pillar. The package structure with an interposer as described in claim 5, wherein the substrate body further comprises an insulating protective layer disposed on the first surface of the substrate body and having an opening corresponding to the interposer. The package structure of the interposer according to claim 5, wherein the substrate body further comprises an insulating protective layer disposed on the first surface of the substrate body and having the corresponding first electrical property The opening of the contact pad. The package structure with an interposer as described in claim 5, further comprising a primer disposed between the interposer and the substrate body. The encapsulation structure with an interposer as described in claim 5, further comprising a primer disposed between the semiconductor wafer and the interposer. The encapsulation structure with an interposer as described in claim 5, further comprising an electronic component attached to the first conductive post.