TWI638411B - Method of fabricating electronic packing - Google Patents

Abstract

An electronic package is formed by forming a conductive pillar on the upper side of the first circuit structure and combining the first electronic component, and then covering the conductive pillars and the first electronic component with an insulating layer, and then forming a second circuit structure. a second circuit structure is disposed on the lower side of the first circuit structure, and a second electronic component is disposed on the second circuit structure, and an encapsulation layer is formed to cover the second electronic component, and finally a portion of the insulating layer is removed to expose a portion of the surface of the conductive pillar俾 Replace the conventional 矽 interposer with the conductive post and the insulating layer to save process cost.

Description

 Electronic package manufacturing method  

The present invention relates to a semiconductor process, and more particularly to a method of fabricating a semiconductor package structure.

With the booming of the electronics industry, electronic products are gradually moving towards versatility and high performance. The technologies used in the field of chip packaging include: Chip Scale Package (CSP), direct attach of wafers. A flip-chip package module such as a Direct Chip Attached (DCA) or a Multi-Chip Module (MCM), or a three-dimensional integrated chip into a three-dimensional integrated circuit (3D IC) Wafer stacking technology, etc.

1 is a schematic cross-sectional view of a semiconductor package 1 of a conventional 3D IC wafer stack, which includes a through silicon interposer (TSI) 10 having a lateral side 10a and a turn a junction side 10b, and a plurality of conductive-silicon vias (TSV) 100 connected to the crystallizing side 10a and the switching side 10b, and having a plurality of redistribution layers (Redistribution Layer) The electrode pad 190 of the semiconductor wafer 19 having a small pitch is electrically coupled to the crystallizing side 10a by a plurality of solder bumps 102, and the solder bumps 102 are covered with a primer 192. And forming an encapsulant 18 on the germane interposer 10 to cover the semiconductor wafer 19, and further on the circuit redistribution layer 101 by a plurality of packaged substrates 17 having a plurality of conductive members 103 electrically coupled to each other. The pad 170 is soldered and the conductive elements 103 are covered with a primer 172.

In addition, when the semiconductor package 1 is fabricated, the semiconductor wafer 19 is first placed on the germane interposer 10, and the germanium interposer 10 is placed on the package substrate 17 with the conductive elements 103. The encapsulant 18 is then formed.

In addition, in the subsequent assembly process of the semiconductor package 1, the semiconductor package 1 is bonded to a circuit board (not shown) by the lower side of the package substrate 17 to utilize the conductive vias 100 as the A medium for signal transmission between the semiconductor wafer 19 and the circuit board.

However, in the manufacturing method of the conventional semiconductor package 1, the NMOS interposer 10 is used as a medium for signal transmission between the semiconductor wafer 19 and the package substrate 17, and the control is required to have a certain aspect ratio (ie, the conductive 矽 hole is perforated). The 100 aspect ratio of 100 um / 10 um) can be used to produce a suitable enamel interposer 10, which often requires a large amount of process time and cost of chemicals, thereby increasing process difficulty and manufacturing cost.

Therefore, how to overcome the various problems of the above-mentioned prior art has become a problem that is currently being solved.

In view of the above-mentioned various deficiencies of the prior art, the present invention provides a method for manufacturing an electronic package, comprising: providing a first line structure having a first side and a second side opposite to each other, and the first line structure includes a circuit layer; forming a plurality of conductive pillars on the first side of the first circuit structure, and bonding the first electronic component on the first side of the first circuit structure, wherein the conductive pillars and the first electronic component are electrically The first circuit layer is connected to the first circuit layer; the insulating layer is formed on the first side of the first circuit structure, so that the insulating layer covers the conductive pillar and the first electronic component; and the second circuit structure is formed on the first circuit On the second side of the structure, the second circuit structure includes a second circuit layer electrically connected to the first circuit layer; a second electronic component is disposed on the second circuit structure, and the electronic component is electrically connected The second circuit layer; forming an encapsulation layer on the second wiring structure to cover the second electronic component; and removing a portion of the insulating layer to expose a portion of the surface of the conductive pillar.

In the above method for manufacturing an electronic package, the material of the conductive pillar is a solder material or a metal material.

In the above method of manufacturing an electronic package, a part of the surface of the first electronic component is exposed to the insulating layer.

In the above method for manufacturing an electronic package, a portion of the encapsulation layer is removed to expose a portion of the surface of the second electronic component to the encapsulation layer.

In the above method for manufacturing an electronic package, the material of the encapsulation layer is the same as or different from the material of the insulating layer.

In the above method of manufacturing an electronic package, a portion of the surface of the conductive pillar on which the conductive layer is exposed is formed.

It can be seen from the above that the electronic package of the present invention is mainly formed by forming the conductive pillars on the first circuit structure and coating the conductive pillars with an insulating layer, so that it is not necessary to form a conventional perforation. It can produce conductive columns of various sizes according to the requirements of aspect ratio, so that the end products can meet the requirements of light, thin, short and small, and can increase the output and save the cost of chemical chemicals.

Furthermore, the method of the present invention replaces the conventional 矽 interposer with the insulating layer, and uses the conductive pillars as a medium for signal transmission between the second electronic component and the circuit board, so compared with the prior art, The method of the invention does not require the production of a TSV, thereby greatly reducing the difficulty of the process and the cost of production.

In addition, by directly connecting the second electronic component of the high I/O function to the second circuit structure, it is not necessary to use a package substrate including the core layer and a TSV interposer, thereby reducing the The thickness of the electronic package.

1‧‧‧Semiconductor package

10‧‧‧矽Intermediary board

10a‧‧‧The crystal side

10b‧‧‧Transfer side

100‧‧‧ Conductive piercing

101‧‧‧Line redistribution

102,230,250‧‧‧ solder bumps

103,28‧‧‧Conductive components

17‧‧‧Package substrate

170‧‧‧ solder pads

172,192‧‧‧ 底胶

18‧‧‧Package colloid

19‧‧‧Semiconductor wafer

190‧‧‧electrode pads

2‧‧‧Electronic package

20‧‧‧Carrier

200‧‧‧Separation layer

21‧‧‧First line structure

21a‧‧‧ first side

21b‧‧‧ second side

210‧‧‧First dielectric layer

211‧‧‧First line layer

212‧‧‧ Metal layer under the bump

22‧‧‧Second line structure

220‧‧‧Second dielectric layer

221‧‧‧second circuit layer

222‧‧‧metal layer

23‧‧‧First electronic components

24‧‧‧Encapsulation layer

25‧‧‧Second electronic components

26,36‧‧‧conductive column

27‧‧‧Insulation

9‧‧‧Circuit board

1 is a schematic cross-sectional view of a conventional semiconductor package; 2A to 2F are schematic cross-sectional views showing a method of manufacturing an electronic package of the present invention; and FIG. 2G is a cross-sectional view showing a subsequent application of the electronic package of the present invention; And Fig. 3 is a schematic cross-sectional view showing another embodiment of the electronic package of the present invention.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.

2A to 2F are schematic cross-sectional views showing the manufacturing method of the electronic package 2 of the present invention.

As shown in FIG. 2A, a carrier 20 having a spacer layer 200 is provided, and a first wiring structure 21 is formed on the spacer layer 200 of the carrier 20. Then, a plurality of conductive pillars 26 are formed and combined with the first electronic component 23 on the first circuit structure 21, wherein the first electronic component 23 is electrically coupled to the first wiring structure 21 by a plurality of solder bumps 230.

In this embodiment, the carrier 20 is a semiconductor board body, such as a dummy Si wafer, a glass or a polymer board, and the spacer layer 200 is, for example, a thermal SiO ₂ layer. Layer) or an adhesive layer (preferably an organic adhesive layer).

Furthermore, the first line structure 21 can be formed by a Redistribution Layer (RDL) process, and the first line structure 21 has a first side 21a and a second side 21b opposite to each other. The two sides 21b are bonded to the separation layer 200. Specifically, the first circuit structure 21 has at least one first dielectric layer 210 and at least one first circuit layer 211 formed in the first dielectric layer 210. The first circuit layer 211 may be formed on the first circuit layer 211. An under bump metallurgy (UBM) 212 is bonded to bond the conductive pillars 26 and the solder bumps 230.

Moreover, the conductive pillar 26 is formed in a patterned manner (such as plating metal, deposited metal or etched metal, etc.) to form a metal pillar such as a copper pillar on the first side 21a of the first wiring structure 21, and The conductive pillars 26 are electrically connected to the first circuit layer 211.

In addition, the first electronic component 23 is an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. Specifically, the first electronic component 23 is electrically connected to the first circuit layer 211 in a flip chip manner. For example, the first electronic component 23 is electrically coupled to the first circuit layer 211 by a plurality of solder bumps 230. It should be understood that the first electronic component 23 can also be electrically connected to the first circuit layer 211 in a wire bonding manner.

As shown in FIG. 2B, an insulating layer 27 is formed on the first side 21a of the first line structure 21 to cover the conductive pillars 26 and the first electronic component 23.

In the present embodiment, the material of the insulating layer 27 is formed by polyimide (PI), dry film, epoxy or package.

As shown in FIG. 2C, the carrier 20 is removed and the spacer layer 200 is retained on the first line structure 21. Next, a second line structure 22 is formed on the spacer layer 200 of the second side 21b of the first line structure 21.

In this embodiment, when the carrier 20 is made of a germanium wafer material, most of the material of the carrier 20 is first removed by grinding, and then the material of the remaining carrier 20 is removed by etching to retain the spacer layer. 200, wherein the spacer layer 200 serves as an etch stop layer. When the carrier 20 is made of a glass material, the spacer layer 200 is partially viscous by heating or illuminating (such as UV light) to remove the carrier 20 and retain the spacer layer 200. The spacer layer 200 is used as an adhesive layer.

Furthermore, the second line structure 22 can be formed by a line redistribution layer (RDL) process, and the second line structure 22 has a plurality of second dielectric layers 220 formed in the second dielectric layer 220 and a second circuit layer 221 of the spacer layer 200 and a metal layer 222 formed on the outermost second dielectric layer 220 to electrically connect the second circuit layer 221 to the first circuit layer 211, and The metal layer 222 is electrically connected to the second circuit layer 221.

In the present embodiment, the metal layer 222 is fabricated, for example, by electroplating, and the metal layer 222 is a patterned wiring layer including electrical pads and conductive traces. However, there are many ways to process the line, such as the RDL process, so it will not be repeated here.

As shown in FIG. 2D, a plurality of second electronic components 25 are disposed on the second line structure 22. Next, an encapsulation layer 24 is formed on the second line structure 22 to encapsulate the second electronic components 25.

In this embodiment, the second electronic component 25 is an active component, a passive component, or a combination thereof, wherein the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor.

Furthermore, the second electronic component 25 is electrically connected to the second circuit layer 221 in a flip chip manner. For example, the second electronic component 25 is electrically bonded to the metal layer 222 by a plurality of solder bumps 250. It should be understood that the second electronic component 25 can also be electrically connected to the metal layer 222 in a wire bonding manner.

The material of the encapsulation layer 24 is made of polyimine (PI), dry film, epoxy or package material, and the material of the encapsulation layer 24 and the insulating layer 27 may be Same or different.

As shown in FIG. 2E, a portion of the insulating layer 27 is removed to expose a portion of the surface of the conductive pillar 26.

In the present embodiment, a flattening process is performed on the insulating layer 27, such as a grinding method, to expose (but flush) a portion of the surface (end) of the conductive pillar 26 to the surface of the insulating layer 27. In other embodiments, an opening process may be performed on the insulating layer 27 such that a portion of the surface of the conductive pillar 26 is exposed to the opening of the insulating layer 27. It should be understood that after removing a portion of the insulating layer 27, the first electronic component 23 may also be exposed to the insulating layer 27 (as shown in FIG. 3).

In addition, a flattening process or a hole opening process may be performed on the encapsulation layer 24 to expose a portion of the surface of the second electronic component 25 to the surface of the encapsulation layer 24.

As shown in FIG. 2F, a plurality of conductive members 28 are formed on a portion of the surface of the conductive pillar 26 on which the insulating layer 27 is exposed to form an electronic package 2.

In this embodiment, the conductive element 28 is a solder ball, a metal bump or a metal pin or the like.

Moreover, the electronic package 2 can be directly electrically connected to a circuit board 9 by the conductive elements 28 (as shown in FIG. 2G), without the need for an additional interposer, thereby reducing the manufacturing cost. And can reduce the overall thickness of the end product.

Alternatively, in other embodiments, the conductive pillars 36 may be solder materials, such as the solder balls shown in FIG. 3, so that the conductive pillars 36 are bonded to the circuit board 9 by the conductive component 28, Or electrically connecting the conductive pillars 36 to the circuit board 9.

In summary, the electronic package of the present invention is formed by forming the conductive pillars 26, 36 on the first circuit structure 21 and covering the conductive pillars 26, 36 with the insulating layer 27. The aspect ratio requires the fabrication of conductive pillars 26, 36 in a variety of sizes (e.g., small aspect ratios) to provide end products that are light, thin, short, and small, and that can increase throughput and save on chemical costs.

Furthermore, the electronic package of the present invention is formed by replacing the conventional interposer with the insulating layer 27, and using the conductive posts 26, 36 as the signal transmission between the circuit board 9 and the second electronic component 25. Compared with the prior art, the method of the present invention does not require the fabrication of a TSV, thereby greatly reducing the difficulty of the process and the manufacturing cost.

In addition, the electronic package of the present invention directly connects the second electronic component 25 with high I/O function to the second circuit structure 22, thereby eliminating the need to use a package substrate with a core layer and a TSV. After the interposer, the thickness of the electronic package 2 can be reduced.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

Claims (10)

An electronic package manufacturing method includes: providing a first circuit structure having opposite first and second sides, wherein the first circuit structure includes a first circuit layer; forming a plurality of conductive pillars at the first a first electronic component is coupled to the first side of the first circuit structure, wherein the conductive pillar and the first electronic component are electrically connected to the first circuit layer; forming an insulating layer On the first side of the first line structure, the insulating layer covers the conductive pillar and the first electronic component; and the second circuit structure is formed on the second side of the first circuit structure, wherein the first The second circuit structure includes a second circuit layer electrically connected to the first circuit layer; a second electronic component is disposed on the second circuit structure, and the second electronic component is electrically connected to the second circuit layer; forming a package Laminating on the second wiring structure to cover the second electronic component; and removing a portion of the insulating layer to expose a portion of the surface of the conductive pillar. The method for manufacturing an electronic package according to claim 1, wherein the conductive pillar is made of a solder material or a metal material. The method of manufacturing an electronic package according to claim 1, wherein a part of the surface of the first electronic component is exposed to the insulating layer. The method for manufacturing an electronic package according to claim 1, further comprising removing a portion of the encapsulation layer to make a part of the surface of the second electronic component Exposed to the encapsulation layer. The method of manufacturing an electronic package according to claim 1, wherein the material of the encapsulation layer is the same as the material of the insulating layer. The method of manufacturing an electronic package according to claim 1, wherein the material of the encapsulation layer is different from the material of the insulation layer. The method of manufacturing an electronic package according to claim 1, further comprising forming a conductive element on a portion of a surface of the conductive pillar on which the insulating layer is exposed. The method of manufacturing an electronic package according to claim 1, wherein the first circuit structure is disposed on a carrier with the second side thereof. The method of manufacturing an electronic package according to claim 8, wherein the carrier is removed after forming the insulating layer on the first side of the first line structure. The method for manufacturing an electronic package according to claim 1, further comprising forming a metal layer under the bump on the first circuit layer to bond the conductive pillar.