US20140124961A1 - Techniques and configurations for recessed semiconductor substrates - Google Patents

Techniques and configurations for recessed semiconductor substrates Download PDF

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Publication number
US20140124961A1
US20140124961A1 US14/153,892 US201414153892A US2014124961A1 US 20140124961 A1 US20140124961 A1 US 20140124961A1 US 201414153892 A US201414153892 A US 201414153892A US 2014124961 A1 US2014124961 A1 US 2014124961A1
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Prior art keywords
semiconductor substrate
dies
channels
redistribution layer
interconnect structures
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US14/153,892
Inventor
Albert Wu
Roawen Chen
Chung Chyung Han
Shiann-Ming Liou
Chien-Chuan Wei
Runzi Chang
Scott Wu
Chuan-Cheng Cheng
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Marvell World Trade Ltd
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Marvell World Trade Ltd
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Priority to US14/153,892 priority Critical patent/US20140124961A1/en
Publication of US20140124961A1 publication Critical patent/US20140124961A1/en
Abandoned legal-status Critical Current

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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Definitions

  • Embodiments of the present disclosure relate to the field of integrated circuits, and more particularly, to techniques, structures, and configurations of recessed semiconductor substrates for package assemblies.
  • Integrated circuit devices such as transistors
  • dies or chips that continue to scale in size to smaller dimensions.
  • the shrinking dimensions of the dies are challenging conventional substrate fabrication and/or package assembly technologies that are currently used to route electrical signals to or from the semiconductor die.
  • laminate substrate technologies may not produce sufficiently small features on a substrate to correspond with the finer pitches of interconnects or other signal-routing features formed on the dies.
  • the present disclosure provides a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies.
  • the present disclosure provides an apparatus comprising a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, a dielectric film formed on the first surface of the semiconductor substrate, a redistribution layer formed on the dielectric film, one or more dies electrically coupled to the redistribution layer, a molding compound formed on the semiconductor substrate, one or more channels formed through the second surface of the semiconductor substrate, and one or more package interconnect structures disposed in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer through the one or more channels to route electrical signals of the one or more dies.
  • FIG. 1 schematically illustrates a package assembly that includes a recessed semiconductor substrate.
  • FIGS. 2A-2I schematically illustrate a package assembly subsequent to various process operations.
  • FIG. 3 schematically illustrates another package assembly that includes a recessed semiconductor substrate.
  • FIG. 4 is a process flow diagram of a method to fabricate a package assembly described herein.
  • Embodiments of the present disclosure describe techniques, structures, and configurations for a semiconductor substrate having a recessed region and associated package assemblies.
  • Other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.
  • the phrase “A/B” means A or B.
  • the phrase “A and/or B” means “(A), (B), or (A and B).”
  • the phrase “at least one of A, B, and C” means “(A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).”
  • the phrase “(A)B” means “(B) or (AB)” that is, A is an optional element.
  • FIG. 1 schematically illustrates a package assembly 100 that includes a recessed semiconductor substrate 102 .
  • the package assembly 100 generally includes a semiconductor substrate 102 , which is a substrate or interposer that substantially comprises a semiconductor material such as, for example, silicon (Si). That is, the bulk of the material of the semiconductor substrate 102 is a semiconductor material.
  • the semiconductor material can include crystalline and/or amorphous types of material. In the case of silicon, for example, the silicon can include single crystal and/or polysilicon types.
  • the semiconductor substrate 102 can include other semiconductor materials such as, for example, germanium, group III-V materials, or group II-VI materials, that may also benefit from the principles described herein.
  • the semiconductor substrate 102 includes a first surface, A 1 , and a second surface, A 2 , that is disposed opposite to the first surface A 1 .
  • the first surface A 1 and the second surface A 2 generally refer to opposing surfaces of the semiconductor substrate 102 to facilitate the description of various configurations described herein.
  • a portion of the second surface A 2 is recessed to provide a thickness, T, that facilitates the formation of one or more channels 104 through the semiconductor substrate 102 .
  • the semiconductor substrate 102 is recessed to have a thickness T between about 10 microns and about 500 microns. The thickness is not limited to this range and other thicknesses, both greater and smaller, can be used in other embodiments.
  • the semiconductor substrate 102 is fabricated using technologies similar to those that are generally known to fabricate integrated circuit (IC) structures on a die or chip. For example, well-known patterning processes such as lithography/etch and/or deposition processes for fabricating IC devices on a die can be used to form features of the semiconductor substrate 102 . By using semiconductor fabrication techniques, the semiconductor substrate 102 can include smaller features than other types of substrates such as laminate (e.g., organic) substrates.
  • the semiconductor substrate 102 facilitates routing of electrical signals, such as input/output (I/O) and/or power/ground signals, for dies, which continue to shrink in size. For example, in some embodiments, the semiconductor substrate 102 allows for fine pitch Si-to-Si interconnects and final line routing between the semiconductor substrate 102 and one or more dies 108 .
  • a dielectric film 105 is formed on the first surface A 1 and/or the second surface A 2 of the semiconductor substrate.
  • the dielectric film 105 can include, for example, silicon dioxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (Si 2 N 2 O), or other suitable dielectric materials.
  • the dielectric film 105 generally provides electrical isolation for electrically conductive material disposed on the semiconductor substrate to prevent current leakage between the electrically conductive material and the semiconductor material (e.g., silicon) of the semiconductor substrate.
  • One or more redistribution layers 106 are formed on the dielectric film 105 to route the electrical signals of the one or more dies 108 that are coupled to the semiconductor substrate 102 .
  • the one or more redistribution layers 106 can provide electrical routing between the one or more dies 108 and one or more package interconnect structures 114 disposed in the one or more channels 104 .
  • the one or more redistribution layers 106 generally include an electrically conductive material such as, for example, a metal (e.g., copper or aluminum). Other suitable electrically conductive materials can be used to form the one or more redistribution layers 106 in other embodiments.
  • the one or more redistribution layers 106 can include a variety of structures to route the electrical signals such as, for example, pads, lands, or traces.
  • a passivation layer comprising an electrically insulative material such as polyimide, for example, can be deposited on the one or more redistribution layers 106 and patterned to provide openings in the passivation layer to allow electrical coupling of the one or more dies 108 to the one or more redistribution layers 106 .
  • One or more dies 108 are coupled to the semiconductor substrate 102 .
  • the one or more dies 108 generally comprise a semiconductor material, such as, for example, silicon.
  • the one or more dies 108 and the semiconductor substrate 102 are fabricated using the same semiconductor material to reduce stress associated with heating/cooling mismatch of materials such as, for example, mismatched coefficients of thermal expansion (CTE).
  • CTE mismatched coefficients of thermal expansion
  • the one or more dies 108 can be coupled to the semiconductor substrate 102 using any suitable configuration.
  • the one or more dies 108 generally have an active side that includes a surface upon which a plurality of integrated circuit (IC) devices (not shown) such as transistors for logic and/or memory are formed and an inactive side that is disposed opposite to the active side.
  • IC integrated circuit
  • the active side of the one or more dies 108 is electrically coupled to the one or more redistribution layers 106 .
  • the active side of the one or more dies 108 is coupled to the one or more redistribution layers 106 using one or more bumps 110 in a flip-chip configuration, as can be seen.
  • the active side of the one or more dies 108 is electrically coupled to the one or more redistribution layers 106 using other structures, such as, for example, one or more bonding wires to provide a wire-bonding configuration.
  • the one or more bumps 110 generally comprise an electrically conductive material such as, for example, solder or other metal to route the electrical signals of the one or more dies 108 .
  • the one or more bumps 110 comprise lead, gold, tin, copper, or lead-free materials, or combinations thereof.
  • the one or more bumps 110 can have a variety of shapes including spherical, cylindrical, rectangular, or other shapes and can be formed using a bumping process, such as, for example, a controlled collapse chip connect (C4) process, stud-bumping, or other suitable process.
  • C4 controlled collapse chip connect
  • the components can include Electronic Compounds and integrated circuits (ICs).
  • ICs Electronic Compounds and integrated circuits
  • the components can include, for example, filter components, resistors, inductors, power amplifiers, capacitors, or packaged ICs.
  • Other active or passive components can be coupled to the semiconductor substrate 102 in other embodiments.
  • a molding compound 112 is disposed on the first surface A 1 of the semiconductor substrate 102 .
  • the molding compound 112 generally comprises an electrically insulative material, such as a thermosetting resin, that is disposed to protect the one or more dies 108 from moisture, oxidation, or chipping associated with handling.
  • the molding compound 112 is disposed to substantially encapsulate the one or more dies 108 and substantially fill a region between the one or more dies 108 and the semiconductor substrate 102 (e.g., between the one or more bumps 110 ), as can be seen.
  • the molding compound 112 can be selected to have a coefficient of thermal expansion (CTE) that is substantially the same or similar to a CTE of the semiconductor substrate 102 and/or the one or more dies 108 to reduce stress associated with mismatched CTE materials.
  • CTE coefficient of thermal expansion
  • one or more channels 104 are formed through the recessed surface (e.g., the second surface A 2 ) of the semiconductor substrate 102 .
  • the one or more channels 104 are filled with an electrically conductive and/or thermally conductive material such as a metal used to form one or more package interconnect structures 114 .
  • the one or more channels 104 generally provide an electrical and/or thermal pathway between the first surface A 1 and the second surface A 2 of the semiconductor substrate 102 .
  • the semiconductor substrate 102 comprises silicon
  • the one or more channels 104 are one or more through-silicon vias (TSVs).
  • TSVs through-silicon vias
  • the one or more channels 104 are tapered.
  • the one or more channels 104 can be straight or have other shapes in other embodiments.
  • One or more package interconnect structures 114 such as, for example, one or more solder balls or posts are disposed in the one or more channels 104 to further route the electrical signals of the one or more dies 108 .
  • the one or more package interconnect structures 114 are electrically coupled to the one or more redistribution layers 106 through the one or more channels 104 .
  • the one or more package interconnect structures 114 are directly coupled to the one or more redistribution layers 106 formed on the first surface A 1 of the semiconductor substrate 102 .
  • the one or more package interconnect structures 114 generally comprise an electrically conductive material such as a metal.
  • the one or more package interconnect structures 114 can be formed in a variety of shapes including spherical, planar, or polygon shapes and can be positioned in a variety of positions including in a row or in an array of multiple rows. Although the one or more package interconnect structures 114 are depicted on a peripheral portion of the semiconductor substrate 102 , the one or more package interconnect structures 114 can be disposed on or near a central portion of the semiconductor substrate 102 in other embodiments.
  • the package assembly 100 can be electrically coupled to another electronic device 150 using the one or more package interconnect structures 114 to further route the electrical signals of the one or more dies 108 to the other electronic device 150 .
  • the other electronic device 150 can include, for example, as a printed circuit board (PCB) (e.g., motherboard), a module, or another package assembly.
  • PCB printed circuit board
  • FIGS. 2A-2I schematically illustrate a package assembly subsequent to various process operations.
  • a package assembly 200 is depicted subsequent to forming a dielectric film 105 on at least the first surface A 1 of the semiconductor substrate 102 .
  • the dielectric film 105 is formed on the first surface A 1 and the second surface A 2 of the semiconductor substrate 102 , as can be seen.
  • the dielectric film 105 can be formed by using a deposition technique such as, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), and/or atomic layer deposition (ALD) to deposit a dielectric material such as, for example, silicon dioxide (SiO 2 ), silicon nitride (SiN), or silicon oxynitride (Si 2 N 2 O).
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • a dielectric material such as, for example, silicon dioxide (SiO 2 ), silicon nitride (SiN), or silicon oxynitride (Si 2 N 2 O).
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • Other suitable deposition techniques and/or dielectric materials can be used in other embodiments.
  • the package assembly 200 is depicted subsequent to forming one or more redistribution layers 106 on the dielectric film 105 that is disposed on the first surface A 1 .
  • the one or more redistribution layers 106 are generally formed by depositing an electrically conductive material on the dielectric film 105 .
  • the deposited electrically conductive material can be patterned and/or etched to provide routing structures (e.g., traces or pads) that route electrical signals of one or more dies (e.g., the one or more dies 108 of FIG. 2C ).
  • Multiple redistribution layers can be stacked on the semiconductor substrate 102 to provide desired routing of the electrical signals.
  • the package assembly 200 is depicted subsequent to electrically coupling one or more dies 108 to the one or more redistribution layers 106 .
  • the one or more dies 108 can be coupled to the semiconductor substrate 102 in a variety of configurations including, for example, flip-chip or wire-bonding configurations, or combinations thereof.
  • a flip-chip configuration an active surface of the die is coupled to the one or more redistribution layers 106 using one or more bumps 110 .
  • a wire-bonding configuration an inactive surface of the die is coupled to the semiconductor substrate 102 using an adhesive and an active surface of the die is electrically coupled to the one or more redistribution layers 106 using one or more bonding wires.
  • one or more bumps 110 are formed on the one or more dies 108 and bonded to the one or more redistribution layers 106 in a flip-chip configuration.
  • the one or more bumps 110 can be formed using a bumping process, such as, for example, a controlled collapse chip connect (C4) process, stud-bumping, or other suitable process.
  • C4 controlled collapse chip connect
  • the one or more bumps 110 can be formed on the one or more dies 108 when the one or more dies 108 are in either wafer or singulated form.
  • the one or more dies 108 can be attached to the semiconductor substrate 102 when the semiconductor substrate 102 is in either wafer or singulated form.
  • the package assembly 200 is depicted subsequent to forming a molding compound 112 on the semiconductor substrate 102 .
  • the molding compound 112 is generally formed by depositing an electrically insulative material to encapsulate the one or more dies 108 .
  • the molding compound 112 is formed by depositing a resin (e.g., a thermosetting resin) in solid form (e.g., a powder) into a mold and applying heat and/or pressure to fuse the resin.
  • a resin e.g., a thermosetting resin
  • solid form e.g., a powder
  • Other well-known techniques for forming the molding compound 112 can be used in other embodiments.
  • the molding compound 112 can be used in conjunction with an underfill layer (e.g., underfill 118 of FIG. 3 ), in some embodiments.
  • underfill material may be disposed between the one or more dies 108 and the semiconductor substrate 102 to encapsulate the one or more bumps 110 and the molding compound 112 can be disposed to encapsulate the one or more dies 108 and the underfill.
  • the molding compound 112 can be formed such that a surface of the one or more dies 108 is exposed to facilitate heat dissipation from the one or more dies 108 .
  • the package assembly 200 is depicted subsequent to recessing the second surface A 2 of the semiconductor substrate 102 .
  • the semiconductor substrate 102 can be recessed by a grinding process or an etch process to provide a semiconductor substrate 102 having a thickness between about 10 microns and about 500 microns. Other recessing techniques and thicknesses can be used in other embodiments.
  • the semiconductor substrate 102 is recessed to provide a thinner substrate that facilitates or enables the formation of one or more channels (e.g., one or more channels 104 ) that pass completely through the semiconductor substrate 102 .
  • the molding compound 112 is used as a mechanical carrier to support the semiconductor substrate 102 when the second surface A 2 of the semiconductor substrate 102 is being recessed and/or when the actions described in connection with FIGS. 2H and 2I are performed.
  • the package assembly 200 is depicted subsequent to forming one or more channels 104 through the semiconductor substrate 102 .
  • the one or more channels 104 are formed in/through the second surface A 2 of the semiconductor substrate 102 to expose the dielectric film 105 , as can be seen.
  • the one or more channels 104 can be formed by selectively removing the semiconductor material of the semiconductor substrate 102 .
  • the second surface A 2 of the semiconductor substrate can be patterned with a photoresist film or hard mask and etched by wet or dry etching processes to remove the semiconductor material from selected locations, as patterned.
  • the etch process is a selective etch and the dielectric film 105 serves as an etch stop layer.
  • the one or more channels 104 are formed subsequent to the molding compound 112 being formed.
  • the package assembly 200 is depicted subsequent to removing portions of the dielectric film 105 exposed in the one or more channels 104 in order to expose the one or more redistribution layers 106 .
  • Dielectric material of the dielectric film 105 can be selectively removed using, for example, a wet or dry patterning/etching process or a laser drilling process.
  • the electrically conductive material of the one or more redistribution layers 106 can serve as an etch/laser stop material.
  • the package assembly 200 is depicted subsequent to forming one or more under-ball metallization (UBM) structures 116 in the one or more channels 104 .
  • the one or more UBM structures 116 are generally formed by depositing an electrically conductive material using any suitable deposition process.
  • the one or more UBM structures 116 may serve as a buffer between material of the one or more package interconnect structures (e.g., the one or more package interconnect structures 114 of FIG. 2I ) and semiconductor material of the semiconductor substrate 102 .
  • the one or more UBM structures 116 are formed on the exposed portions of the one or more redistribution layers 106 in the one or more channels 104 and formed on the semiconductor substrate 102 within the one or more channels 104 . In other embodiments, the one or more UBM structures 116 are not formed at all (e.g., as can be seen in the package assembly 100 of FIG. 1 ). Forming the UBM structures 116 may provide increased joint reliability. Not forming the UBM structures 116 may simplify the fabrication process and/or reduce costs associated with the fabrication process.
  • the package assembly 200 is depicted subsequent to forming one or more package interconnect structures 114 in the one or more channels 104 .
  • the one or more package interconnect structures 114 are electrically coupled to the one or more redistribution layers 106 to route the electrical signals of the one or more dies 108 .
  • the one or more package interconnect structures 114 are formed on the one or more UBM structures 116 . In other embodiments, the one or more package interconnect structures 114 are formed directly on the one or more redistribution layers 106 .
  • the one or more package interconnect structures 114 can be formed according to a variety of suitable techniques including, for example, screen printing, electrical plating, and/or solder ball placement.
  • the one or more package interconnect structures 114 can be configured in a variety of ways including, for example, a ball-grid array (BGA) configuration.
  • BGA ball-grid array
  • FIG. 3 schematically illustrates another package assembly 300 that includes a recessed semiconductor substrate 102 .
  • the package assembly 300 is similar to the package assembly 200 depicted in FIG. 2I , except that the package assembly 300 further includes (i) an underfill 118 disposed between the one or more dies 108 and the semiconductor substrate 102 and (ii) an exposed backside surface of the one or more dies 108 .
  • the underfill 118 can be formed, for example, prior to forming the molding compound 112 (e.g., as shown in the package assembly 200 of FIG. 2C ).
  • the underfill 118 is deposited in liquid form by a liquid dispensing or injection process.
  • the underfill 118 can include, for example, an epoxy or other suitable electrically insulative material.
  • the underfill 118 generally increases adhesion between the one or more dies 108 and the semiconductor substrate 102 , provides additional electrical insulation between the one or more bumps 110 , and/or protects the one or more bumps 110 from moisture and oxidation.
  • the underfill 118 is used in conjunction with the molding compound 112 , as can be seen.
  • the molding compound 112 can be formed such that a backside surface of the one or more dies 108 is exposed to facilitate heat dissipation.
  • the molding compound 112 can be deposited using a mold that allows the molding compound 112 to be formed such that the backside surface of the one or more dies 108 is exposed.
  • the molding compound can be deposited to encapsulate the one or more dies and, subsequently, the molding compound can be recessed to expose the backside surface of the one or more dies 108 .
  • FIG. 4 is a process flow diagram of a method 400 to fabricate a package assembly (e.g., the package assembly 200 of FIG. 2I ) described herein.
  • the method 400 includes providing a semiconductor substrate (e.g., the semiconductor substrate 102 of FIG. 2A ).
  • the semiconductor substrate generally comprises a first surface (e.g., the first surface A 1 of FIG. 2A ) and a second surface (e.g., the second surface A 2 of FIG. 2A ) that is disposed opposite to the first surface.
  • the method 400 further includes forming a dielectric film (e.g., the dielectric film 105 of FIG. 2A ) on the semiconductor substrate.
  • the dielectric film can be formed according to techniques described in connection with FIG. 2A .
  • the method 400 further includes forming a redistribution layer (e.g., the one or more redistribution layers 106 of FIG. 2B ) on the semiconductor substrate.
  • the redistribution layer can be formed according to techniques described in connection with FIG. 2B .
  • the method 400 further includes electrically coupling one or more dies (e.g., the one or more dies 108 of FIG. 2C ) to the redistribution layer.
  • the one or more dies can be coupled according to techniques described in connection with FIG. 2C .
  • the method 400 further includes forming a molding compound (e.g., the molding compound 112 of FIG. 2D ) on the semiconductor substrate.
  • the molding compound can be formed according to techniques described in connection with FIG. 2D .
  • the method 400 further includes recessing a surface (e.g., the second surface A 2 of FIG. 2E ) of the semiconductor substrate.
  • the surface can be recessed according to techniques described in connection with FIG. 2E .
  • the method 400 further includes forming one or more channels (e.g., the one or more channels 104 of FIG. 2F and FIG. 2G ) through the semiconductor substrate.
  • the one or more channels can be formed according to techniques described in connection with FIGS. 2F and 2G .
  • the method 400 further includes forming one or more under bump metallization (UBM) structures (e.g., the one or more UBM structures 116 of FIG. 2H ) in the one or more channels.
  • UBM under bump metallization
  • the one or more UBM structures can be formed according to techniques described in connection with FIG. 2H .
  • the method 400 further includes forming one or more package interconnect structures (e.g., the one or more package interconnect structures 114 of FIG. 2I ) in the one or more channels.
  • the one or more package interconnect structures can be formed according to techniques described in connection with FIG. 2I .

Abstract

Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This disclosure is a continuation of U.S. application Ser. No. 13/007,059, filed Jan. 14, 2011, which claims priority to U.S. Provisional Patent Application No. 61/301,125, filed Feb. 3, 2010, and to U.S. Provisional Patent Application No. 61/316,282, filed Mar. 22, 2010, and to U.S. Provisional Patent Application No. 61/321,068, filed Apr. 5, 2010, and to U.S. Provisional Patent Application No. 61/325,189, filed Apr. 16, 2010. The disclosures of the applications referenced above are incorporated herein by reference in their entireties.
    • TECHNICAL FIELD
  • Embodiments of the present disclosure relate to the field of integrated circuits, and more particularly, to techniques, structures, and configurations of recessed semiconductor substrates for package assemblies.
    • BACKGROUND
  • The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
  • Integrated circuit devices, such as transistors, are formed on dies or chips that continue to scale in size to smaller dimensions. The shrinking dimensions of the dies are challenging conventional substrate fabrication and/or package assembly technologies that are currently used to route electrical signals to or from the semiconductor die. For example, laminate substrate technologies may not produce sufficiently small features on a substrate to correspond with the finer pitches of interconnects or other signal-routing features formed on the dies.
    • SUMMARY
  • In one embodiment, the present disclosure provides a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies.
  • In another embodiment, the present disclosure provides an apparatus comprising a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, a dielectric film formed on the first surface of the semiconductor substrate, a redistribution layer formed on the dielectric film, one or more dies electrically coupled to the redistribution layer, a molding compound formed on the semiconductor substrate, one or more channels formed through the second surface of the semiconductor substrate, and one or more package interconnect structures disposed in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer through the one or more channels to route electrical signals of the one or more dies.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Embodiments of the present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments herein are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.
  • FIG. 1 schematically illustrates a package assembly that includes a recessed semiconductor substrate.
  • FIGS. 2A-2I schematically illustrate a package assembly subsequent to various process operations.
  • FIG. 3 schematically illustrates another package assembly that includes a recessed semiconductor substrate.
  • FIG. 4 is a process flow diagram of a method to fabricate a package assembly described herein.
    •  DETAILED DESCRIPTION
  • Embodiments of the present disclosure describe techniques, structures, and configurations for a semiconductor substrate having a recessed region and associated package assemblies. In the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like numerals designate like parts throughout. Other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.
  • The description may use perspective-based descriptions such as up/down, over/under, and/or top/bottom. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.
  • For the purposes of the present disclosure, the phrase “A/B” means A or B. For the purposes of the present disclosure, the phrase “A and/or B” means “(A), (B), or (A and B).” For the purposes of the present disclosure, the phrase “at least one of A, B, and C” means “(A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).” For the purposes of the present disclosure, the phrase “(A)B” means “(B) or (AB)” that is, A is an optional element.
  • Various operations are described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
  • The description uses the phrases “in an embodiment,” “in embodiments,” or similar language, which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
  • FIG. 1 schematically illustrates a package assembly 100 that includes a recessed semiconductor substrate 102. The package assembly 100 generally includes a semiconductor substrate 102, which is a substrate or interposer that substantially comprises a semiconductor material such as, for example, silicon (Si). That is, the bulk of the material of the semiconductor substrate 102 is a semiconductor material. The semiconductor material can include crystalline and/or amorphous types of material. In the case of silicon, for example, the silicon can include single crystal and/or polysilicon types. In other embodiments, the semiconductor substrate 102 can include other semiconductor materials such as, for example, germanium, group III-V materials, or group II-VI materials, that may also benefit from the principles described herein.
  • The semiconductor substrate 102 includes a first surface, A1, and a second surface, A2, that is disposed opposite to the first surface A1. The first surface A1 and the second surface A2 generally refer to opposing surfaces of the semiconductor substrate 102 to facilitate the description of various configurations described herein.
  • According to various embodiments, a portion of the second surface A2 is recessed to provide a thickness, T, that facilitates the formation of one or more channels 104 through the semiconductor substrate 102. In some embodiments, the semiconductor substrate 102 is recessed to have a thickness T between about 10 microns and about 500 microns. The thickness is not limited to this range and other thicknesses, both greater and smaller, can be used in other embodiments.
  • The semiconductor substrate 102 is fabricated using technologies similar to those that are generally known to fabricate integrated circuit (IC) structures on a die or chip. For example, well-known patterning processes such as lithography/etch and/or deposition processes for fabricating IC devices on a die can be used to form features of the semiconductor substrate 102. By using semiconductor fabrication techniques, the semiconductor substrate 102 can include smaller features than other types of substrates such as laminate (e.g., organic) substrates. The semiconductor substrate 102 facilitates routing of electrical signals, such as input/output (I/O) and/or power/ground signals, for dies, which continue to shrink in size. For example, in some embodiments, the semiconductor substrate 102 allows for fine pitch Si-to-Si interconnects and final line routing between the semiconductor substrate 102 and one or more dies 108.
  • A dielectric film 105 is formed on the first surface A1 and/or the second surface A2 of the semiconductor substrate. The dielectric film 105 can include, for example, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (Si2N2O), or other suitable dielectric materials. The dielectric film 105 generally provides electrical isolation for electrically conductive material disposed on the semiconductor substrate to prevent current leakage between the electrically conductive material and the semiconductor material (e.g., silicon) of the semiconductor substrate.
  • One or more redistribution layers 106 are formed on the dielectric film 105 to route the electrical signals of the one or more dies 108 that are coupled to the semiconductor substrate 102. For example, the one or more redistribution layers 106 can provide electrical routing between the one or more dies 108 and one or more package interconnect structures 114 disposed in the one or more channels 104.
  • The one or more redistribution layers 106 generally include an electrically conductive material such as, for example, a metal (e.g., copper or aluminum). Other suitable electrically conductive materials can be used to form the one or more redistribution layers 106 in other embodiments.
  • The one or more redistribution layers 106 can include a variety of structures to route the electrical signals such as, for example, pads, lands, or traces. Although not depicted, a passivation layer comprising an electrically insulative material such as polyimide, for example, can be deposited on the one or more redistribution layers 106 and patterned to provide openings in the passivation layer to allow electrical coupling of the one or more dies 108 to the one or more redistribution layers 106.
  • One or more dies 108 are coupled to the semiconductor substrate 102. The one or more dies 108 generally comprise a semiconductor material, such as, for example, silicon. In an embodiment, the one or more dies 108 and the semiconductor substrate 102 are fabricated using the same semiconductor material to reduce stress associated with heating/cooling mismatch of materials such as, for example, mismatched coefficients of thermal expansion (CTE).
  • The one or more dies 108 can be coupled to the semiconductor substrate 102 using any suitable configuration. The one or more dies 108 generally have an active side that includes a surface upon which a plurality of integrated circuit (IC) devices (not shown) such as transistors for logic and/or memory are formed and an inactive side that is disposed opposite to the active side. The active side of the one or more dies 108 is electrically coupled to the one or more redistribution layers 106.
  • In some embodiments, the active side of the one or more dies 108 is coupled to the one or more redistribution layers 106 using one or more bumps 110 in a flip-chip configuration, as can be seen. In other embodiments, the active side of the one or more dies 108 is electrically coupled to the one or more redistribution layers 106 using other structures, such as, for example, one or more bonding wires to provide a wire-bonding configuration.
  • The one or more bumps 110 generally comprise an electrically conductive material such as, for example, solder or other metal to route the electrical signals of the one or more dies 108. According to various embodiments, the one or more bumps 110 comprise lead, gold, tin, copper, or lead-free materials, or combinations thereof. The one or more bumps 110 can have a variety of shapes including spherical, cylindrical, rectangular, or other shapes and can be formed using a bumping process, such as, for example, a controlled collapse chip connect (C4) process, stud-bumping, or other suitable process.
  • Although not shown, one or more other active or passive components can be mounted on the semiconductor substrate 102. The components can include Electronic Compounds and integrated circuits (ICs). The components can include, for example, filter components, resistors, inductors, power amplifiers, capacitors, or packaged ICs. Other active or passive components can be coupled to the semiconductor substrate 102 in other embodiments.
  • A molding compound 112 is disposed on the first surface A1 of the semiconductor substrate 102. The molding compound 112 generally comprises an electrically insulative material, such as a thermosetting resin, that is disposed to protect the one or more dies 108 from moisture, oxidation, or chipping associated with handling. In some embodiments, the molding compound 112 is disposed to substantially encapsulate the one or more dies 108 and substantially fill a region between the one or more dies 108 and the semiconductor substrate 102 (e.g., between the one or more bumps 110), as can be seen. The molding compound 112 can be selected to have a coefficient of thermal expansion (CTE) that is substantially the same or similar to a CTE of the semiconductor substrate 102 and/or the one or more dies 108 to reduce stress associated with mismatched CTE materials.
  • According to various embodiments, one or more channels 104, which may also be referred to as vias, are formed through the recessed surface (e.g., the second surface A2) of the semiconductor substrate 102. The one or more channels 104 are filled with an electrically conductive and/or thermally conductive material such as a metal used to form one or more package interconnect structures 114. The one or more channels 104 generally provide an electrical and/or thermal pathway between the first surface A1 and the second surface A2 of the semiconductor substrate 102. In an embodiment where the semiconductor substrate 102 comprises silicon, the one or more channels 104 are one or more through-silicon vias (TSVs). In some embodiments, the one or more channels 104 are tapered. The one or more channels 104 can be straight or have other shapes in other embodiments.
  • One or more package interconnect structures 114 such as, for example, one or more solder balls or posts are disposed in the one or more channels 104 to further route the electrical signals of the one or more dies 108. The one or more package interconnect structures 114 are electrically coupled to the one or more redistribution layers 106 through the one or more channels 104. In the depicted embodiment of FIG. 1, the one or more package interconnect structures 114 are directly coupled to the one or more redistribution layers 106 formed on the first surface A1 of the semiconductor substrate 102.
  • The one or more package interconnect structures 114 generally comprise an electrically conductive material such as a metal. The one or more package interconnect structures 114 can be formed in a variety of shapes including spherical, planar, or polygon shapes and can be positioned in a variety of positions including in a row or in an array of multiple rows. Although the one or more package interconnect structures 114 are depicted on a peripheral portion of the semiconductor substrate 102, the one or more package interconnect structures 114 can be disposed on or near a central portion of the semiconductor substrate 102 in other embodiments.
  • The package assembly 100 can be electrically coupled to another electronic device 150 using the one or more package interconnect structures 114 to further route the electrical signals of the one or more dies 108 to the other electronic device 150. The other electronic device 150 can include, for example, as a printed circuit board (PCB) (e.g., motherboard), a module, or another package assembly.
  • FIGS. 2A-2I schematically illustrate a package assembly subsequent to various process operations. Referring to FIG. 2A, a package assembly 200 is depicted subsequent to forming a dielectric film 105 on at least the first surface A1 of the semiconductor substrate 102. In embodiments, the dielectric film 105 is formed on the first surface A1 and the second surface A2 of the semiconductor substrate 102, as can be seen. The dielectric film 105 can be formed by using a deposition technique such as, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), and/or atomic layer deposition (ALD) to deposit a dielectric material such as, for example, silicon dioxide (SiO2), silicon nitride (SiN), or silicon oxynitride (Si2N2O). Other suitable deposition techniques and/or dielectric materials can be used in other embodiments.
  • Referring to FIG. 2B, the package assembly 200 is depicted subsequent to forming one or more redistribution layers 106 on the dielectric film 105 that is disposed on the first surface A1. The one or more redistribution layers 106 are generally formed by depositing an electrically conductive material on the dielectric film 105. The deposited electrically conductive material can be patterned and/or etched to provide routing structures (e.g., traces or pads) that route electrical signals of one or more dies (e.g., the one or more dies 108 of FIG. 2C). Multiple redistribution layers can be stacked on the semiconductor substrate 102 to provide desired routing of the electrical signals.
  • Referring to FIG. 2C, the package assembly 200 is depicted subsequent to electrically coupling one or more dies 108 to the one or more redistribution layers 106. The one or more dies 108 can be coupled to the semiconductor substrate 102 in a variety of configurations including, for example, flip-chip or wire-bonding configurations, or combinations thereof. In a flip-chip configuration, an active surface of the die is coupled to the one or more redistribution layers 106 using one or more bumps 110. In a wire-bonding configuration, an inactive surface of the die is coupled to the semiconductor substrate 102 using an adhesive and an active surface of the die is electrically coupled to the one or more redistribution layers 106 using one or more bonding wires.
  • In the depicted embodiment of FIG. 2C, one or more bumps 110 are formed on the one or more dies 108 and bonded to the one or more redistribution layers 106 in a flip-chip configuration. The one or more bumps 110 can be formed using a bumping process, such as, for example, a controlled collapse chip connect (C4) process, stud-bumping, or other suitable process. The one or more bumps 110 can be formed on the one or more dies 108 when the one or more dies 108 are in either wafer or singulated form. The one or more dies 108 can be attached to the semiconductor substrate 102 when the semiconductor substrate 102 is in either wafer or singulated form.
  • Referring to FIG. 2D, the package assembly 200 is depicted subsequent to forming a molding compound 112 on the semiconductor substrate 102. The molding compound 112 is generally formed by depositing an electrically insulative material to encapsulate the one or more dies 108. According to various embodiments, the molding compound 112 is formed by depositing a resin (e.g., a thermosetting resin) in solid form (e.g., a powder) into a mold and applying heat and/or pressure to fuse the resin. Other well-known techniques for forming the molding compound 112 can be used in other embodiments.
  • The molding compound 112 can be used in conjunction with an underfill layer (e.g., underfill 118 of FIG. 3), in some embodiments. For example, underfill material may be disposed between the one or more dies 108 and the semiconductor substrate 102 to encapsulate the one or more bumps 110 and the molding compound 112 can be disposed to encapsulate the one or more dies 108 and the underfill. In some embodiments, the molding compound 112 can be formed such that a surface of the one or more dies 108 is exposed to facilitate heat dissipation from the one or more dies 108.
  • Referring to FIG. 2E, the package assembly 200 is depicted subsequent to recessing the second surface A2 of the semiconductor substrate 102. The semiconductor substrate 102 can be recessed by a grinding process or an etch process to provide a semiconductor substrate 102 having a thickness between about 10 microns and about 500 microns. Other recessing techniques and thicknesses can be used in other embodiments. The semiconductor substrate 102 is recessed to provide a thinner substrate that facilitates or enables the formation of one or more channels (e.g., one or more channels 104) that pass completely through the semiconductor substrate 102. According to various embodiments, the molding compound 112 is used as a mechanical carrier to support the semiconductor substrate 102 when the second surface A2 of the semiconductor substrate 102 is being recessed and/or when the actions described in connection with FIGS. 2H and 2I are performed.
  • Referring to FIG. 2F, the package assembly 200 is depicted subsequent to forming one or more channels 104 through the semiconductor substrate 102. The one or more channels 104 are formed in/through the second surface A2 of the semiconductor substrate 102 to expose the dielectric film 105, as can be seen. The one or more channels 104 can be formed by selectively removing the semiconductor material of the semiconductor substrate 102. For example, the second surface A2 of the semiconductor substrate can be patterned with a photoresist film or hard mask and etched by wet or dry etching processes to remove the semiconductor material from selected locations, as patterned. In some embodiments, the etch process is a selective etch and the dielectric film 105 serves as an etch stop layer. According to various embodiments, the one or more channels 104 are formed subsequent to the molding compound 112 being formed.
  • Referring to FIG. 2G, the package assembly 200 is depicted subsequent to removing portions of the dielectric film 105 exposed in the one or more channels 104 in order to expose the one or more redistribution layers 106. Dielectric material of the dielectric film 105 can be selectively removed using, for example, a wet or dry patterning/etching process or a laser drilling process. The electrically conductive material of the one or more redistribution layers 106 can serve as an etch/laser stop material.
  • Referring to FIG. 2H, the package assembly 200 is depicted subsequent to forming one or more under-ball metallization (UBM) structures 116 in the one or more channels 104. The one or more UBM structures 116 are generally formed by depositing an electrically conductive material using any suitable deposition process. The one or more UBM structures 116 may serve as a buffer between material of the one or more package interconnect structures (e.g., the one or more package interconnect structures 114 of FIG. 2I) and semiconductor material of the semiconductor substrate 102. In some embodiments, the one or more UBM structures 116 are formed on the exposed portions of the one or more redistribution layers 106 in the one or more channels 104 and formed on the semiconductor substrate 102 within the one or more channels 104. In other embodiments, the one or more UBM structures 116 are not formed at all (e.g., as can be seen in the package assembly 100 of FIG. 1). Forming the UBM structures 116 may provide increased joint reliability. Not forming the UBM structures 116 may simplify the fabrication process and/or reduce costs associated with the fabrication process.
  • Referring to FIG. 2I, the package assembly 200 is depicted subsequent to forming one or more package interconnect structures 114 in the one or more channels 104. The one or more package interconnect structures 114 are electrically coupled to the one or more redistribution layers 106 to route the electrical signals of the one or more dies 108. In some embodiments, the one or more package interconnect structures 114 are formed on the one or more UBM structures 116. In other embodiments, the one or more package interconnect structures 114 are formed directly on the one or more redistribution layers 106.
  • The one or more package interconnect structures 114 can be formed according to a variety of suitable techniques including, for example, screen printing, electrical plating, and/or solder ball placement. The one or more package interconnect structures 114 can be configured in a variety of ways including, for example, a ball-grid array (BGA) configuration.
  • FIG. 3 schematically illustrates another package assembly 300 that includes a recessed semiconductor substrate 102. The package assembly 300 is similar to the package assembly 200 depicted in FIG. 2I, except that the package assembly 300 further includes (i) an underfill 118 disposed between the one or more dies 108 and the semiconductor substrate 102 and (ii) an exposed backside surface of the one or more dies 108.
  • The underfill 118 can be formed, for example, prior to forming the molding compound 112 (e.g., as shown in the package assembly 200 of FIG. 2C). According to various embodiments, the underfill 118 is deposited in liquid form by a liquid dispensing or injection process. The underfill 118 can include, for example, an epoxy or other suitable electrically insulative material. The underfill 118 generally increases adhesion between the one or more dies 108 and the semiconductor substrate 102, provides additional electrical insulation between the one or more bumps 110, and/or protects the one or more bumps 110 from moisture and oxidation. In some embodiments, the underfill 118 is used in conjunction with the molding compound 112, as can be seen.
  • The molding compound 112 can be formed such that a backside surface of the one or more dies 108 is exposed to facilitate heat dissipation. In one embodiment, the molding compound 112 can be deposited using a mold that allows the molding compound 112 to be formed such that the backside surface of the one or more dies 108 is exposed. In other embodiments, the molding compound can be deposited to encapsulate the one or more dies and, subsequently, the molding compound can be recessed to expose the backside surface of the one or more dies 108.
  • FIG. 4 is a process flow diagram of a method 400 to fabricate a package assembly (e.g., the package assembly 200 of FIG. 2I) described herein. At 402, the method 400 includes providing a semiconductor substrate (e.g., the semiconductor substrate 102 of FIG. 2A). The semiconductor substrate generally comprises a first surface (e.g., the first surface A1 of FIG. 2A) and a second surface (e.g., the second surface A2 of FIG. 2A) that is disposed opposite to the first surface.
  • At 404, the method 400 further includes forming a dielectric film (e.g., the dielectric film 105 of FIG. 2A) on the semiconductor substrate. The dielectric film can be formed according to techniques described in connection with FIG. 2A.
  • At 406, the method 400 further includes forming a redistribution layer (e.g., the one or more redistribution layers 106 of FIG. 2B) on the semiconductor substrate. The redistribution layer can be formed according to techniques described in connection with FIG. 2B.
  • At 408, the method 400 further includes electrically coupling one or more dies (e.g., the one or more dies 108 of FIG. 2C) to the redistribution layer. The one or more dies can be coupled according to techniques described in connection with FIG. 2C.
  • At 410, the method 400 further includes forming a molding compound (e.g., the molding compound 112 of FIG. 2D) on the semiconductor substrate. The molding compound can be formed according to techniques described in connection with FIG. 2D.
  • At 412, the method 400 further includes recessing a surface (e.g., the second surface A2 of FIG. 2E) of the semiconductor substrate. The surface can be recessed according to techniques described in connection with FIG. 2E.
  • At 414, the method 400 further includes forming one or more channels (e.g., the one or more channels 104 of FIG. 2F and FIG. 2G) through the semiconductor substrate. The one or more channels can be formed according to techniques described in connection with FIGS. 2F and 2G.
  • At 416, the method 400 further includes forming one or more under bump metallization (UBM) structures (e.g., the one or more UBM structures 116 of FIG. 2H) in the one or more channels. The one or more UBM structures can be formed according to techniques described in connection with FIG. 2H.
  • At 418, the method 400 further includes forming one or more package interconnect structures (e.g., the one or more package interconnect structures 114 of FIG. 2I) in the one or more channels. The one or more package interconnect structures can be formed according to techniques described in connection with FIG. 2I.
  • Although certain embodiments have been illustrated and described herein, a wide variety of alternate and/or equivalent embodiments or implementations calculated to achieve the same purposes may be substituted for the embodiments illustrated and described without departing from the scope of the present disclosure. This disclosure is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, it is manifestly intended that embodiments described herein be limited only by the claims and the equivalents thereof.

Claims (8)

1. An apparatus comprising:
a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface;
a dielectric film formed between the first surface of the semiconductor substrate and a redistribution layer;
the redistribution layer formed on the dielectric film, only one side of the redistribution layer contacting with the dielectric film;
one or more dies electrically coupled to the redistribution layer;
a molding compound formed on the semiconductor substrate;
one or more channels formed through the second surface of the semiconductor substrate, the one or more channels having a width at the second surface that is at least as large as a largest width of a package interconnect structure; and
one or more of the package interconnect structures disposed in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer through the one or more channels to route electrical signals of the one or more dies.
2. The apparatus of claim 1, wherein the one or more dies are coupled to the redistribution layer in a flip-chip configuration using one or more bumps.
3. The apparatus of claim 1, wherein the molding compound substantially encapsulates the one or more dies.
4. The apparatus of claim 1, wherein the second surface of the semiconductor substrate is recessed such that the semiconductor substrate has a thickness between about 50 microns and about 300 microns.
5. The apparatus of claim 1, further comprising:
an underfill layer formed between (i) the one or more dies and (ii) the semiconductor substrate.
6. The apparatus of claim 1, wherein:
the one or more package interconnect structures comprise solder balls to route electrical signals of the one or more dies; and
the redistribution layer comprises an electrically conductive material to route the electrical signals of the one or more dies.
7. The apparatus of claim 1, wherein:
the semiconductor substrate comprises silicon;
the one or more dies comprise silicon; and
the one or more channels comprise one or more through-silicon vias.
8. The apparatus of claim 7, wherein:
the molding compound and the semiconductor substrate have a coefficient of thermal expansion (CTE) that is the same or substantially similar; and
the one or more through-silicon vias are tapered.
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US13/015,988 Expired - Fee Related US9034730B2 (en) 2010-02-03 2011-01-28 Recessed semiconductor substrates and associated techniques
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9312149B2 (en) 2011-11-16 2016-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming chip-on-wafer assembly
US10032746B2 (en) 2014-09-05 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having recessed edges and method of manufacture

Families Citing this family (87)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7548752B2 (en) 2004-12-22 2009-06-16 Qualcomm Incorporated Feedback to support restrictive reuse
US20110175218A1 (en) 2010-01-18 2011-07-21 Shiann-Ming Liou Package assembly having a semiconductor substrate
US20130026609A1 (en) * 2010-01-18 2013-01-31 Marvell World Trade Ltd. Package assembly including a semiconductor substrate with stress relief structure
US20110186960A1 (en) 2010-02-03 2011-08-04 Albert Wu Techniques and configurations for recessed semiconductor substrates
US8188591B2 (en) * 2010-07-13 2012-05-29 International Business Machines Corporation Integrated structures of high performance active devices and passive devices
US8884431B2 (en) * 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US8936966B2 (en) * 2012-02-08 2015-01-20 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods for semiconductor devices
US8836433B2 (en) 2011-05-10 2014-09-16 Skyworks Solutions, Inc. Apparatus and methods for electronic amplification
US8546900B2 (en) * 2011-06-09 2013-10-01 Optiz, Inc. 3D integration microelectronic assembly for integrated circuit devices
US8409923B2 (en) * 2011-06-15 2013-04-02 Stats Chippac Ltd. Integrated circuit packaging system with underfill and method of manufacture thereof
US9449941B2 (en) 2011-07-07 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Connecting function chips to a package to form package-on-package
US20130075892A1 (en) * 2011-09-27 2013-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Three Dimensional Integrated Circuit Fabrication
KR101346485B1 (en) 2011-12-29 2014-01-10 주식회사 네패스 Stacked semiconductor package and method of manufacturing the same
US9147670B2 (en) * 2012-02-24 2015-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Functional spacer for SIP and methods for forming the same
US9881894B2 (en) 2012-03-08 2018-01-30 STATS ChipPAC Pte. Ltd. Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration
US9613917B2 (en) 2012-03-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) device with integrated passive device in a via
US8741691B2 (en) * 2012-04-20 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating three dimensional integrated circuit
US9236277B2 (en) 2012-08-10 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit with a thermally conductive underfill and methods of forming same
US8810006B2 (en) * 2012-08-10 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer system and method
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US8975726B2 (en) 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
US9391041B2 (en) 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
US9799592B2 (en) * 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
US9165878B2 (en) * 2013-03-14 2015-10-20 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
US9087777B2 (en) 2013-03-14 2015-07-21 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
CN104217967A (en) * 2013-05-31 2014-12-17 宏启胜精密电子(秦皇岛)有限公司 Semiconductor device and manufacturing method thereof
KR102094924B1 (en) * 2013-06-27 2020-03-30 삼성전자주식회사 Semiconductor packages having through electrodes and methods for fabricating the same
US20150001694A1 (en) * 2013-07-01 2015-01-01 Texas Instruments Incorporated Integrated circuit device package with thermal isolation
US20150243881A1 (en) * 2013-10-15 2015-08-27 Robert L. Sankman Magnetic shielded integrated circuit package
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9679839B2 (en) 2013-10-30 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
CN103560090B (en) * 2013-10-31 2016-06-15 中国科学院微电子研究所 A kind of manufacture method of the radiator structure for PoP encapsulation
DE102013223847A1 (en) * 2013-11-21 2015-05-21 Robert Bosch Gmbh Carrier substrate for a thermoelectric generator and electrical circuit
EP2881753B1 (en) 2013-12-05 2019-03-06 ams AG Optical sensor arrangement and method of producing an optical sensor arrangement
EP2881983B1 (en) * 2013-12-05 2019-09-18 ams AG Interposer-chip-arrangement for dense packaging of chips
US20150237732A1 (en) * 2014-02-18 2015-08-20 Qualcomm Incorporated Low-profile package with passive device
US9230936B2 (en) 2014-03-04 2016-01-05 Qualcomm Incorporated Integrated device comprising high density interconnects and redistribution layers
JP6513966B2 (en) * 2014-03-06 2019-05-15 ローム株式会社 Semiconductor device
CN105206602B (en) * 2014-06-16 2020-07-24 联想(北京)有限公司 Integrated module stacking structure and electronic equipment
US9666559B2 (en) * 2014-09-05 2017-05-30 Invensas Corporation Multichip modules and methods of fabrication
US9496154B2 (en) 2014-09-16 2016-11-15 Invensas Corporation Use of underfill tape in microelectronic components, and microelectronic components with cavities coupled to through-substrate vias
DE112014003166B4 (en) * 2014-12-19 2021-09-23 Intel Corporation Stacked semiconductor device assembly having improved interconnect bandwidth and method of making such an assembly
TWI562299B (en) * 2015-03-23 2016-12-11 Siliconware Precision Industries Co Ltd Electronic package and the manufacture thereof
JP2018518043A (en) * 2015-04-13 2018-07-05 ロイヨール コーポレーション Support and removal of flexible substrates
US9613931B2 (en) 2015-04-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) having dummy dies and methods of making the same
KR101672640B1 (en) * 2015-06-23 2016-11-03 앰코 테크놀로지 코리아 주식회사 Semiconductor device
US9865568B2 (en) * 2015-06-25 2018-01-09 Intel Corporation Integrated circuit structures with recessed conductive contacts for package on package
US9601405B2 (en) 2015-07-22 2017-03-21 Avago Technologies General Ip (Singapore) Pte. Ltd. Semiconductor package with an enhanced thermal pad
US9449935B1 (en) * 2015-07-27 2016-09-20 Inotera Memories, Inc. Wafer level package and fabrication method thereof
US9589865B2 (en) 2015-07-28 2017-03-07 Avago Technologies General Ip (Singapore) Pte. Ltd. Power amplifier die having multiple amplifiers
WO2017039275A1 (en) * 2015-08-31 2017-03-09 한양대학교 산학협력단 Semiconductor package structure and method for manufacturing same
KR101923659B1 (en) 2015-08-31 2019-02-22 삼성전자주식회사 Semiconductor package structure, and method of fabricating the same
JP2017073472A (en) * 2015-10-07 2017-04-13 株式会社ディスコ Semiconductor device manufacturing method
US10887439B2 (en) * 2015-12-22 2021-01-05 Intel Corporation Microelectronic devices designed with integrated antennas on a substrate
CN105514087A (en) * 2016-01-26 2016-04-20 中芯长电半导体（江阴）有限公司 Double-faced fan-out type wafer-level packaging method and packaging structure
CN105810590A (en) * 2016-03-18 2016-07-27 中国电子科技集团公司第二十六研究所 Acoustic surface wave filter wafer bonding and packaging technology
US10236245B2 (en) * 2016-03-23 2019-03-19 Dyi-chung Hu Package substrate with embedded circuit
US9842818B2 (en) 2016-03-28 2017-12-12 Intel Corporation Variable ball height on ball grid array packages by solder paste transfer
US10325828B2 (en) * 2016-03-30 2019-06-18 Qorvo Us, Inc. Electronics package with improved thermal performance
WO2017189224A1 (en) 2016-04-26 2017-11-02 Linear Technology Corporation Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
CN109478516B (en) * 2016-04-29 2023-06-13 库利克和索夫工业公司 Connecting an electronic component to a substrate
US20170338128A1 (en) * 2016-05-17 2017-11-23 Powertech Technology Inc. Manufacturing method of package structure
KR102506697B1 (en) * 2016-05-18 2023-03-08 에스케이하이닉스 주식회사 Semiconductor package including through mold ball connectors
WO2018004686A1 (en) * 2016-07-01 2018-01-04 Intel Corporation Device, method and system for providing recessed interconnect structures of a substrate
WO2018009146A1 (en) * 2016-07-07 2018-01-11 Agency For Science, Technology And Research Semiconductor packaging structure and method of forming the same
US10319694B2 (en) * 2016-08-10 2019-06-11 Qualcomm Incorporated Semiconductor assembly and method of making same
CN106298759A (en) * 2016-09-09 2017-01-04 宜确半导体（苏州）有限公司 A kind of radio-frequency power amplifier module and RF front-end module
CN106298824B (en) * 2016-09-20 2019-08-20 上海集成电路研发中心有限公司 A kind of cmos image sensor chip and preparation method thereof
US10304799B2 (en) * 2016-12-28 2019-05-28 Intel Corporation Land grid array package extension
US10438931B2 (en) * 2017-01-16 2019-10-08 Powertech Technology Inc. Package structure and manufacturing method thereof
CN108400118A (en) * 2017-02-06 2018-08-14 钰桥半导体股份有限公司 The semiconductor subassembly and preparation method thereof that three-dimensional is integrated
CN108400117A (en) * 2017-02-06 2018-08-14 钰桥半导体股份有限公司 The heat-dissipating gain-type semiconductor subassembly and preparation method thereof that three-dimensional is integrated
US10854568B2 (en) * 2017-04-07 2020-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
US10522449B2 (en) 2017-04-10 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
DE102017123449B4 (en) 2017-04-10 2023-12-28 Taiwan Semiconductor Manufacturing Co. Ltd. Housing with Si-substrate-free intermediate piece and training process
US11172581B2 (en) * 2017-06-29 2021-11-09 Intel Corporation Multi-planar circuit board having reduced z-height
US10403602B2 (en) * 2017-06-29 2019-09-03 Intel IP Corporation Monolithic silicon bridge stack including a hybrid baseband die supporting processors and memory
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US10755979B2 (en) * 2018-10-31 2020-08-25 Ningbo Semiconductor International Corporation Wafer-level packaging methods using a photolithographic bonding material
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
CN111952268A (en) * 2019-05-15 2020-11-17 西部数据技术公司 Multi-module integrated interposer and semiconductor device formed thereby
CN113140520A (en) * 2020-01-19 2021-07-20 江苏长电科技股份有限公司 Packaging structure and forming method thereof
EP3876683A1 (en) * 2020-03-05 2021-09-08 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Heat removal mechanism for stack-based electronic device with process control component and processing components
US11393763B2 (en) * 2020-05-28 2022-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out (info) package structure and method
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component
KR20220034337A (en) 2020-09-11 2022-03-18 삼성전자주식회사 Semiconductor device
TWI768552B (en) * 2020-11-20 2022-06-21 力成科技股份有限公司 Stacked semiconductor package and packaging method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557066A (en) * 1993-04-30 1996-09-17 Lsi Logic Corporation Molding compounds having a controlled thermal coefficient of expansion, and their uses in packaging electronic devices
US6359790B1 (en) * 1999-07-01 2002-03-19 Infineon Technologies Ag Multichip module having a silicon carrier substrate
US20100109142A1 (en) * 2008-10-23 2010-05-06 United Test And Assembly Center Ltd. Interposer for semiconductor package

Family Cites Families (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US1264411A (en) 1917-12-20 1918-04-30 Kirstein Sons Company E Opthalmic mounting.
US5200362A (en) 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US5291062A (en) * 1993-03-01 1994-03-01 Motorola, Inc. Area array semiconductor device having a lid with functional contacts
US5659203A (en) * 1995-06-07 1997-08-19 International Business Machines Corporation Reworkable polymer chip encapsulant
JP2830903B2 (en) 1995-07-21 1998-12-02 日本電気株式会社 Method for manufacturing semiconductor device
US6046499A (en) 1996-03-27 2000-04-04 Kabushiki Kaisha Toshiba Heat transfer configuration for a semiconductor device
US6127460A (en) 1997-12-02 2000-10-03 Sumitomo Bakelite Co., Ltd. Liquid epoxy resin potting material
US6833613B1 (en) 1997-12-18 2004-12-21 Micron Technology, Inc. Stacked semiconductor package having laser machined contacts
JP3109477B2 (en) * 1998-05-26 2000-11-13 日本電気株式会社 Multi-chip module
US5977640A (en) 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
JP3602968B2 (en) 1998-08-18 2004-12-15 沖電気工業株式会社 Semiconductor device and substrate connection structure thereof
US6222246B1 (en) * 1999-01-08 2001-04-24 Intel Corporation Flip-chip having an on-chip decoupling capacitor
DE10004647C1 (en) 2000-02-03 2001-07-26 Infineon Technologies Ag Method for producing a semiconductor component with a multichip module and a silicon carrier substrate
US6356453B1 (en) * 2000-06-29 2002-03-12 Amkor Technology, Inc. Electronic package having flip chip integrated circuit and passive chip component
US6525413B1 (en) 2000-07-12 2003-02-25 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
US20020070443A1 (en) * 2000-12-08 2002-06-13 Xiao-Chun Mu Microelectronic package having an integrated heat sink and build-up layers
US6787916B2 (en) * 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
JP2003188507A (en) 2001-12-18 2003-07-04 Mitsubishi Electric Corp Semiconductor integrated circuit and printed circuit board for mounting the same
JP4044769B2 (en) * 2002-02-22 2008-02-06 富士通株式会社 Semiconductor device substrate, manufacturing method thereof, and semiconductor package
US7010854B2 (en) 2002-04-10 2006-03-14 Formfactor, Inc. Re-assembly process for MEMS structures
US6798057B2 (en) * 2002-11-05 2004-09-28 Micron Technology, Inc. Thin stacked ball-grid array package
JP4115326B2 (en) 2003-04-15 2008-07-09 新光電気工業株式会社 Manufacturing method of semiconductor package
US7518158B2 (en) * 2003-12-09 2009-04-14 Cree, Inc. Semiconductor light emitting devices and submounts
JP4865197B2 (en) * 2004-06-30 2012-02-01 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US7268012B2 (en) * 2004-08-31 2007-09-11 Micron Technology, Inc. Methods for fabrication of thin semiconductor assemblies including redistribution layers and packages and assemblies formed thereby
TWI249231B (en) 2004-12-10 2006-02-11 Phoenix Prec Technology Corp Flip-chip package structure with embedded chip in substrate
US7271482B2 (en) * 2004-12-30 2007-09-18 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
TWI241697B (en) 2005-01-06 2005-10-11 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
DE102005014049B4 (en) 2005-03-23 2010-11-25 Diana Diehl Holding device as well as pocket using the same ones
KR20080021703A (en) 2005-06-29 2008-03-07 코닌클리케 필립스 일렉트로닉스 엔.브이. Method of manufacturing an assembly and assembly
TW200707676A (en) * 2005-08-09 2007-02-16 Chipmos Technologies Inc Thin IC package for improving heat dissipation from chip backside
US7327029B2 (en) 2005-09-27 2008-02-05 Agere Systems, Inc. Integrated circuit device incorporating metallurigical bond to enhance thermal conduction to a heat sink
US8044412B2 (en) * 2006-01-20 2011-10-25 Taiwan Semiconductor Manufacturing Company, Ltd Package for a light emitting element
US7808075B1 (en) * 2006-02-07 2010-10-05 Marvell International Ltd. Integrated circuit devices with ESD and I/O protection
WO2007115371A1 (en) 2006-04-10 2007-10-18 Epitactix Pty Ltd Method, apparatus and resulting structures in the manufacture of semiconductors
KR100800478B1 (en) 2006-07-18 2008-02-04 삼성전자주식회사 Stack type semiconductor package and method of fabricating the same
JP5064768B2 (en) * 2006-11-22 2012-10-31 新光電気工業株式会社 Electronic component and method for manufacturing electronic component
JP2008166373A (en) 2006-12-27 2008-07-17 Nec Electronics Corp Semiconductor device and its manufacturing method
KR100827667B1 (en) * 2007-01-16 2008-05-07 삼성전자주식회사 Semiconductor package having semiconductor chip in substrate and method of fabricating the same
JP4970979B2 (en) * 2007-02-20 2012-07-11 ルネサスエレクトロニクス株式会社 Semiconductor device
WO2008105535A1 (en) * 2007-03-01 2008-09-04 Nec Corporation Semiconductor device and method for manufacturing the same
TWI345823B (en) 2007-03-21 2011-07-21 Powertech Technology Inc Semiconductor package with wire-bonding connections
TWI351751B (en) 2007-06-22 2011-11-01 Ind Tech Res Inst Self-aligned wafer or chip structure, self-aligned
US7799608B2 (en) * 2007-08-01 2010-09-21 Advanced Micro Devices, Inc. Die stacking apparatus and method
KR101329355B1 (en) 2007-08-31 2013-11-20 삼성전자주식회사 stack-type semicondoctor package, method of forming the same and electronic system including the same
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
CN101878527B (en) 2007-11-30 2012-09-26 斯盖沃克斯瑟路申斯公司 Wafer level packaging using flip chip mounting
US20090170241A1 (en) * 2007-12-26 2009-07-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
US7741194B2 (en) 2008-01-04 2010-06-22 Freescale Semiconductor, Inc. Removable layer manufacturing method
US20090212420A1 (en) * 2008-02-22 2009-08-27 Harry Hedler integrated circuit device and method for fabricating same
JP2009231584A (en) 2008-03-24 2009-10-08 Japan Gore Tex Inc Method of manufacturing led substrate and the led substrate
US20090243100A1 (en) * 2008-03-27 2009-10-01 Jotaro Akiyama Methods to Form a Three-Dimensionally Curved Pad in a Substrate and Integrated Circuits Incorporating such a Substrate
US8093696B2 (en) * 2008-05-16 2012-01-10 Qimonda Ag Semiconductor device
US7919851B2 (en) * 2008-06-05 2011-04-05 Powertech Technology Inc. Laminate substrate and semiconductor package utilizing the substrate
KR101481577B1 (en) 2008-09-29 2015-01-13 삼성전자주식회사 Semiconductor package having ink-jet type dam and method of manufacturing the same
US8030780B2 (en) 2008-10-16 2011-10-04 Micron Technology, Inc. Semiconductor substrates with unitary vias and via terminals, and associated systems and methods
US8704350B2 (en) 2008-11-13 2014-04-22 Samsung Electro-Mechanics Co., Ltd. Stacked wafer level package and method of manufacturing the same
US7858441B2 (en) 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
US7786008B2 (en) * 2008-12-12 2010-08-31 Stats Chippac Ltd. Integrated circuit packaging system having through silicon vias with partial depth metal fill regions and method of manufacture thereof
TWI499024B (en) 2009-01-07 2015-09-01 Advanced Semiconductor Eng Package-on-package device, semiconductor package and method for manufacturing the same
US8378383B2 (en) * 2009-03-25 2013-02-19 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer between stacked semiconductor die
US20110175218A1 (en) 2010-01-18 2011-07-21 Shiann-Ming Liou Package assembly having a semiconductor substrate
US20110186960A1 (en) 2010-02-03 2011-08-04 Albert Wu Techniques and configurations for recessed semiconductor substrates
US8378477B2 (en) * 2010-09-14 2013-02-19 Stats Chippac Ltd. Integrated circuit packaging system with film encapsulation and method of manufacture thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557066A (en) * 1993-04-30 1996-09-17 Lsi Logic Corporation Molding compounds having a controlled thermal coefficient of expansion, and their uses in packaging electronic devices
US6359790B1 (en) * 1999-07-01 2002-03-19 Infineon Technologies Ag Multichip module having a silicon carrier substrate
US20100109142A1 (en) * 2008-10-23 2010-05-06 United Test And Assembly Center Ltd. Interposer for semiconductor package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9312149B2 (en) 2011-11-16 2016-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming chip-on-wafer assembly
US10032746B2 (en) 2014-09-05 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having recessed edges and method of manufacture

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