US20110175218A1 - Package assembly having a semiconductor substrate - Google Patents

Package assembly having a semiconductor substrate Download PDF

Info

Publication number
US20110175218A1
US20110175218A1 US12/973,249 US97324910A US2011175218A1 US 20110175218 A1 US20110175218 A1 US 20110175218A1 US 97324910 A US97324910 A US 97324910A US 2011175218 A1 US2011175218 A1 US 2011175218A1
Authority
US
United States
Prior art keywords
semiconductor substrate
side
semiconductor
semiconductor die
attached
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/973,249
Inventor
Shiann-Ming Liou
Sehat Sutardja
Albert Wu
Chuan-Cheng Cheng
Chien-Chuan Wei
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Marvell World Trade Ltd
Original Assignee
Marvell World Trade Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US29592510P priority Critical
Priority to US32855610P priority
Priority to US33354210P priority
Priority to US34715610P priority
Priority to US35085210P priority
Assigned to MARVELL INTERNATIONAL LTD. reassignment MARVELL INTERNATIONAL LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MARVELL SEMICONDUCTOR, INC.
Priority to US12/973,249 priority patent/US20110175218A1/en
Application filed by Marvell World Trade Ltd filed Critical Marvell World Trade Ltd
Assigned to MARVELL SEMICONDUCTOR, INC. reassignment MARVELL SEMICONDUCTOR, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LIOU, SHIANN-MING, WEI, CHIEN-CHUAN, WU, ALBERT, CHENG, CHUAN-CHENG, SUTARDJA, SEHAT
Publication of US20110175218A1 publication Critical patent/US20110175218A1/en
Priority claimed from US13/648,114 external-priority patent/US20130026609A1/en
Assigned to MARVELL INTERNATIONAL LTD. reassignment MARVELL INTERNATIONAL LTD. LICENSE (SEE DOCUMENT FOR DETAILS). Assignors: MARVELL WORLD TRADE LTD.
Assigned to MARVELL WORLD TRADE LTD. reassignment MARVELL WORLD TRADE LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MARVELL INTERNATIONAL LTD.
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147Semiconductor insulating substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60Protection against electrostatic charges or discharges, e.g. Faraday shields
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401Structure
    • H01L2224/1403Bump connectors having different sizes, e.g. different diameters, heights or widths
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1418Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181On opposite sides of the body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73207Bump and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06506Wire or wire-like electrical connections between devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/0651Wire or wire-like electrical connections from device to substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06582Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586Housing with external bump or bump-like connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01032Germanium [Ge]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • H01L2924/12035Zener diode
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12044OLED
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor

Abstract

Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This disclosure claims priority to U.S. Provisional Patent Application No. 61/295,925, filed Jan. 18, 2010, and to U.S. Provisional Patent Application No. 61/328,556, filed Apr. 27, 2010, and to U.S. Provisional Patent Application No. 61/333,542, filed May 11, 2010, and to U.S. Provisional. Patent Application No. 61/347,156, filed May 21, 2010, and to U.S. Provisional Patent Application No, 61/350,852, filed Jun. 2, 2010, the entire specifications of which are hereby incorporated by reference in their entirety for all purposes, except for those sections, if any, that are inconsistent with this specification.
  • TECHNICAL FIELD
  • Embodiments of the present disclosure relate to the field of integrated circuits, and more particularly, to techniques, structures, and configurations of semiconductor substrates for package assemblies.
  • BACKGROUND
  • The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
  • Integrated circuit devices, such as transistors, are firmed on semiconductor dies that continue to scale in size to smaller dimensions. The shrinking dimensions of the semiconductor dies are challenging conventional substrate fabrication and/or package assembly technologies and configurations that are currently used to route electrical signals to or from the semiconductor die. For example, laminate substrate technologies may not produce sufficiently small features on a substrate to correspond with the finer pitches of interconnects or other signal-routing features formed on the semiconductor dies.
  • SUMMARY
  • In one embodiment, the present disclosure provides a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer being configured to route electrical signals of the semiconductor die.
  • In another embodiment, the present disclosure provides an apparatus including a semiconductor substrate comprising a semiconductor material, a dielectric layer formed on the semiconductor substrate, an interconnect layer formed on the dielectric layer, and a semiconductor die attached to the semiconductor substrate, wherein an active side of the semiconductor die is electrically coupled to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Embodiments of the present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments herein are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.
  • FIG. 1 schematically illustrates an example package assembly using a semiconductor substrate.
  • FIGS. 2A-2C schematically illustrate a semiconductor substrate subsequent to various process operations.
  • FIGS. 3A-3D schematically illustrate a package assembly using a semiconductor substrate subsequent to various process operations.
  • FIGS. 4A-4B schematically illustrate the package assembly of FIG. 3B subsequent to various process operations.
  • FIGS. 5A-5G schematically illustrate the package assembly of FIG. 3A subsequent to various process operations.
  • FIGS. 6-11 schematically illustrate various package assembly configurations using a semiconductor substrate.
  • FIG. 12 is a process flow diagram of a method to fabricate a package assembly using a semiconductor substrate.
  • FIG. 13 is a process flow diagram of another method to fabricate a package assembly using a semiconductor substrate.
  • FIG. 14 is a process flow diagram of yet another method to fabricate a package assembly using a semiconductor substrate.
  • DETAILED DESCRIPTION
  • Embodiments of the present disclosure describe techniques, structures, and configurations for integrated circuit (IC) package assemblies (referred to as “package assemblies” herein) using semiconductor substrates. In the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like numerals designate like parts throughout. Other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.
  • The description may use perspective-based descriptions such as up/down, over/under, and/or top/bottom. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.
  • For the purposes of the present disclosure, the phrase “A/B” means A or B. For the purposes of the present disclosure, the phrase “A and/or B” means “(A), (B), or (A and B).” For the purposes of the present disclosure, the phrase “at least one of A, B, and C” means “(A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).” For the purposes of the present disclosure, the phrase “(A)B” means “(B) or (AB)” that is, A is an optional element.
  • Various operations are described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
  • The description uses the phrases “in an embodiment,” “in embodiments,” or similar language, which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
  • FIG. 1 schematically illustrates an example package assembly 100 using a semiconductor substrate 102. As used herein, the semiconductor substrate 102 refers to a substrate or interposer that substantially comprises a semiconductor material such as, for example, silicon (Si). That is, the bulk of the material of the semiconductor substrate is a semiconductor material. The semiconductor material can include crystalline and/or amorphous types of material. In the case of silicon, for example, the silicon can include single crystal and/or polysilicon types. In other embodiments, the semiconductor substrate 102 can include other semiconductor materials such as, for example, germanium, group III-V materials, or group II-VI materials, that can also benefit from the principles described herein.
  • Generally, the semiconductor substrate 102 is fabricated using technologies similar to those that are used to fabricate IC structures on a semiconductor die or chip (e.g., one or more semiconductor dies 108). For example, well-known patterning processes (e.g., lithography and/or etch) and deposition processes for fabricating IC devices on a semiconductor die can be used to form structures on the semiconductor substrate 102. By using semiconductor fabrication techniques, the semiconductor substrate 102 can include smaller features than other types of substrates such as laminate (e.g., organic) substrates. The semiconductor substrate 102 may facilitate routing of electrical signals for current semiconductor dies, which continue to shrink in size. For example, in some embodiments, the semiconductor substrate 102 allows for fine pitch Si-to-Si interconnects and final line routing between the semiconductor substrate 102 and the one or more semiconductor dies 108.
  • The semiconductor substrate 102 includes a first side, A1, and a second side, A2, that is disposed opposite to the first side A1. The first side A1 and the second side A2 generally refer to opposing surfaces of the semiconductor substrate 102 to facilitate the description of various configurations described herein and are not intended to be limited to a particular structure of the semiconductor substrate 102.
  • A dielectric layer 104 is formed on at least the first side A1 of the semiconductor substrate 102 and can also be formed on the second side A1 of the semiconductor substrate 102. The dielectric layer 104 can be formed by depositing an electrically insulative material such as, for example, silicon dioxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiOxNy), where x and y represent suitable stoichiometric values, to substantially cover one or more surfaces of the semiconductor substrate 102, as shown. Other suitable electrically insulative materials can be used in other embodiments. The dielectric layer 104 can be formed by using a deposition technique including, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), and/or atomic layer deposition (ALD). Other suitable deposition techniques can be used in other embodiments.
  • The dielectric layer 104 can provide electrical isolation for features formed on the semiconductor substrate 102. For example, the dielectric layer 104 can be used to prevent shorting between electrically conductive features (e.g., one or more interconnect layers 106) formed on the dielectric layer 104 and the semiconductor material (e.g., silicon) of the semiconductor substrate 102. The dielectric layer 104 can further be used as a gate dielectric in the formation of one or more devices (e.g., capacitor 222 of FIG. 2C) on the semiconductor substrate 102.
  • One or more interconnect layers 106 are formed on the dielectric layer 104 to route electrical signals such as, for example, input/output (I/O) signals and/or power/ground signals, to and/or from one or more semiconductor dies 108 coupled to the semiconductor substrate 102. The one or more interconnect layers 106 can be formed by depositing and/or patterning an electrically conductive material such as, for example, a metal (e.g., copper or aluminum) or a doped semiconductor material (e.g., doped polysilicon). Other suitable electrically conductive materials can be used in other embodiments. The one or more interconnect layers 106 can include a variety of structures to route the electrical signals such as, for example, pads, lands, or traces. Although not depicted, a passivation layer comprising an electrically insulative material such as, for example, polyimide can be deposited on the one or more interconnect layers 106 and patterned to provide openings in the passivation layer to facilitate electrical coupling of the one or more semiconductor dies 108 to the one or more interconnect layers 106.
  • The one or more semiconductor dies 108 are attached to the first side A1 of the semiconductor substrate 102 using any suitable configuration including, for example, a flip-chip configuration, as depicted. Other suitable die-attach configurations such as, for example, a wire-bonding configuration can be used in other embodiments.
  • In the depicted embodiment, one or more bumps 110 are formed on the one or more semiconductor dies 108 and bonded to the one or more interconnect layers 106. The one or more humps 110 generally comprise an electrically conductive material such as, for example, solder or other metal to route the electrical signals of the one or more semiconductor dies 108. According to various embodiments, the one or more bumps 110 comprise lead, gold, tin, copper, or lead-free materials, or combinations thereof. The one or more bumps 110 can have a variety of shapes including spherical, cylindrical, rectangular, or other shapes and can be formed using a bumping process, such as, for example, a controlled collapse chip connect (C4) process, stud-bumping, or other suitable bumping process.
  • The one or more bumps 110 can be formed on the one or more semiconductor dies 108 while the one or more semiconductor dies 108 are in either wafer or singulated form. The one or more semiconductor dies 108 can be attached to the semiconductor substrate 102 while the semiconductor substrate 102 is in either wafer or singulated form.
  • The one or more semiconductor dies 108 generally have an active side that includes a surface upon which a plurality of integrated circuit (IC) devices (not shown) such as transistors for logic and/or memory are formed and an inactive side that is disposed opposite to the active side. The active side of the one or more semiconductor dies 108 is electrically coupled to the one or more interconnect layers 106. In the depicted embodiment, the active side of the one or more semiconductor dies 108 is coupled to the one or more interconnect layers 106 using the one or more bumps 110. In other embodiments, the active side of the one or more semiconductor dies 108 is electrically coupled to the one or more interconnect layers 106 using other structures, such as, for example, one or more bonding wires (e.g., one or more bonding wires 934 of FIG. 9).
  • One or more package interconnect structures such as, for example, one or more solder balls 112 or bumps (e.g., the one or more bumps 520 of FIG. 5A) can be formed on the one or more interconnect layers 106 to further route the electrical signals of the one or more semiconductor dies 108. The one or more package interconnect structures generally comprise an electrically conductive material. In some embodiments, the one or more package interconnect structures are disposed adjacent to a peripheral portion of the semiconductor substrate 102 and the one or more semiconductor dies 108 are disposed adjacent to a central portion of the semiconductor substrate 102, as depicted. The one or more package interconnect structures can be formed in a variety of shapes including spherical, planar, polygon, or combinations thereof.
  • According to various embodiments, the one or more semiconductor dies 108 and the semiconductor substrate 102 are coupled together to form a package assembly. The package assembly 100 can be electrically coupled to other electrical devices such as a printed circuit board (PCB) 1.50 (e.g., motherboard) or module using the one or more package interconnect structures to further route the electrical signals of the one or more semiconductor dies 108. The one or more package interconnect structures (e.g., the one or more solder balls 112) can be sized, in some embodiments, to provide a gap between the one or more semiconductor dies 108 and the printed circuit board 150, as shown.
  • FIGS. 2A-2C schematically illustrate a semiconductor substrate 102 subsequent to various process operations. Referring to FIG. 2A, a semiconductor substrate 102 comprising a semiconductor material is depicted. The semiconductor substrate 102 can include, for example, opposing planar surfaces on the first side A1 and the second side A2. The semiconductor substrate 102 can be cut, for example, from an ingot of monocrystalline or polycrystalline semiconductor material. The semiconductor substrate 102 is generally in wafer form during processing described in connection with FIGS. 2A-2C, but can be in singulated form.
  • Referring to FIG. 2B, the semiconductor substrate 102 is depicted subsequent formation of a dielectric layer 104 on at least the first side A1 of the semiconductor substrate 102. The dielectric layer 104 can be formed on the second side A2 in addition to the first side A1 in some embodiments.
  • Referring to FIG. 2C, the semiconductor substrate 102 is depicted subsequent to formation of one or more interconnect layers 106 on the dielectric layer 104 that is disposed on the first side A1 of the semiconductor substrate 102. A passivation layer (not shown) can be deposited on the one or more interconnect layers 106 and patterned to provide openings for electrically coupling one or more semiconductor dies (e.g., the one or more semiconductor dies 108 of FIG. 1) to the one or more interconnect layers 106.
  • According to various embodiments, one or more devices including IC devices and/or passive devices can be formed on the first side A1 of the semiconductor substrate 102. For example, an example capacitor 222 and an example electro-static discharge (ESD) protection device 224 can be formed on the semiconductor substrate 102 as depicted in region 275 of the semiconductor substrate 102. An enlarged view of region 275 is depicted in region 277, which shows the capacitor 222 and the ESD protection device 224 in greater detail.
  • The capacitor 222 can be, for example, a de-coupling capacitor to reduce noise associated with the electrical signals such as power/ground signals of the one or more semiconductor dies. The capacitor 222 can include, for example, a metal-oxide-semiconductor (MOS) structure having a source region, S, and a drain region, D, formed in the semiconductor substrate 102. The source region S and the drain region D can be formed, for example, by using a doping or implant process to alter the electrical conductivity of the semiconductor material of the semiconductor substrate 102. In some embodiments, the source region S and/or the drain region D is implanted with a dopant to form an N-type junction in a P-type substrate. A P-type junction in an N-type substrate can be used in other embodiments. According to various embodiments, the source region S and the drain region D are formed prior to forming the dielectric layer 104 of FIG. 2B. The dielectric layer 104 can function as a gate dielectric for the MOS structure with the one or more interconnect layers 106 functioning as a gate electrode of the MOS structure. The gate electrode can include, for example, doped polysilicon or a metal. Other suitable techniques can be used to form a capacitor 222 in the semiconductor substrate 102 in other embodiments.
  • The ESD protection device 224 can include, for example, a diode to protect against electro-static discharge. The ESD protection device 224 can be formed, for example, by a doping or implant process to create an N-type region in the semiconductor substrate 102, which may be a P-type substrate in some embodiments. A P-type region can be formed in an N-type substrate in other embodiments. The ESD protection device 224 can be formed, for example, using techniques associated with forming MOS or bipolar devices. According to various embodiments, the ESD protection device 224 includes a complementary MOS (CMOS), bipolar, transient voltage suppression (TVS) and/or Zener diode or a metal oxide varistor (MOV). The ESD protection device 224 can include other suitable devices that protect against electro-static discharge in other embodiments.
  • FIGS. 3A-3D schematically illustrate a package assembly using a semiconductor substrate 102 subsequent to various process operations. Referring to FIG. 3A, a package assembly 300A is depicted subsequent to attaching one or more semiconductor dies 108 to the first side A1 of the semiconductor substrate 102 in a flip-chip configuration. In some embodiments, one or more humps 110 are formed on the active side of the one or more semiconductor dies 108 and subsequently bonded to the one or more interconnect layers 106 to provide an electrical pathway for the electrical signals of the one or more semiconductor dies 108. The one or more semiconductor dies 108 can be attached to the semiconductor substrate 102 when the semiconductor substrate 102 is in either wafer form or singulated form.
  • Referring to FIG. 3B, a package assembly 300B is depicted subsequent to depositing an underfill material 314 to substantially fill a region between the one or more semiconductor dies 108 and the semiconductor substrate 102. According to various embodiments, the underfill material 314 is deposited in liquid form by a liquid dispensing or injection process. The underfill material 314 can include, for example, an epoxy or other suitable electrically insulative material. The underfill material 314 generally increases adhesion between the one or more semiconductor dies 108 and the semiconductor substrate 102, provides additional electrical insulation between the one or more semiconductor bumps, and/or protects the one or more bumps 110 from moisture and oxidation.
  • Referring to FIG. 3C, a package assembly 300C is depicted subsequent to depositing a molding compound 316 to substantially encapsulate the one or more semiconductor dies 108. The molding compound 316 generally protects the one or more semiconductor dies 108 from moisture, oxidation, or chipping associated Frith handling. The molding compound 316 may be used in conjunction with the underfill material 314, as depicted, in cases where the materials used for the molding compound 316 do not readily fill the region (e.g., due to a small pitch of the one or more bumps 110). According to various embodiments, the molding compound 316 is formed by depositing a resin (e.g., a thermosetting resin) in solid form (e.g., a powder) into a mold and applying heat and/or pressure to fuse the resin. In some embodiments, the molding compound 316 is not the same material as the underfill material 314.
  • Referring to FIG. 3D a package assembly 300D is depicted subsequent to forming one or more package interconnect structures such as solder balls 112 or bumps on the interconnect layer 106 to further route the electrical signals of the one or more semiconductor dies 108. For example, the solder balls 112 can be printed, electrically plated, or placed on designated locations such as bond pads of the one or more interconnect layers 106. The one or more package interconnect structures can be arranged, for example, in a single row or in multiple rows and can be formed in a variety of locations including a central or a peripheral portion of the package assembly 300D. In some embodiments, the package assembly 300D is a final package assembly. The final package assembly is an assembly that is ready to be mounted on another component such as a printed circuit board (e.g., the printed circuit board 150 of FIG. 1).
  • When the actions described in connection with FIGS. 3B-3D are performed on a semiconductor substrate 102 in wafer form, the semiconductor substrate 102 is further singulated by a suitable singulation process. According to various embodiments, the semiconductor substrate 102 can be singulated subsequent to the actions described in connection with FIG. 3A, FIG. 3B, FIG. 3C, or FIG. 3D.
  • In some embodiments, the one or more package interconnect structures (e.g., the one or more solder balls 112) can be formed on the semiconductor substrate 102 of the package assembly 300A to form a final package assembly. The final package assembly using the package assembly 300A may save costs associated with using an underfill material and/or molding compound. In some embodiments, the semiconductor substrate 102 comprises a material that has a coefficient of thermal expansion (CTE) that is substantially the same as a material of the one or more semiconductor dies 108. For example, the semiconductor substrate 102 and the one or more semiconductor dies 108 may both comprise silicon. In such a case, the stress of thermal expansion, which is generally mitigated by the underfill material 314 and/or the molding compound 316, is reduced because the semiconductor substrate 102 and the one or more semiconductor dies 108 have the same CTE. Thus, when the CTE is similar or the same for the semiconductor substrate 102 and the one or more semiconductor dies 108, the underfill material 314 and/or the molding compound 316 may not be used at all.
  • In some embodiments, the one or more package interconnect structures (e.g., the one or more solder balls 112) can be formed on the semiconductor substrate 102 of the package assembly 300B to form a final package assembly. The final package assembly using the underfill material 314 may increase reliability of joints such as solder joints associated with the one or more bumps 110 of the package assembly 300B.
  • FIGS. 4A-4B schematically illustrate the package assembly 300B of FIG. 3B subsequent to various process operations. Although the package assembly 300B is used as an example to illustrate the principles of these embodiments, the principles can be suitably applied to other package assemblies described herein including, for example, the package assembly 300A.
  • Referring to FIG. 4A, a package assembly 400A is depicted subsequent to the formation of one or more package interconnect structures (e.g., solder balls 112) on the one or more interconnect layers 106 and the formation of one or more thermal dissipation structures (e.g., solder balls 418) on an inactive side of the one or more semiconductor dies 108, as shown. The one or more package interconnect structures and the one or more thermal dissipation structures can include other types of structures such as, for example, bumps in other embodiments. The one or more thermal dissipation structures generally comprise a thermally conductive material such as, for example, metal to provide a thermal path for heat dissipation. The one or more package interconnect structures and the one or more thermal dissipation structures can be sized to have respective surfaces that are substantially coplanar. For example, the solder balls 112 and the solder balls 418 can be sized to have a surface that substantially lies in the same plane 419 to facilitate connection to a substantially planar surface such as a printed circuit board (e.g., printed circuit board 150 of FIG. 4B). In some embodiments, the solder balls 112 are larger in size than the solder balls 418, as depicted.
  • The actions described in connection with FIG. 4A can be performed when the semiconductor substrate 102 is in either wafer form or singulated form. If in wafer form, the semiconductor substrate 102 is singulated prior to mounting the package assembly 400A on the printed circuit board.
  • Referring to FIG. 4B, a package assembly 400B is depicted subsequent to attachment of the one or more package interconnect structures (e.g., the one or more solder balls 112) and the one or more thermal dissipation structures (e.g., the one or more solder balls 418) to the printed circuit board 150. According to various embodiments, the package assembly 400B is mounted on the printed circuit board 150 using a surface mount technology (SMT).
  • FIGS. 5A-5G schematically illustrate the package assembly 300A of FIG. 3A subsequent to various process operations. Although the package assembly 300A is used as an example to illustrate the principles of these embodiments, the principles can be suitably applied to other package assemblies described herein.
  • Referring to FIG. 5A, a package assembly 500A is depicted subsequent to forming one or more package interconnect structures (e.g., one or more bumps 520) on the one or more interconnect layers 106. The one or more bumps 520 can be formed, for example, by printing, plating, or placing the one or more humps 520 on the one or more interconnect layers 106 of the semiconductor substrate 102. The one or more bumps 520 can be reflowed to form a circular shape, but is not limited to the circular shape. In other embodiments, the one or more bumps 520 can have other shapes such as a planar shape. The one or more bumps 520 can be formed using any suitable electrically conductive material such as, for example, lead, gold, tin, copper, or lead-free materials, or combinations thereof.
  • The one or more package interconnect structures can include other types of structures than the one or more bumps 520 depicted in FIG. 5A. For example, the one or more package interconnect structures can include solder balls (e.g., the solder balls 112 of FIG. 1) in other embodiments.
  • Referring to FIG. 5B, a package assembly 500B is depicted subsequent to depositing a molding compound 316 to substantially fill a region between the one or more semiconductor dies 108 and the semiconductor substrate 102. Filling this region with molding compound 316 may save cost and process steps associated with fabrication of the semiconductor substrate 102. Generally, underfill material (e.g., the underfill material 314 of FIG. 3C) is more costly than the molding compound 316.
  • The molding compound 316 is further deposited to substantially encapsulate the one or more semiconductor dies 108. In some embodiments, the molding compound 316 is deposited to substantially cover a surface on the first side A 1 of the semiconductor substrate 102, which can be in either wafer form or singulated form. When the semiconductor substrate 102 is in wafer form, the molding compound 316 can be deposited to overmold an entire surface of the wafer corresponding with the first side A1 of the semiconductor substrate 102. The deposited molding compound 316 can be further divided into smaller blocks or regions for stress/warpage control. For example, portions of the molding compound 316 can be patterned using well-known etch and/or lithography processes or otherwise removed at peripheral edges of each semiconductor substrate unit on the wafer.
  • Referring to FIG. 5C, a package assembly 500C is depicted subsequent to forming one or more openings 526 in the molding compound 316. According to various embodiments, the one or more openings 526 are formed to expose the one or more package interconnect structures (e.g., the one or more bumps 520). The one or more openings 526 can be formed using a laser ablation or etching process. In these embodiments, the one or more package interconnect structures provide an etch stop or laser stop material during formation of the one or more openings 526.
  • Referring to FIG. 5D, a package assembly 500D is depicted subsequent to depositing an electrically conductive material (e.g., one or more solder balls 112) to substantially fill the one or more openings (e.g., the one or more openings 526 of FIG. 5C). In the depicted embodiment, one or more solder balls 112 are electrically coupled to the one or snore bumps 520, which are electrically coupled to the one or more interconnect layers 106. The one or more solder balls 112 can, for example, be placed and reflowed to provide package interconnect structures for the package assembly 500D. That is, the package interconnect structures can include the one or more solder balls 112 and the one or more bumps 520, coupled as shown.
  • In other embodiments, the one or more solder balls 112 are formed directly on the one or more interconnect layers 106. That is, in some embodiments, the one or more bumps 520 are not be formed at all and the one or more solder balls 112 are directly bonded to the one or more interconnect layers 106 through the one or more openings.
  • When the one or more bumps 520 are used in conjunction with the one or more solder balls 112, as depicted, the one or more solder balls 112 can be smaller than solder balls that are used in a package assembly that does not use the one or more bumps 520. The additional height provided by the one or more bumps 520 facilitates using a smaller size for the one or more solder balls 112 because less solder ball material is needed to fill the one or more openings.
  • The one or more solder balls 112 can include multiple rows of solder balls configured to further route the electrical signals of the one or more semiconductor dies 108. The package interconnect structures can include other types of structures. For example, in some embodiments, one or more post structures are formed in the one or more openings to route the electrical signals of the one or more semiconductor dies 108.
  • In some embodiments, the package interconnect structures (e.g., the one or more solder balls 112) are attached to a printed circuit board (e.g., the printed circuit board 150 of FIG. 1). According to various embodiments, the package assembly 500D is a final package assembly.
  • In some embodiments, the semiconductor substrate 102 is in wafer form and a backside of the wafer (e.g., the second side A2 of the semiconductor substrate 102) is thinned to provide a smaller package assembly. Material can be removed from the backside of the wafer using, for example, well-known mechanical and/or chemical wafer thinning processes such as grinding or etching.
  • Referring to FIG. 5E, a package assembly 500E is depicted subsequent to forming a molding compound 316 to substantially cover the second side A1 of the semiconductor substrate 102. The molding compound 316 disposed on the second side A2 can be used, for example, to counterbalance stress associated with the molding compound 316 disposed on the first side A1 of the semiconductor substrate 102 and, thus, reduce stress and/or warpage for the package assembly 500E. In some embodiments, the molding compound 316 is deposited on the second side A2 of the semiconductor substrate 102 when the semiconductor substrate 102 is in wafer form, prior to singulation. In some embodiments, the package assembly 500E is a final package assembly.
  • Referring to FIG. 5F, a package assembly 500F is depicted to show that, in some embodiments, the molding compound 316 is formed on the first side A1 of the semiconductor substrate 102 to have a surface that is substantially coplanar with or lower than an inactive side of the one or more semiconductor dies 108. In an embodiment, the package assembly 500F is formed by removing material of the molding compound 316 of the package assembly 500B of FIG. 5B to expose the one or more semiconductor dies 108. The material can be removed, for example, by a polishing process. In another embodiment, the molding compound 316 of the package assembly 500F is formed by using a mold that is configured to provide a surface of the molding compound 316 that is substantially coplanar with or lower than the inactive side of the one or more semiconductor dies 108. In some embodiments, the package assembly 500F is a final package assembly.
  • Referring to FIG. 5G, a package assembly 500G is depicted subsequent to the formation of one or more thermal dissipation structures (e.g., solder balls 518) on inactive side of the one or more semiconductor dies 108, as shown. The one or more thermal dissipation structures generally comprise a thermally conductive material such as, for example, metal (e.g., solder) to provide a thermal path for heat dissipation. The one or more package interconnect structures (e.g., the one or more solder balls 112) and the one or more thermal dissipation structures (e.g., the solder balls 518) can be sized to have surfaces that are substantially coplanar, as can be seen. For example, the solder balls 112 and the solder balls 518 can be sized to have a surface that substantially lies in the same plane 519 to facilitate connection to a substantially planar surface such as a printed circuit board (e.g., the printed circuit board 150 of FIG. 4B). In some embodiments, the solder balls 112 are larger in size than the solder balls 518, as depicted. The solder balls 112, 518 can be formed such that they have surfaces that do not lie in the same plane 519 in other embodiments.
  • The one or more solder balls 518 can be formed, for example, by forming one or more openings in the molding compound 316 of the package assembly 500B of FIG. 5B or the package assembly 500D of FIG. 5D to expose the inactive side of the one or more semiconductor dies 108. The one or more openings can be formed using a laser ablation or etching process. The inactive side of the one or more semiconductor dies 108 can function as a laser stop or etch stop material. Subsequent to formation of the one or more openings, the one or more solder balls 518 can be deposited to substantially fill the one or more openings over the one or more semiconductor dies 108. In some embodiments, the package assembly 500G is a final package assembly.
  • FIGS. 6-11 schematically illustrate various package assembly configurations using a semiconductor substrate 102. Referring to FIG. 6, a package assembly 600 is depicted subsequent to formation of a molding compound 316 on the second side A2 of the semiconductor substrate 102. The molding compound 316 can be deposited to substantially cover the second side A2 of the semiconductor substrate 102. The molding compound 316 can be formed to protect or strengthen the semiconductor substrate 102. For example, the molding compound 316 can be formed prior to attaching the one or more semiconductor dies 108 to the semiconductor substrate 102 to protect the semiconductor substrate 102 from chipping or other damage that can occur while handling the semiconductor substrate 102 during package assembly actions described herein. In some embodiments, the molding compound 316 is deposited on the second side A2 of the semiconductor substrate 102 when the semiconductor substrate 102 is in wafer form, prior to singulation.
  • Referring to FIG. 7, a package assembly 700 is depicted subsequent to attachment of a heat spreader 730 to the second side A2 of the semiconductor substrate 102. The heat spreader 730 includes a structure that facilitates heat removal such as a metal plate. The heat spreader 730 can be thermally coupled to the second side A2 of the semiconductor substrate 102 using a thermally conductive adhesive. The heat spreader 730 can be attached when the semiconductor substrate 102 is in either wafer form or singulated form. In other embodiments, the heat spreader 703 can be formed using deposition processes similar to those used to form the one or more interconnect layers 106.
  • Referring to FIG. 8, a package assembly 800 is depicted subsequent to removing portions of the semiconductor material from the second side A2 of the semiconductor substrate 102 to increase a surface area for improved heat dissipation. According to various embodiments, one or more recessed regions 832, such as holes or channels, are formed in a surface on the second side A2 of the semiconductor substrate 102. The one or more recessed regions 832 can be formed according to any suitable technique including, for example, an etching process. A profile of the one or more recessed regions 832 can have other shapes than depicted in other embodiments. A thermally conductive layer (not shown) such as a metal layer can be deposited on the surface having the one or more recessed regions 832 to increase thermal dissipation.
  • Referring to FIG. 9A, a package assembly 900A includes one or more semiconductor dies 108 attached to the semiconductor substrate 102 in a wire-bonding configuration. An inactive side of the one or more semiconductor dies 108 is attached to the first side A1 of the semiconductor substrate 102 using an adhesive and an active side of the one or more semiconductor dies is electrically coupled to the one or more interconnect layers 106 using one or more bonding wires 934. The adhesive can include any suitable die attach material such as an epoxy. The one or more bonding wires 934 generally comprise an electrically conductive material, such as a metal, to route the electrical signals of the one or more semiconductor dies 108. The one or more bonding wires 934 can be formed using, for example, a ball-bonding or wedge-bonding process.
  • In an embodiment, a bonding wire 934 a is formed to electrically couple an active side of a first semiconductor die to an active side of a second semiconductor die, as shown. The one or more bonding wires 934 can further include a bonding wire 934 b that electrically couples an active side of a semiconductor die to the one or more interconnect layers 106 disposed between the first semiconductor die and the second semiconductor die. A molding compound 316 is formed to substantially encapsulate the one or more semiconductor dies 108 and the one or more bonding wires 934, as shown.
  • FIG. 9B illustrates a package assembly 900B that is similar to the package assembly 900A as shown in FIG. 9A. In the package assembly 900B, vias 938, such as through-silicon vias, that are filled with conducting materials are used to provide electrical connections from the semiconductor dies 108 to external components. These vias 938 may be used to provide power and ground connections.
  • Referring to FIG. 10A, a package assembly 1000A includes one or more semiconductor dies 108A,B attached to the semiconductor substrate 102 in a mixed flip-chip and wire-bonding configuration. For example, a first semiconductor die of the one or more semiconductor dies 108A,B is attached to the semiconductor substrate 102 in a flip-chip configuration using one or more bumps 110 and a second semiconductor die of the one or more semiconductor dies 108A,B is attached to the semiconductor substrate 102 in a wire-bonding configuration using one or more bonding wires 934. A molding compound 316 is formed to substantially encapsulate the one or more semiconductor dies 108A,B and the one or more bonding wires 934, as shown.
  • FIG. 10B illustrates a package assembly 1000B that is similar to the package assembly 1000A as shown in FIG. 10A. In the package assembly 1000B, vias 938, such as through-silicon vias, that are filled with conducting materials are used to provide electrical connections from the semiconductor die 108B to external components. These vias 938 may be used to provide power and ground connections.
  • Referring to FIG. 11, a package assembly 1100 includes one or more semiconductor dies 108 attached to the semiconductor substrate 102 in a stacked flip-chip and wire-bonding configuration. A first semiconductor die of the one or more semiconductor dies 108 is attached to the semiconductor substrate 102 in a flip-chip configuration. An active side of the first semiconductor die is electrically coupled to the one or more interconnect layers 106 using one or more bumps 110, as shown. An inactive side of a second semiconductor die of the one or more semiconductor dies 108 is attached to first semiconductor die using an adhesive 936, as shown. In some embodiments, a spacer (not shown) such as dummy silicon can be positioned between the first and second semiconductor dies. An active side of the second semiconductor die is electrically coupled to the one or more interconnect layers 106 using one or more bonding wires 934. In other embodiments, vias (not shown), such as through-silicon vias, that are filled with conducting materials may be used to couple the active side of the second semiconductor die to external components through the molding compound 316. The vias may be used to provide power and ground connections.
  • In some embodiments, the active side of the second semiconductor die is electrically coupled to the one or more interconnect layers 106 by using a bonding wire 934 c to electrically couple the active side of the second semiconductor die to the inactive side of the first semiconductor die and using a bonding wire 934 d to electrically couple the first bonding wire 934 c to the one or more interconnect layers 106. A molding compound 316 is formed to substantially encapsulate the one or more semiconductor dies 108 and the one or more bonding wires 934, as shown. Although not shown, in other embodiments, a bottom semiconductor die of the one or more semiconductor dies 108 can be coupled to the semiconductor substrate 102 in a wirebonding configuration and a top semiconductor die of the one or more semiconductor dies 108 can be coupled to the bottom semiconductor die in a flip-chip configuration.
  • Techniques and con figurations described in connection with FIGS. 6-11 can be suitably combined with other embodiments described herein. For example, in some embodiments, the techniques and configurations described for the package assemblies of FIGS. 6-8 can be performed on the package assemblies of FIG. 1, FIGS. 3A-3D, FIGS. 4A-4B, FIGS. 5A-5G, or FIGS. 9-11. In some embodiments, the techniques and configurations described for the package assemblies of FIGS. 9-11 can be performed, for example, on the package assemblies of FIG. 1, FIGS. 3A-3D, FIGS. 4A-4B, FIGS. 5A-5G, or FIGS. 6-8. Other suitable combinations of the techniques and configurations described herein can be used in other embodiments.
  • FIG. 12 is a process flow diagram of a method 1200 to fabricate a package assembly (e.g., the package assembly 100 of FIG. 1) using a semiconductor substrate (e.g., the semiconductor substrate 102 of FIG. 1). At 1202, the method 1200 includes providing a semiconductor substrate comprising a semiconductor material. The semiconductor substrate generally has a first side (e.g., the first side A1 of FIG. 2A) and a second side (e.g., the second side A2 of FIG. 2A) that is disposed opposite to the first side. In some embodiments, one or more devices are formed on the first side (e.g., the first side A1 of FIG. 1) of the semiconductor substrate prior to attaching the semiconductor die to the semiconductor substrate. For example, a capacitor (e.g., the capacitor 222 of FIG. 2C) or an ESD protection device (e.g., the ESD protection device 224 of FIG. 2C) can be formed on the first side of the semiconductor substrate. The one or more devices can be formed using techniques described in connection with FIG. 2C and further described in connection with 1204 and 1206 of method 1200.
  • At 1204, the method 1200 further includes forming a dielectric layer (e.g., the dielectric layer 104 of FIG. 1) on at least one side (e.g., the first side A1) of the semiconductor substrate. The dielectric layer can further be formed on the opposite side (e.g., the second side A2) of the semiconductor substrate in some embodiments.
  • The dielectric layer 104 can be formed by depositing an electrically insulative material such as, for example, silicon dioxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiOxNy) to substantially cover one or more surfaces of the semiconductor substrate 102, as shown. Other suitable electrically insulative materials can be used in other embodiments.
  • The dielectric layer 104 can be formed by using a suitable deposition technique including, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), and/or atomic layer deposition (ALD). Other suitable deposition techniques can be used in other embodiments. The dielectric layer 104 can be used as a dielectric (e.g., gate dielectric) in the formation of the one or more devices (e.g., capacitor 222 or ESD protection device 224 of FIG. 2C) on the semiconductor substrate 102.
  • At 1206, the method 1200 further includes forming one or more interconnect layers (e.g., the one or more interconnect layers 106 of FIG. 1) on the dielectric layer on the first side of the semiconductor substrate. The one or more interconnect layers can be used to route electrical signals such as, for example, input/output (I/O) signals and/or power/ground signals, to and/or from one or more semiconductor dies (e.g., the one or more semiconductor dies 108 of FIG. 1).
  • The one or more interconnect layers can be formed by depositing and/or patterning an electrically conductive material such as, for example, a metal (e.g., copper or aluminum) or a doped semiconductor material (e.g., doped polysilicon). Other suitable electrically conductive materials can be used in other embodiments.
  • The one or more interconnect layers can include a variety of structures to route the electrical signals such as, for example, pads, lands, or traces. A passivation layer comprising an electrically insulative material such as, for example, polyimide can be deposited on the one or more interconnect layers and patterned to provide openings in the passivation layer to facilitate electrical coupling of the one or more semiconductor dies to the one or more interconnect layers.
  • The one or more interconnect layers can be used as an electrode material in the formation of the one or more devices on the semiconductor substrate. For example, the electrode material can serve as a gate electrode for the one or more devices.
  • At 1208, the method 1200 further includes attaching a semiconductor die (e.g., the one or more semiconductor dies 108 of FIG. 1) to the semiconductor substrate. As described herein, one or more semiconductor dies can be attached to the first side of the semiconductor substrate in a variety of configurations.
  • In an embodiment, the semiconductor die is attached to the first side of the semiconductor substrate in a flip-chip configuration (e.g., as shown in the package assembly 100 of FIG. 1). In the flip-chip configuration, the active side of the semiconductor die is generally attached to the first side of the semiconductor substrate using one or more bumps (e.g., the one or more bumps 110 of FIG. 1).
  • In another embodiment, the semiconductor die is attached to the first side of the semiconductor substrate in a wire-bonding configuration (e.g., as shown in the package assembly 900 of FIG. 9). In the wire-bonding configuration, an inactive side of the semiconductor die is attached to the first side of the semiconductor using an adhesive.
  • In yet another embodiment, the semiconductor die is attached to the semiconductor substrate in a flip-chip configuration and another semiconductor die is attached to the semiconductor substrate in a wire-bonding configuration (e.g., as shown in the package assembly 1000 of FIG. 10). In still yet another embodiment, an active side of the semiconductor die is attached to the first side of the semiconductor substrate in a flip-chip configuration and an inactive side of another semiconductor die is attached to the semiconductor die using an adhesive (e.g., as shown in the package assembly 1100 of FIG. 11).
  • At 1210, the method 1200 further includes electrically coupling the active side of the semiconductor die to the one or more interconnect layers. In an embodiment, the active side of the semiconductor die is electrically coupled to the one or more interconnect layers using the one or more bumps. In another embodiment, the active side of the semiconductor die is electrically coupled to the one or more interconnect layers using one or more bonding wires (e.g., the one or more bonding wires 934 of FIG. 9). Combinations of these techniques can be used in other embodiments.
  • At 1212, the method 1200 further includes depositing an underfill material (e.g., the underfill material 314 of FIG. 3B) and/or a molding compound (e.g., the molding compound 316 of FIG. 3C, 5B, or 9). The underfill material is generally deposited to substantially fill a regio between the semiconductor die and the semiconductor substrate. According to various embodiments, the underfill material is en deposited in liquid form by a liquid dispensing or infection process. The underfill material can include, for example, an epoxy or other suitable electrically insulative material.
  • The molding compound is generally deposited to substantially encapsulate the semiconductor die. In a wire-bonding configuration, the molding compound is deposited to su substantially encapsulate the one or more bonding wires. According to various embodiments, the molding compound is formed by depositing a resin (e.g., a thermosetting resin) in solid form (e.g., a powder) into a mold and applying heat and/or pressure to fuse the resin. In some embodiments, the molding compound is not the same material as the underfill material.
  • In a flip-chip configuration, the molding compound can be used in conjunction with the underfill material (e.g., as shown in FIG. 3C). In other embodiments of the flip-chip configuration, the molding compound can be deposited to fill the underfill region. That is, in some embodiments, the underfill material is not used and the molding compound is deposited to substantially fill a region between the semiconductor die and the semiconductor substrate (e.g., as shown in FIG. 5B). In some embodiments, the molding compound is formed to cover only a portion of the first side of the semiconductor substrate (e.g., as shown in FIG. 3C). In other embodiments, the molding compound is formed to substantially cover the entire first side of the semiconductor substrate (e.g., as shown in FIG. 5B).
  • At 1214, the method 1200 further includes forming one or more package interconnect structures on the one or more interconnect layers to route electrical signals of the semiconductor die to and/or from the semiconductor substrate. In some embodiments, the one or more package interconnect structures include one or more solder balls (e.g., the one or more solder balls 112 of FIG. 3D or 5D). The one or more solder balls can be formed, for example, by printing, plating, or placing the one or more solder balls on the one or more interconnect layers of the semiconductor substrate. A reflow process can be used to form a connection between the one or more solder balls and the one or more interconnect layers. In some embodiments, the one or more solder balls can be attached or electrically coupled to the one or more interconnect layers through one or more openings (e.g., the one or more openings 526 of FIG. 5C) formed in the molding compound as described herein.
  • In some embodiments, the one or more package interconnect structures include one or more bumps (e.g., the one or more bumps 520 of FIG. 5A). The one or more bumps can be formed, for example, by printing, plating, or placing the one or more bumps on the one or more interconnect layers of the semiconductor substrate. The one or more bumps can be reflowed to form a circular shape. The one or more bumps can have other shapes such as a planar shape. The one or more bumps can be formed using any suitable electrically conductive material such as, for example, lead, gold, tin, copper, or lead-free materials, or combinations thereof. The one or more package interconnect structures can include combinations of the one or more bumps and the one or more solder balls (e.g., as shown in FIG. 5D). The one or more package interconnect structures can be electrically coupled to a printed circuit hoard (e.g., the printed circuit board 150 of FIG. 1).
  • At 1216, the method 1200 further includes performing additional operations to increase thermal dissipation, protect/strengthen, counter-balance, and/or reduce warpage of the semiconductor substrate. In some embodiments, one or more thermal dissipation structures (e.g., the one or more solder balls 418 or 518 of respective FIG. 4A or 5G) are formed on an inactive side of a semiconductor die to provide a thermal path for heat dissipation away from the semiconductor die, as described herein. The one or more thermal dissipation structures for heat dissipation can formed simultaneously as the one or more package interconnects and can be subsequently attached to a printed circuit board (e.g., the printed circuit board 150 of FIG. 4B) during a surface mount process to couple the one or more package interconnects to the printed circuit board.
  • In some embodiments, a heat spreader (e.g., the heat spreader 730 of FIG. 7) is thermally coupled to the second side of the substrate. The heat spreader can be attached, for example, by using a thermally conductive compound. In other embodiments, one or more recessed regions (e.g., the one or more recessed regions 832 of FIG. 8) are formed by removing portions of the semiconductor material from the second side of the semiconductor substrate to increase a surface area of the second side. The increased surface area facilitates heat removal away from the second side of the semiconductor substrate.
  • In an embodiment, a molding compound is formed to substantially cover the second side of the semiconductor substrate (e.g., as shown in FIG. 6). The molding compound can be used to strengthen and/or protect the semiconductor substrate against chipping or other environmental harm. In some embodiments, the molding compound is formed on the second side of the semiconductor substrate to counter-balance and/or prevent warpage associated with a molding compound formed on the first side of the semiconductor substrate (e.g., as shown in FIG. 5E). The actions described in connection with method 1200 can include other suitable embodiments for techniques described elsewhere in this description.
  • FIG. 13 is a process flow diagram of another method 1300 to fabricate a package assembly (e.g., the package assembly 400B of FIG. 4B) using a semiconductor substrate (e.g., the semiconductor substrate 102 of FIG. 4B). At 1302, 1304, and 1306, the method 1300 respectively includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on at least one side of the semiconductor substrate, and forming one or more interconnect layers on the dielectric layer, which may comport with embodiments already described in connection with 1202, 1204, and 1206 of method 1200.
  • At 1308, the method 1300 further includes coupling one or more semiconductor dies (e.g., the semiconductor dies 108 of FIG. 3A) to the interconnect layer using one or more bumps (e.g., the one or more bumps 110 of FIG. 3A). The one or more semiconductor dies can be configured, for example, in a flip-chip configuration where an active side of the semiconductor die is coupled to the semiconductor substrate using the one or more bumps.
  • At 1310, the method 1300 further includes depositing an underfill material (e.g., the underfill material 314 of FIG. 3B) to substantially fill a region between the semiconductor die and the semiconductor substrate. According to various embodiments, the underfill material is deposited in liquid form by a liquid dispensing or injection process. A molding compound (e.g., the molding compound 316 of FIG. 3C) can also be formed to substantially encapsulate the one or more semiconductor dies. The underfill material and the molding compound generally comport with embodiments described herein.
  • At 1312, the method 1300 further includes forming one or more package interconnect structures (e.g., the solder balls 112 of FIG. 3D) and/or one or more thermal dissipation structures (e.g., the one or more solder balls 418 of FIG. 4A). The one or more package interconnect structures are electrically coupled to the one or more interconnect layers. In some embodiments, the one or more package interconnect structures are formed on the one or more interconnect layers. The one or more thermal dissipation structures are generally formed on an inactive side of the one or more semiconductor dies to provide a thermal path for heat dissipation. The one or more package interconnect structures and the one or more thermal dissipation structures can be sized to have respective surfaces that are substantially coplanar (e.g., plane 419 of FIG. 4A).
  • At 1314, the method 1300 further includes coupling the one or more package interconnect structures and/or the one or more thermal dissipation structures to a printed circuit board (e.g., the printed circuit board 150 of FIG. 4B). The printed circuit board can be a motherboard in some embodiments. The one or more package interconnect structures and/or the one or more thermal dissipation structures can be coupled to other electronic devices, such as another package assembly, in other embodiments.
  • FIG. 14 is a process flow diagram of yet another method 1400 to fabricate a package assembly (e.g., the package assembly 500G of FIG. 5G) using a semiconductor substrate (e.g., the semiconductor substrate 102 of FIG. 5G). At 1402, 1404, and 1406, the method 1400 respectively includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on at least one side of the semiconductor substrate, and forming one or more interconnect layers on the dielectric layer, which may comport with embodiments already described in connection with 1202, 1204, and 1206 of method 1200.
  • At 1408, the method 1400 further includes coupling one or more semiconductor dies (e.g., the semiconductor dies 108 of FIG. 5A) to the interconnect layer using one or more bumps (e.g., the one or more humps 110 of FIG. 5A). The one or more semiconductor dies can be configured, for example, in a flip-chip configuration where an active side of the semiconductor die is coupled to the semiconductor substrate using the one or more bumps.
  • At 1410, the method 1400 further includes forming one or more additional bumps (e.g., the one or more humps 520 of FIG. 5A) on the one or more interconnect layers in some embodiments. The one or more additional bumps are generally formed prior to the molding compound being deposited.
  • At 1412, the method 1400 further includes depositing a molding compound the molding compound 316 of FIG. 5B) to fill a region between the semiconductor die and the semiconductor substrate. In some embodiments, the molding compound is deposited to substantially encapsulate the one or more semiconductor dies. A portion of the molding compound can be recessed by well-known mechanical and/or chemical processes to expose a surface of the one or more semiconductor dies.
  • The molding compound can be formed by depositing a resin of solid form into a mold and subsequently applying heat and/or pressure to fuse the resin. According to various embodiments, the molding compound is deposited when the semiconductor substrate is in wafer form to overmold an entire surface of the wafer. The deposited molding compound can be divided into smaller blocks or regions to reduce stress between the molding compound and the wafer.
  • In some embodiments where the semiconductor die is coupled to a first side of the semiconductor substrate, a molding compound is formed to substantially cover a second side of the semiconductor substrate, the second side being disposed opposite to the first side of the semiconductor substrate. The molding compound can be used in this manner to reduce stress and/or warpage associated with a molding compound disposed on the first side of the semiconductor substrate.
  • At 1414, the method 1400 further includes forming one or more package interconnect structures (e.g., the solder balls 112 of FIG. 5G) and/or one or more thermal dissipation structures (e.g., the one or more solder balls 518 of FIG. 5G). The one or more package interconnect structures are electrically coupled to the one or more interconnect layers. In some embodiments, the one or more package interconnect structures are formed on the one or more interconnect layers. In other embodiments where the one or more additional bumps (e.g., the one or more bumps 520 of FIG. 5D) are formed, the one or more package interconnect structures are formed on the one or more additional bumps. For example, one or more openings (e.g., the one or more openings 526 of FIG. 5C) can be formed in the molding compound using an etch or laser process to expose the one or more additional bumps. The one or more additional bumps can function as a laser or etch stop material. Subsequently, the one or more package interconnect structures can be formed on the exposed one or more additional humps within the one or more openings.
  • The one or more thermal dissipation structures are generally formed on an inactive side of the one or more semiconductor dies to provide a thermal path for heat dissipation. One or more openings can be formed in the molding compound to expose the inactive side of the one or more semiconductor dies to allow formation of the one or more thermal dissipation structures on the one or more semiconductor dies. The one or more package interconnect structures and the one or more thermal dissipation structures can be sized to have respective surfaces that are substantially coplanar (e.g., plane 519 of FIG. 5G). The semiconductor substrate can be subsequently thinned by grinding or etching processes.
  • At 1416, the method 1400 further includes coupling the one or more package interconnect structures and/or the one or more thermal dissipation structures to a printed circuit board (e.g., the printed circuit board 150 of FIG. 4B). The printed circuit board can be a motherboard in some embodiments. The one or more package interconnect structures and/or the one or more thermal dissipation structures can be coupled to other electronic devices, such as another package assembly, in other embodiments.
  • Although certain embodiments have been illustrated and described herein, a wide variety of alternate and/or equivalent embodiments or implementations calculated to achieve the same purposes may be substituted for the embodiments illustrated and described without departing from the scope of the present disclosure. This disclosure is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, it is manifestly intended that embodiments described herein be limited only by the claims and the equivalents thereof.

Claims (23)

1. A method comprising:
providing a semiconductor substrate comprising a semiconductor material;
forming a dielectric layer on the semiconductor substrate;
forming an interconnect layer on the dielectric layer;
attaching a semiconductor die to the semiconductor substrate; and
electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die.
2. The method of claim 1, wherein:
the semiconductor die is attached to the semiconductor substrate in a flip-chip configuration; and
the active side of the semiconductor die is electrically coupled to the interconnect layer using one or more bumps.
3. The method of claim 1, wherein:
the semiconductor die is attached to the semiconductor substrate in a wire-bonding configuration;
an inactive side of the semiconductor die is attached to the semiconductor substrate using an adhesive; and
the active side of the semiconductor die is electrically coupled to the interconnect layer using one or more bonding wires.
4. The method of claim 1, further comprising:
forming a molding compound to substantially encapsulate the semiconductor die.
5. The method of claim 4, wherein the semiconductor die is attached to a first side of the semiconductor substrate, the method further comprising:
forming a molding compound to substantially cover a second side of the semiconductor substrate, the second side being disposed opposite to the first side of the semiconductor substrate.
6. The method of claim 1, wherein the semiconductor die is attached to a first side of the semiconductor substrate, the method further comprising:
thermally coupling a heat spreader to a second side of the semiconductor substrate, the second side being disposed opposite to the first side of the semiconductor substrate.
7. The method of claim 1, wherein the semiconductor die is attached to a first side of the semiconductor substrate, the method further comprising:
removing portions of the semiconductor material from a second side of the semiconductor substrate to increase a surface area of the second side, the second side being disposed opposite to the first side of the semiconductor substrate.
8. The method of claim 1, wherein the semiconductor die is a first semiconductor die, the method further comprising:
electrically coupling an active side of a second semiconductor die to the interconnect layer.
9. The method of claim 8, wherein:
an inactive side of the second semiconductor die is attached to the first semiconductor die using an adhesive; and
the active side of the second semiconductor die is electrically coupled to the interconnect layer using one or more bonding wires.
10. The method of claim 1, further comprising:
forming a de-coupling capacitor on the semiconductor substrate; and
forming an electro-static discharge (ESD) protection device on the semiconductor substrate to protect against electro-static discharge, wherein the de-coupling capacitor and the ESD protection device are formed prior to attaching the semiconductor die to the semiconductor substrate.
11. An apparatus comprising:
a semiconductor substrate comprising a semiconductor material;
a dielectric layer formed on the semiconductor substrate;
an interconnect layer formed on the dielectric layer; and
a semiconductor die attached to the semiconductor substrate, wherein an active side of the semiconductor die is electrically coupled to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die.
12. The apparatus of claim 11, wherein:
the semiconductor die is attached to the semiconductor substrate in a flip-chip configuration; and
the active side of the semiconductor die is electrically coupled to the interconnect layer using one or more bumps.
13. The apparatus of claim 11, wherein:
the semiconductor die is attached to the semiconductor substrate in a wirebonding configuration;
an inactive side of the semiconductor die is attached to the semiconductor substrate using an adhesive; and
the active side of the semiconductor die is electrically coupled to the interconnect layer using one or more bonding wires.
14. The apparatus of claim 11, further comprising:
one or more package interconnect structures formed on the interconnect layer to further route the electrical signals of the semiconductor die.
15. The apparatus of claim 14, further comprising:
a printed circuit board, wherein the semiconductor substrate is (i) mounted on the printed circuit board and (ii) electrically coupled to the printed circuit board using the one or more package interconnect structures.
16. The apparatus of claim 11, further comprising:
a molding compound disposed to substantially encapsulate the semiconductor die.
17. The apparatus of claim 11, wherein the semiconductor die is attached to a first side of the semiconductor substrate, the apparatus further comprising:
a molding compound disposed to substantially cover a second side of the semiconductor substrate, the second side being disposed opposite to the first side of the semiconductor substrate.
18. The apparatus of claim 11, wherein the semiconductor die is attached to a first side of the semiconductor substrate, the apparatus further comprising:
a heat spreader thermally coupled to a second side of the semiconductor substrate, the second side being disposed opposite to the first side of the semiconductor substrate.
19. The apparatus of claim 11, wherein the semiconductor die is attached to a first side of the semiconductor substrate, the apparatus further comprising:
one or more recessed regions formed in the second side of the semiconductor substrate to increase a surface area of the second side of the semiconductor substrate.
20. The apparatus of claim 11, wherein the semiconductor die is a first semiconductor die, the apparatus further comprising:
a second semiconductor die, wherein an active side of the second semiconductor die is electrically coupled to the interconnect layer.
21. The apparatus of claim 20, wherein:
an inactive side of the second semiconductor die is attached to the first semiconductor die using an adhesive; and
the active side of the second semiconductor die is electrically coupled to the interconnect layer using one or more bonding wires.
22. The apparatus of claim 11, wherein the semiconductor substrate comprises:
a de-coupling capacitor formed on the semiconductor substrate to reduce noise associated with the electrical signals; and
an electro-static discharge (ESD) protection device formed on the semiconductor substrate to protect against electro-static discharge.
23. The apparatus of claim 11, wherein:
the semiconductor substrate comprises silicon;
the semiconductor die comprises silicon;
the dielectric layer comprises at least one of silicon dioxide (SiO2), silicon nitride (SiN), and silicon oxynitride (SiOxNy); and
the interconnect layer comprises a metal.
US12/973,249 2010-01-18 2010-12-20 Package assembly having a semiconductor substrate Abandoned US20110175218A1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US29592510P true 2010-01-18 2010-01-18
US32855610P true 2010-04-27 2010-04-27
US33354210P true 2010-05-11 2010-05-11
US34715610P true 2010-05-21 2010-05-21
US35085210P true 2010-06-02 2010-06-02
US12/973,249 US20110175218A1 (en) 2010-01-18 2010-12-20 Package assembly having a semiconductor substrate

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US12/973,249 US20110175218A1 (en) 2010-01-18 2010-12-20 Package assembly having a semiconductor substrate
KR1020127021633A KR20120127460A (en) 2010-01-18 2010-12-21 Package assembly having a semiconductor substrate
CN201080061743.XA CN102714190B (en) 2010-01-18 2010-12-21 Package assembly having a semiconductor substrate
PCT/US2010/061630 WO2011087798A1 (en) 2010-01-18 2010-12-21 Package assembly having a semiconductor substrate
TW100101828A TWI521616B (en) 2010-01-18 2011-01-18 Package assembly having a semiconductor substrate
US13/648,114 US20130026609A1 (en) 2010-01-18 2012-10-09 Package assembly including a semiconductor substrate with stress relief structure
US14/678,304 US9275929B2 (en) 2010-01-18 2015-04-03 Package assembly having a semiconductor substrate

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US13/648,114 Continuation-In-Part US20130026609A1 (en) 2010-01-18 2012-10-09 Package assembly including a semiconductor substrate with stress relief structure
US14/678,304 Continuation US9275929B2 (en) 2010-01-18 2015-04-03 Package assembly having a semiconductor substrate

Publications (1)

Publication Number Publication Date
US20110175218A1 true US20110175218A1 (en) 2011-07-21

Family

ID=44276983

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/973,249 Abandoned US20110175218A1 (en) 2010-01-18 2010-12-20 Package assembly having a semiconductor substrate
US14/678,304 Active US9275929B2 (en) 2010-01-18 2015-04-03 Package assembly having a semiconductor substrate

Family Applications After (1)

Application Number Title Priority Date Filing Date
US14/678,304 Active US9275929B2 (en) 2010-01-18 2015-04-03 Package assembly having a semiconductor substrate

Country Status (5)

Country Link
US (2) US20110175218A1 (en)
KR (1) KR20120127460A (en)
CN (1) CN102714190B (en)
TW (1) TWI521616B (en)
WO (1) WO2011087798A1 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130113115A1 (en) * 2011-11-07 2013-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. System in package process flow
CN103988294A (en) * 2011-10-10 2014-08-13 马维尔国际贸易有限公司 Package assembly including a semiconductor substrate with stress relief structure
US9130365B2 (en) 2012-03-14 2015-09-08 General Electric Company Method and system for ultra miniaturized packages for transient voltage suppressors
US20160118365A1 (en) * 2014-10-22 2016-04-28 Freescale Semiconductor, Inc. Die attachment for packaged semiconductor device
US9666539B1 (en) * 2015-12-03 2017-05-30 International Business Machines Corporation Packaging for high speed chip to chip communication
US9768144B2 (en) 2010-02-03 2017-09-19 Marvell World Trade Ltd. Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101640076B1 (en) * 2014-11-05 2016-07-15 앰코 테크놀로지 코리아 주식회사 Stacked chip package and method for manufacturing the same
CN104882419B (en) * 2015-05-08 2017-11-24 无锡中感微电子股份有限公司 Chip Package
US10078098B2 (en) 2015-06-23 2018-09-18 Analog Devices, Inc. Z axis accelerometer design with offset compensation
US9673148B2 (en) * 2015-11-03 2017-06-06 Dyi-chung Hu System in package
US10014218B1 (en) * 2017-04-20 2018-07-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming semiconductor device structure with bumps
US10096576B1 (en) * 2017-06-13 2018-10-09 Micron Technology, Inc. Semiconductor device assemblies with annular interposers

Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5291062A (en) * 1993-03-01 1994-03-01 Motorola, Inc. Area array semiconductor device having a lid with functional contacts
US5659203A (en) * 1995-06-07 1997-08-19 International Business Machines Corporation Reworkable polymer chip encapsulant
US5977640A (en) * 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
US6222246B1 (en) * 1999-01-08 2001-04-24 Intel Corporation Flip-chip having an on-chip decoupling capacitor
US6285559B1 (en) * 1998-05-26 2001-09-04 Nec Corporation Multichip module
US6356453B1 (en) * 2000-06-29 2002-03-12 Amkor Technology, Inc. Electronic package having flip chip integrated circuit and passive chip component
US20030160325A1 (en) * 2002-02-22 2003-08-28 Fujitsu Limited Semiconductor device substrate and manufacturing method thereof and semiconductor package
US6753205B2 (en) * 2001-09-13 2004-06-22 Tru-Si Technologies, Inc. Method for manufacturing a structure comprising a substrate with a cavity and a semiconductor integrated circuit bonded to a contact pad located in the cavity
US20050121686A1 (en) * 2003-12-09 2005-06-09 Bernd Keller Semiconductor light emitting devices and submounts and methods for forming the same
US6984544B2 (en) * 2000-07-12 2006-01-10 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
US20070035008A1 (en) * 2005-08-09 2007-02-15 Chipmos Technologies (Bermuda) Ltd. Chipmos Technologies Inc. Thin IC package for improving heat dissipation from chip backside
US7268012B2 (en) * 2004-08-31 2007-09-11 Micron Technology, Inc. Methods for fabrication of thin semiconductor assemblies including redistribution layers and packages and assemblies formed thereby
US20080117607A1 (en) * 2006-11-22 2008-05-22 Shinko Electric Industries Co., Ltd. Electronic component and method for manufacturing the same
US20080197491A1 (en) * 2007-02-20 2008-08-21 Nec Electronics Corporation Semiconductor device and method for producing the same
US20090101897A1 (en) * 2006-01-20 2009-04-23 Hymite A/S Package for a light emitting element
US20090243100A1 (en) * 2008-03-27 2009-10-01 Jotaro Akiyama Methods to Form a Three-Dimensionally Curved Pad in a Substrate and Integrated Circuits Incorporating such a Substrate
US20090283899A1 (en) * 2008-05-16 2009-11-19 Kimyung Yoon Semiconductor Device
US20090302485A1 (en) * 2008-06-05 2009-12-10 Powertech Technology Inc. Laminate substrate and semiconductor package utilizing the substrate
US20100148336A1 (en) * 2008-12-12 2010-06-17 Byung Tai Do Integrated circuit packaging system having through silicon vias with partial depth metal fill regions and method of manufacture thereof
US20100164079A1 (en) * 2005-06-29 2010-07-01 Koninklijke Philips Electronics, N.V. Method of manufacturing an assembly and assembly
US7808075B1 (en) * 2006-02-07 2010-10-05 Marvell International Ltd. Integrated circuit devices with ESD and I/O protection

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200362A (en) 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
JP2830903B2 (en) 1995-07-21 1998-12-02 日本電気株式会社 A method of manufacturing a semiconductor device
US6833613B1 (en) 1997-12-18 2004-12-21 Micron Technology, Inc. Stacked semiconductor package having laser machined contacts
DE19930308B4 (en) 1999-07-01 2006-01-12 Infineon Technologies Ag Multichip module with silicon carrier substrate
DE10004647C1 (en) 2000-02-03 2001-07-26 Infineon Technologies Ag A method of manufacturing a semiconductor device having a multi-chip module and a silicon support substrate
US7010854B2 (en) 2002-04-10 2006-03-14 Formfactor, Inc. Re-assembly process for MEMS structures
JP4115326B2 (en) * 2003-04-15 2008-07-09 新光電気工業株式会社 A method of manufacturing a semiconductor package
TWI249231B (en) 2004-12-10 2006-02-11 Phoenix Prec Technology Corp Flip-chip package structure with embedded chip in substrate
TWI241697B (en) 2005-01-06 2005-10-11 Siliconware Prec Ind Co Ltd Semiconductor package and fabrication method thereof
DE102005014049B4 (en) 2005-03-23 2010-11-25 Diana Diehl Holder and bag using derselbigen
US7327029B2 (en) 2005-09-27 2008-02-05 Agere Systems, Inc. Integrated circuit device incorporating metallurigical bond to enhance thermal conduction to a heat sink
WO2007115371A1 (en) * 2006-04-10 2007-10-18 Epitactix Pty Ltd Method, apparatus and resulting structures in the manufacture of semiconductors
KR100800478B1 (en) * 2006-07-18 2008-02-04 삼성전자주식회사 Stack type semiconductor package and method of fabricating the same
JP2008166373A (en) * 2006-12-27 2008-07-17 Nec Electronics Corp Semiconductor device and its manufacturing method
TWI345823B (en) 2007-03-21 2011-07-21 Powertech Technology Inc Semiconductor package with wire-bonding connections
TWI351751B (en) 2007-06-22 2011-11-01 Ind Tech Res Inst Self-aligned wafer or chip structure, self-aligned
KR101329355B1 (en) * 2007-08-31 2013-11-20 삼성전자주식회사 stack-type semicondoctor package, method of forming the same and electronic system including the same
US7777351B1 (en) * 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
KR20150068495A (en) 2007-11-30 2015-06-19 스카이워크스 솔루션즈, 인코포레이티드 Wafer level packaging using flip chip mounting
US7741194B2 (en) * 2008-01-04 2010-06-22 Freescale Semiconductor, Inc. Removable layer manufacturing method
JP2009231584A (en) 2008-03-24 2009-10-08 Japan Gore Tex Inc Method of manufacturing led substrate and the led substrate
US8030780B2 (en) 2008-10-16 2011-10-04 Micron Technology, Inc. Semiconductor substrates with unitary vias and via terminals, and associated systems and methods
US8704350B2 (en) * 2008-11-13 2014-04-22 Samsung Electro-Mechanics Co., Ltd. Stacked wafer level package and method of manufacturing the same
US7858441B2 (en) * 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
TWI499024B (en) * 2009-01-07 2015-09-01 Advanced Semiconductor Eng Package-on-package device, semiconductor package and method for manufacturing the same
US20110186960A1 (en) 2010-02-03 2011-08-04 Albert Wu Techniques and configurations for recessed semiconductor substrates

Patent Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5291062A (en) * 1993-03-01 1994-03-01 Motorola, Inc. Area array semiconductor device having a lid with functional contacts
US5659203A (en) * 1995-06-07 1997-08-19 International Business Machines Corporation Reworkable polymer chip encapsulant
US6285559B1 (en) * 1998-05-26 2001-09-04 Nec Corporation Multichip module
US5977640A (en) * 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
US6222246B1 (en) * 1999-01-08 2001-04-24 Intel Corporation Flip-chip having an on-chip decoupling capacitor
US6356453B1 (en) * 2000-06-29 2002-03-12 Amkor Technology, Inc. Electronic package having flip chip integrated circuit and passive chip component
US6984544B2 (en) * 2000-07-12 2006-01-10 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
US6753205B2 (en) * 2001-09-13 2004-06-22 Tru-Si Technologies, Inc. Method for manufacturing a structure comprising a substrate with a cavity and a semiconductor integrated circuit bonded to a contact pad located in the cavity
US20030160325A1 (en) * 2002-02-22 2003-08-28 Fujitsu Limited Semiconductor device substrate and manufacturing method thereof and semiconductor package
US20050121686A1 (en) * 2003-12-09 2005-06-09 Bernd Keller Semiconductor light emitting devices and submounts and methods for forming the same
US7268012B2 (en) * 2004-08-31 2007-09-11 Micron Technology, Inc. Methods for fabrication of thin semiconductor assemblies including redistribution layers and packages and assemblies formed thereby
US20100164079A1 (en) * 2005-06-29 2010-07-01 Koninklijke Philips Electronics, N.V. Method of manufacturing an assembly and assembly
US20070035008A1 (en) * 2005-08-09 2007-02-15 Chipmos Technologies (Bermuda) Ltd. Chipmos Technologies Inc. Thin IC package for improving heat dissipation from chip backside
US20090101897A1 (en) * 2006-01-20 2009-04-23 Hymite A/S Package for a light emitting element
US7808075B1 (en) * 2006-02-07 2010-10-05 Marvell International Ltd. Integrated circuit devices with ESD and I/O protection
US20080117607A1 (en) * 2006-11-22 2008-05-22 Shinko Electric Industries Co., Ltd. Electronic component and method for manufacturing the same
US20080197491A1 (en) * 2007-02-20 2008-08-21 Nec Electronics Corporation Semiconductor device and method for producing the same
US20090243100A1 (en) * 2008-03-27 2009-10-01 Jotaro Akiyama Methods to Form a Three-Dimensionally Curved Pad in a Substrate and Integrated Circuits Incorporating such a Substrate
US20090283899A1 (en) * 2008-05-16 2009-11-19 Kimyung Yoon Semiconductor Device
US20090302485A1 (en) * 2008-06-05 2009-12-10 Powertech Technology Inc. Laminate substrate and semiconductor package utilizing the substrate
US20100148336A1 (en) * 2008-12-12 2010-06-17 Byung Tai Do Integrated circuit packaging system having through silicon vias with partial depth metal fill regions and method of manufacture thereof

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9768144B2 (en) 2010-02-03 2017-09-19 Marvell World Trade Ltd. Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate
CN103988294A (en) * 2011-10-10 2014-08-13 马维尔国际贸易有限公司 Package assembly including a semiconductor substrate with stress relief structure
US20130113115A1 (en) * 2011-11-07 2013-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. System in package process flow
US10163877B2 (en) * 2011-11-07 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. System in package process flow
US9130365B2 (en) 2012-03-14 2015-09-08 General Electric Company Method and system for ultra miniaturized packages for transient voltage suppressors
US20160118365A1 (en) * 2014-10-22 2016-04-28 Freescale Semiconductor, Inc. Die attachment for packaged semiconductor device
US9559077B2 (en) * 2014-10-22 2017-01-31 Nxp Usa, Inc. Die attachment for packaged semiconductor device
US9666539B1 (en) * 2015-12-03 2017-05-30 International Business Machines Corporation Packaging for high speed chip to chip communication

Also Published As

Publication number Publication date
US9275929B2 (en) 2016-03-01
TW201140717A (en) 2011-11-16
KR20120127460A (en) 2012-11-21
WO2011087798A1 (en) 2011-07-21
TWI521616B (en) 2016-02-11
US20150221577A1 (en) 2015-08-06
CN102714190B (en) 2016-11-30
CN102714190A (en) 2012-10-03

Similar Documents

Publication Publication Date Title
US9153494B2 (en) Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV
US9224647B2 (en) Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer
US8076770B2 (en) Semiconductor device including a first land on the wiring substrate and a second land on the sealing portion
US10109573B2 (en) Packaged semiconductor devices and packaging devices and methods
US8492201B2 (en) Semiconductor device and method of forming through vias with reflowed conductive material
US10079159B2 (en) Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
US8183678B2 (en) Semiconductor device having an interposer
US8021907B2 (en) Method and apparatus for thermally enhanced semiconductor package
US8174105B2 (en) Stacked semiconductor package having discrete components
CN103681368B (en) The semiconductor device and a method of line fo-wlp be cylindrical in vertical interconnects
US8466544B2 (en) Semiconductor device and method of forming interposer and opposing build-up interconnect structure with connecting conductive TMV for electrical interconnect of Fo-WLCSP
US8310051B2 (en) Package-on-package with fan-out WLCSP
US9059186B2 (en) Embedded semiconductor die package and method of making the same using metal frame carrier
US8791562B2 (en) Stack package and semiconductor package including the same
US20110024916A1 (en) Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias
US8169058B2 (en) Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars
US8883561B2 (en) Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP
KR101692120B1 (en) Semiconductor package including an embedded surface mount device and method of forming the same
US9852969B2 (en) Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US20080169548A1 (en) Semiconductor package having a semiconductor chip in a substrate and method of fabricating the same
US9343429B2 (en) Semiconductor device and method of forming double-sided through vias in saw streets
CN102376595B (en) The method of forming fo-wlcsp having a conductive layer and the conductive vias and the semiconductor device
US20110124156A1 (en) Method of Fabricating Semiconductor Die with Through-Hole Via on Saw Streets and Through-Hole Via in Active Area of Die
US8445323B2 (en) Semiconductor package with semiconductor core structure and method of forming same
US7768115B2 (en) Stack chip and stack chip package having the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: MARVELL SEMICONDUCTOR, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIOU, SHIANN-MING;SUTARDJA, SEHAT;WU, ALBERT;AND OTHERS;SIGNING DATES FROM 20101208 TO 20101215;REEL/FRAME:025531/0558

Owner name: MARVELL INTERNATIONAL LTD., BERMUDA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MARVELL SEMICONDUCTOR, INC.;REEL/FRAME:025531/0494

Effective date: 20101216

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: MARVELL WORLD TRADE LTD., BARBADOS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MARVELL INTERNATIONAL LTD.;REEL/FRAME:037454/0640

Effective date: 20101217

Owner name: MARVELL INTERNATIONAL LTD., BERMUDA

Free format text: LICENSE;ASSIGNOR:MARVELL WORLD TRADE LTD.;REEL/FRAME:037478/0514

Effective date: 20101217