CN105514087A - Double-faced fan-out type wafer-level packaging method and packaging structure - Google Patents

Double-faced fan-out type wafer-level packaging method and packaging structure Download PDF

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Publication number
CN105514087A
CN105514087A CN201610051002.2A CN201610051002A CN105514087A CN 105514087 A CN105514087 A CN 105514087A CN 201610051002 A CN201610051002 A CN 201610051002A CN 105514087 A CN105514087 A CN 105514087A
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China
Prior art keywords
wiring layer
type wafer
level packaging
sided fan
electrode bumps
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CN201610051002.2A
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Chinese (zh)
Inventor
蔡奇风
林正忠
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SJ Semiconductor Jiangyin Corp
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SJ Semiconductor Jiangyin Corp
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Priority to CN201610051002.2A priority Critical patent/CN105514087A/en
Publication of CN105514087A publication Critical patent/CN105514087A/en
Priority to PCT/CN2016/082830 priority patent/WO2017128567A1/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/02379—Fan-out arrangement
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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Abstract

The invention provides a double-faced fan-out type wafer-level packaging method and packaging structure. The packaging structure comprises a substrate, a first rewiring layer, a second rewiring layer, through hole electrodes, a first device, first electrode protruding blocks, a first curing material, a second device, second electrode protruding blocks and a second curing material, the first rewiring layer and the second rewiring layer are connected through the through hole electrodes, and each electrode protrudes out of the surface of the corresponding curing material. According to the double-faced fan-out type wafer-level packaging method and packaging structure, interconnecting of the double-faced devices is achieved by forming electrode through holes, vertical interconnection of a multilayer packaging structure can be achieved, and different electronic equipment functions are achieved; the rewiring layers are fabricated before chip adhesion, so that chip shifting is avoided; the structure is bonded to a carrier, so that warping of the structure is avoided; the electrode protruding blocks are used for interconnection and outputting, so that integration of different devices is guaranteed; outputting of the electrode protruding blocks is controlled by controlling the thickness of the curing materials, so that the grinding process of the curing materials is omitted; through double-faced fan-out packaging, the integration level of the devices is greatly improved.

Description

Two-sided fan-out-type wafer-level packaging method and encapsulating structure
Technical field
The invention belongs to field of semiconductor package, particularly relate to a kind of two-sided fan-out-type wafer-level packaging method and encapsulating structure.
Background technology
Fan-out-type wafer-level packaging (Fan-outWaferLevelpackage, FOWLP) being a kind of embedded chip method for packing of wafer level processing, is one of good Advanced Packaging method of more, the integrated flexibility of current a kind of input/output end port (I/O).Fan-out-type wafer-level packaging has the advantage of its uniqueness compared to the wafer-level packaging of routine: 1. I/O spacing is flexible, does not rely on chip size; 2. only use effective die, product yield improves; 3. there is 3D package path flexibly, namely can form the figure of General Cell at top; 4. there is good electrical property and hot property; 5. frequency applications; 6. easily in re-wiring layer (RDL), high-density wiring is realized.
Existing fan-out-type wafer-level packaging method is generally: provide carrier, forms adhesive layer at carrier surface; Semiconductor chip is faced up and is mounted on adhesive layer surface; Dielectric layer; Photoetching, electroplate out re-wiring layer (RDL); Adopt Shooting Technique by semiconductor chip plastic packaging in capsulation material layer; Plastic packaging grinding, opening; Photoetching, electroplate out ball lower metal layer; Carry out planting ball backflow, form welded ball array; Remove carrier.And, prior art in the process of the techniques such as moulding process and follow-up solder reflow, the defect such as easily occur warpage, break, thus reduce the rate of finished products of encapsulating products.Chip can be packaged on two surfaces of same substrate by two-sided fan-out-type chip encapsulation technology simultaneously, greatly can improve the integrated level of device, reduce costs.Simultaneously by the application of carrier, reduce warpage, improve rate of finished products in view of above reason, provide that a kind of step is simple, low cost and effectively improve integrated level, the two-sided fan-out-type wafer-level packaging method of rate of finished products and encapsulating structure are necessary.
Summary of the invention
The feature of prior art in view of the above, the object of the present invention is to provide a kind of novel two-sided fan-out-type wafer-level packaging method and encapsulating structure, for improving in prior art the integrated level encapsulating finished product, reducing costs.
For achieving the above object and other relevant objects, the invention provides a kind of two-sided fan-out-type wafer-level packaging method, comprise step: step 1), a substrate is provided, makes the first re-wiring layer in described substrate first surface; Step 2), the first device is attached to described first re-wiring layer, and realizes the electric connection of the first device and the first re-wiring layer; Step 3), on described first re-wiring layer, make the first electrode bumps; Step 4), moulding process is carried out to the first device, after shaping, exposes described first electrode bumps; Step 5), there is the one side of the first electrode bumps to be bonded on a carrier based on adhesive layer by exposing; Step 6), in described substrate, form the through hole electrode between the second surface through described first re-wiring layer and substrate; Step 7), make the second re-wiring layer in the second surface of described substrate, and realize the electric connection of each through hole electrode and the second re-wiring layer; Step 8), the second device is attached to described second re-wiring layer, and realizes the electric connection of the second device and the second re-wiring layer; Step 9), on described second re-wiring layer, make the second electrode bumps; Step 10), moulding process is carried out to the second device, after shaping, exposes described second electrode bumps; Step 11), remove described adhesive layer and carrier.
As a kind of preferred version of two-sided fan-out-type wafer-level packaging method of the present invention, described first re-wiring layer and the second re-wiring layer comprise patterned dielectric layer and patterned metal wiring layer.
Preferably, the material of described dielectric layer comprises epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, one or more combinations in fluorine-containing glass.
Preferably, the material of described metal wiring layer comprises one or more combinations in copper, aluminium, nickel, gold, silver, titanium.
As a kind of preferred version of two-sided fan-out-type wafer-level packaging method of the present invention, described first device and the second device comprise one or both combinations in bare chip and packaged chip.
As a kind of preferred version of two-sided fan-out-type wafer-level packaging method of the present invention, step 3) comprising: step 3-1), on described first re-wiring layer, make copper post; Step 3-2), on described copper post, make nickel dam; Step 3-3), on described nickel dam, make solder metal, and carry out high temperature reflux formation solder ball, to complete the preparation of the first electrode bumps.
As a kind of preferred version of two-sided fan-out-type wafer-level packaging method of the present invention, step 4) and step 10) the curing materials that adopts of moulding process comprise one in polyimides, silica gel and epoxy resin.
As a kind of preferred version of two-sided fan-out-type wafer-level packaging method of the present invention, the material of described carrier comprises one or more the composite material in silicon, glass, silica, pottery, polymer and metal.
As a kind of preferred version of two-sided fan-out-type wafer-level packaging method of the present invention, described adhesive layer comprises one deck separating layer, step 10) in can be irradiated by UV or laser is removed, device is separated with carrier; Remaining adhesive layer is removed by chemical reagent, and adhesive layer is separated with the first projection.
As a kind of preferred version of two-sided fan-out-type wafer-level packaging method of the present invention, step 9) comprising: step 9-1), on described second re-wiring layer, make copper post; Step 9-2), on described copper post, make nickel dam; Step 9-3), on described nickel dam, make solder metal, and carry out high temperature reflux formation solder ball, to complete the preparation of the second electrode bumps.
The present invention also provides a kind of two-sided fan-out-type wafer level packaging structure, comprise: substrate, the first surface of described substrate is formed with the first re-wiring layer, second surface is formed with the second re-wiring layer, and is formed with the through hole electrode connecting described first re-wiring layer and the second re-wiring layer in described substrate; First device, is fixed on described first re-wiring layer, and with the electric connection of the first re-wiring layer; First electrode bumps, is formed on described first re-wiring layer; First curing materials, is covered in described first device surface, and exposes and have described first electrode bumps; Second device, is fixed on described second re-wiring layer, and with the electric connection of the second re-wiring layer; Second electrode bumps, is formed on described second re-wiring layer; Second curing materials, is covered in described second device surface, and exposes and have described second electrode bumps.
As a kind of preferred version of two-sided fan-out-type wafer level packaging structure of the present invention, described first re-wiring layer and the second re-wiring layer comprise patterned dielectric layer and patterned metal wiring layer.
As a kind of preferred version of two-sided fan-out-type wafer level packaging structure of the present invention, the material of described dielectric layer comprises epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, one or more combinations in fluorine-containing glass.
As a kind of preferred version of two-sided fan-out-type wafer level packaging structure of the present invention, the material of described metal wiring layer comprises one or more combinations in copper, aluminium, nickel, gold, silver, titanium
As a kind of preferred version of two-sided fan-out-type wafer level packaging structure of the present invention, described first device and the second device comprise one or both combinations in bare chip and packaged chip.
As a kind of preferred version of two-sided fan-out-type wafer level packaging structure of the present invention, described curing materials comprises the one in polyimides, silica gel and epoxy resin.
As a kind of preferred version of two-sided fan-out-type wafer level packaging structure of the present invention, described first electrode bumps and the second electrode bumps comprise copper post, are formed at the nickel dam on described copper post and are formed at described solder ball.
As mentioned above, two-sided fan-out-type wafer-level packaging method of the present invention and encapsulating structure, have following beneficial effect:
1) by making the interconnection that electrode through hole realizes between double-sided device in substrate, this structure can realize the perpendicular interconnection of multilayer encapsulation structure, realizes different electronic functionalities;
2) before re-wiring layer is made in die attach, the chip in forming process can be avoided to be shifted, avoid line abnormal;
3) by structure bond on carrier, avoid and make the structure warpage caused in the process of re-wiring layer and solder ball, the defect such as to break;
4) electrode bumps is adopted to draw, for the integrated of multiple different components provides effective guarantee as interconnection;
5) thickness by controlling curing materials carrys out the extraction of control electrode projection, saves the techniques such as the grinding of curing materials.
Accompanying drawing explanation
Fig. 1 ~ Figure 15 is shown as the structural representation that each step of two-sided fan-out-type wafer-level packaging method of the present invention presents, and wherein, Figure 15 is shown as the structural representation of two-sided fan-out-type wafer level packaging structure of the present invention.
Element numbers explanation
101 substrates
102 first re-wiring layers
103 bare chips
104 packaged chips
105 first electrode bumps
106 first curing materials
107 adhesive layers
108 carriers
109 through hole electrodes
110 second re-wiring layers
111 packaged chips
112 bare chips
113 second electrode bumps
114 second curing materials
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 1 ~ Figure 15.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in diagram but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
As shown in Fig. 1 ~ Figure 15, the present embodiment provides a kind of two-sided fan-out-type wafer-level packaging method, comprises step:
As shown in Fig. 1 ~ Fig. 2, first carry out step 1), a substrate 101 is provided, makes the first re-wiring layer 102 in described substrate 101 first surface.
Exemplarily, described substrate 101 can be made for materials such as silicon, silicon dioxide, BCB plate, pottery, glass, polymer.
Exemplarily, described first re-wiring layer 102 comprises patterned dielectric layer and patterned metal wiring layer.The material of described dielectric layer comprises epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, the one in fluorine-containing glass.The material of described metal wiring layer comprises one or more combinations in copper, aluminium, nickel, gold, silver, titanium.
As shown in Figure 3, then carry out step 2), the first device is attached to described first re-wiring layer 102, and realizes the electric connection of the first device and the first re-wiring layer 102.
Exemplarily, described first device comprises one or more combinations in bare chip and packaged chip.In the present embodiment, described first device comprises two kinds of devices, and wherein, a kind of device is bare chip 103, and another kind of device is packaged chip 104, and described first device can be the device architecture realizing any function, is not limited to cited example herein.
As shown in Figure 4, then carry out step 3), on described first re-wiring layer 102, make the first electrode bumps 105.
Exemplarily, step 3) comprising:
Step 3-1), on described first re-wiring layer 102, make copper post;
Step 3-2), on described copper post, make nickel dam;
Step 3-3), on described nickel dam, make solder metal, and carry out high temperature reflux formation solder ball, to complete the preparation of the first electrode bumps 105.Exemplarily, described solder metal is silver-colored ashbury metal.
As shown in Figure 5, then carry out step 4), moulding process is carried out to the first device, after shaping, exposes described first electrode bumps 105.
Exemplarily, by controlling the thickness of the first curing materials of described moulding process, realizing exposing of described first electrode bumps 105, to save follow-up grinding with the technique the first electrode bumps exposed, greatly having saved process costs.
Exemplarily, the first curing materials 106 that the moulding process of this step adopts comprises the one in polyimides, silica gel and epoxy resin.
Exemplarily, moulding process can comprise spin coating proceeding, Shooting Technique, compressing and forming process, typography, transfer modling technique, fluid sealant cure process and vacuum lamination process etc.Exemplarily, compressing and forming process is used herein.
As shown in Figure 6, then carry out step 5), there is the one side of the first electrode bumps 105 to be bonded on a carrier 108 based on adhesive layer 107 by exposing.
Exemplarily, the material of described carrier 108 comprises one or more the composite material in silicon, glass, silica, pottery, polymer and metal.
Exemplarily, described adhesive layer 107 can be adhesive tape, epoxy resin, UV adhesive glue etc., and follow-up removal technique can be exposure method, laser ablation, solution corrosion etc.In the present embodiment, described adhesive layer 107 comprises a separating layer, the step 10 follow-up) in, adopt laser ablation to remove separating layer, then remove remaining adhesive layer to realize its being separated with the first electrode bumps 105 with chemical reagent.
As shown in Fig. 7 ~ Figure 10, then carry out step 6), thinning described substrate 101, forms the through hole electrode 109 between the second surface through described first re-wiring layer 102 and substrate 101 in described substrate 101.
Particularly, this step comprises:
As shown in Figure 7, first carry out step 6-1), by the thinning described substrate 101 of Ginding process;
As shown in Figure 8, then carry out step 6-2), in described base, form through hole by photoetching-method such as etching or laser;
As shown in Figure 9, then carry out step 6-3), deposit metallic material in described through hole, as copper, aluminium etc.;
As shown in Figure 10, finally carry out step 6-4), remove the metal material of substrate 101 excess surface, can polishing processes or etch etc. be adopted as.
As shown in figure 11, then carry out step 7), make and the second re-wiring layer 110 in the second surface of described substrate 101, and realize the electric connection of each through hole electrode 109 and the second re-wiring layer 110.
Exemplarily, described second re-wiring layer 110 comprises patterned dielectric layer and patterned metal wiring layer.The material of described dielectric layer comprises epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, the one in fluorine-containing glass.The material of described metal wiring layer comprises one or more combinations in copper, aluminium, nickel, gold, silver, titanium.
As shown in figure 12, then carry out step 8), the second device is attached to described second re-wiring layer 110, and realizes the electric connection of the second device and the second re-wiring layer 110.
Exemplarily, described second device comprises one or more combinations in bare chip and packaged chip.In the present embodiment, described second device comprises two kinds of different devices, one is bare chip 112, another kind is packaged chip 111, wherein, described second device and the first device can be identical chip, also can be different chips, can according to needing to select the device of difference in functionality to carry out integrated, to meet different application demands.
As shown in figure 13, then carry out step 9), on described second re-wiring layer 110, make the second electrode bumps 113.
Exemplarily, step 9) comprising:
Step 9-1), on described second re-wiring layer 110, make copper post;
Step 9-2), on described copper post, make nickel dam;
Step 9-3), on described nickel dam, make solder metal, and carry out high temperature reflux formation solder ball, to complete the preparation of the second electrode bumps 113.In the present embodiment, described solder metal is silver-colored ashbury metal.
As shown in figure 14, then carry out step 10), moulding process is carried out to the second device, after shaping, exposes described second electrode bumps 113.
Exemplarily, by controlling the thickness of the second curing materials of described moulding process, realizing exposing of described second electrode bumps 113, to save follow-up grinding with the technique the second electrode bumps exposed, greatly having saved process costs.
Exemplarily, the second curing materials 114 that moulding process adopts comprises the one in polyimides, silica gel and epoxy resin.
As shown in figure 15, finally carry out step 11), remove described adhesive layer 107 and carrier 108.
Exemplarily, described adhesive layer 107 comprises one deck separating layer, adopts laser ablation to remove separating layer, then removes remaining adhesive layer with chemical reagent, carrier is separated with the first electrode bumps 105.As shown in figure 15, the present embodiment also provides a kind of two-sided fan-out-type wafer level packaging structure, comprise: substrate 101, the first surface of described substrate 101 is formed with the first re-wiring layer 102, second surface is formed with the second re-wiring layer 110, and is formed with the through hole electrode 109 connecting described first re-wiring layer 102 and the second re-wiring layer 110 in described substrate 101; First device, is fixed on described first re-wiring layer 102, and with the electric connection of the first re-wiring layer 102; First electrode bumps 105, is formed on described first re-wiring layer 102; First curing materials 106, is covered in described first device surface, and exposes and have described first electrode bumps 105; Second device, is fixed on described second re-wiring layer 110, and with the electric connection of the second re-wiring layer 110; Second electrode bumps 113, is formed on described second re-wiring layer 110; Second curing materials 114, is covered in described second device surface, and exposes and have described second electrode bumps 113.
Exemplarily, described first re-wiring layer 102 and the second re-wiring layer 110 comprise patterned dielectric layer and patterned metal wiring layer.
Exemplarily, the material of described dielectric layer comprises epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, one or more combinations in fluorine-containing glass.
Exemplarily, the material of described metal wiring layer comprises one or more combinations in copper, aluminium, nickel, gold, silver, titanium.
Exemplarily, described first device and the second device comprise one or both combinations in bare chip and packaged chip.
Exemplarily, described curing materials comprises the one in polyimides, silica gel and epoxy resin.
Exemplarily, described first electrode bumps 105 and the second electrode bumps 113 comprise copper post, are formed at the nickel dam on described copper post and are formed at described solder ball.
As mentioned above, two-sided fan-out-type wafer-level packaging method of the present invention and encapsulating structure, have following beneficial effect:
1) by making the interconnection that electrode through hole realizes between double-sided device in substrate 101, this structure can realize the perpendicular interconnection of multilayer encapsulation structure, realizes different electronic functionalities;
2) before re-wiring layer is made in die attach, the chip in forming process can be avoided to be shifted, avoid line abnormal;
3) by structure bond on carrier 108, avoid and make the structure warpage caused in the process of re-wiring layer and solder ball, the defect such as to break;
4) electrode bumps is adopted to draw, for the integrated of multiple different components provides effective guarantee as interconnection;
5) thickness by controlling curing materials carrys out the extraction of control electrode projection, saves the techniques such as the grinding of curing materials.
So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.

Claims (17)

1. a two-sided fan-out-type wafer-level packaging method, is characterized in that, comprise step:
Step 1), a substrate is provided, makes the first re-wiring layer in described substrate first surface;
Step 2), the first device is attached to described first re-wiring layer, and realizes the electric connection of the first device and the first re-wiring layer;
Step 3), on described first re-wiring layer, make the first electrode bumps;
Step 4), moulding process is carried out to the first device, after shaping, exposes described first electrode bumps;
Step 5), there is the one side of the first electrode bumps to be bonded on a carrier based on adhesive layer by exposing;
Step 6), in described substrate, form the through hole electrode between the second surface through described first re-wiring layer and substrate;
Step 7), make the second re-wiring layer in the second surface of described substrate, and realize the electric connection of each through hole electrode and the second re-wiring layer;
Step 8), the second device is attached to described second re-wiring layer, and realizes the electric connection of the second device and the second re-wiring layer;
Step 9), on described second re-wiring layer, make the second electrode bumps;
Step 10), moulding process is carried out to the second device, after shaping, exposes described second electrode bumps;
Step 11), remove described adhesive layer and carrier.
2. two-sided fan-out-type wafer-level packaging method according to claim 1, is characterized in that: described first re-wiring layer and the second re-wiring layer comprise patterned dielectric layer and patterned metal wiring layer.
3. two-sided fan-out-type wafer-level packaging method according to claim 2, is characterized in that: the material of described dielectric layer comprises epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, one or more combinations in fluorine-containing glass.
4. two-sided fan-out-type wafer-level packaging method according to claim 2, is characterized in that: the material of described metal wiring layer comprises one or more combinations in copper, aluminium, nickel, gold, silver, titanium.
5. two-sided fan-out-type wafer-level packaging method according to claim 1, is characterized in that: described first device and the second device comprise one or both combinations in bare chip and packaged chip.
6. two-sided fan-out-type wafer-level packaging method according to claim 1, is characterized in that: step 3) comprising:
Step 3-1), on described first re-wiring layer, make copper post;
Step 3-2), on described copper post, make nickel dam;
Step 3-3), on described nickel dam, make solder metal, and carry out high temperature reflux formation solder ball, to complete the preparation of the first electrode bumps.
7. two-sided fan-out-type wafer-level packaging method according to claim 1, is characterized in that: step 4) and step 10) the curing materials that adopts of moulding process comprise one in polyimides, silica gel and epoxy resin.
8. two-sided fan-out-type wafer-level packaging method according to claim 1, is characterized in that: the material of described carrier comprises one or more the composite material in silicon, glass, silica, pottery, polymer and metal.
9. two-sided fan-out-type wafer-level packaging method according to claim 1, is characterized in that: described adhesive layer comprises one deck separating layer, step 10) in can be irradiated by UV or laser is removed, device is separated with carrier; Remaining adhesive layer is removed by chemical reagent, and adhesive layer is separated with the first projection.
10. two-sided fan-out-type wafer-level packaging method according to claim 1, is characterized in that: step 9) comprising:
Step 9-1), on described second re-wiring layer, make copper post;
Step 9-2), on described copper post, make nickel dam;
Step 9-3), on described nickel dam, make solder metal, and carry out high temperature reflux formation solder ball, to complete the preparation of the second electrode bumps.
11. 1 kinds of two-sided fan-out-type wafer level packaging structures, is characterized in that, comprising:
Substrate, the first surface of described substrate is formed with the first re-wiring layer, and second surface is formed with the second re-wiring layer, and is formed with the through hole electrode connecting described first re-wiring layer and the second re-wiring layer in described substrate;
First device, is fixed on described first re-wiring layer, and with the electric connection of the first re-wiring layer;
First electrode bumps, is formed on described first re-wiring layer;
First curing materials, is covered in described first device surface, and exposes and have described first electrode bumps;
Second device, is fixed on described second re-wiring layer, and with the electric connection of the second re-wiring layer;
Second electrode bumps, is formed on described second re-wiring layer;
Second curing materials, is covered in described second device surface, and exposes and have described second electrode bumps.
12. two-sided fan-out-type wafer level packaging structures according to claim 11, is characterized in that: described first re-wiring layer and the second re-wiring layer comprise patterned dielectric layer and patterned metal wiring layer.
13. two-sided fan-out-type wafer level packaging structures according to claim 12, is characterized in that: the material of described dielectric layer comprises epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, one or more combinations in fluorine-containing glass.
14. two-sided fan-out-type wafer level packaging structures according to claim 12, is characterized in that: the material of described metal wiring layer comprises one or more combinations in copper, aluminium, nickel, gold, silver, titanium.
15. two-sided fan-out-type wafer level packaging structures according to claim 11, is characterized in that: described first device and the second device comprise one or both combinations in bare chip and packaged chip.
16. two-sided fan-out-type wafer level packaging structures according to claim 11, is characterized in that: described curing materials comprises the one in polyimides, silica gel and epoxy resin.
17. two-sided fan-out-type wafer level packaging structures according to claim 11, is characterized in that: described first electrode bumps and the second electrode bumps comprise copper post, be formed at the nickel dam on described copper post and be formed at described solder ball.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101320716A (en) * 2007-06-08 2008-12-10 日本电气株式会社 Semiconductor device and method for manufacturing same
US7858441B2 (en) * 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
CN102169841A (en) * 2010-02-03 2011-08-31 马维尔国际贸易有限公司 Recessed semiconductor substrate and associated technique

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202871783U (en) * 2012-08-31 2013-04-10 江阴长电先进封装有限公司 Chip-embedded type stacking-wafer level packaging structure
CN204332941U (en) * 2015-01-27 2015-05-13 江阴长电先进封装有限公司 A kind of 3-D stacks encapsulating structure
CN105514087A (en) * 2016-01-26 2016-04-20 中芯长电半导体（江阴）有限公司 Double-faced fan-out type wafer-level packaging method and packaging structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101320716A (en) * 2007-06-08 2008-12-10 日本电气株式会社 Semiconductor device and method for manufacturing same
US7858441B2 (en) * 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
CN102169841A (en) * 2010-02-03 2011-08-31 马维尔国际贸易有限公司 Recessed semiconductor substrate and associated technique

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US11239194B2 (en) 2017-06-30 2022-02-01 Taiwan Semiconductor Manufacturing Co., Ltd Chip package structure
US11791301B2 (en) 2017-06-30 2023-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package structure
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