CN111348613A

CN111348613A - Packaging method and packaging structure

Info

Publication number: CN111348613A
Application number: CN201811572256.4A
Authority: CN
Inventors: 杨天伦
Original assignee: China Core Integrated Circuit Ningbo Co Ltd
Current assignee: China Core Integrated Circuit Ningbo Co Ltd
Priority date: 2018-12-21
Filing date: 2018-12-21
Publication date: 2020-06-30
Anticipated expiration: 2038-12-21
Also published as: CN111348613B

Abstract

The invention provides a packaging method and a packaging structure, the packaging method comprises bonding a first wafer with a first electrical connection end point and a first device component and a second wafer with a second electrical connection end point and a second device component by adopting a wafer level packaging mode, cutting to form a step-shaped wafer, wherein the second electrical connection end point and the first electrical connection end point in the wafer are distributed in a step shape, bonding the wafer to a third wafer with a third electrical connection end point and a third device component, and exposing the third electrical connection end point of the wafer, so that the first electrical connection end point, the second electrical connection end point and the third electrical connection end point are sequentially distributed in a step shape, thereby reducing the manufacturing process difficulty and the packaging cost of a rewiring structure, and realizing a three-dimensional packaging scheme of integrated packaging of multiple devices, is beneficial to improving the product integration level.

Description

Packaging method and packaging structure

Technical Field

The present invention relates to the field of packaging technologies, and in particular, to a packaging method and a packaging structure.

Background

Micro-Electro-Mechanical System (MEMS) devices have the characteristics of miniaturization, integration, high performance, and low cost, and have been widely used in the fields of automobiles, aerospace, satellite navigation, signal processing, biology, etc. however, most MEMS devices need to work in a vacuum environment or an inert gas airtight environment, however, the vacuum packaging cost of the case level is high, and the low cost requirement of the MEMS devices cannot be met.

Referring to fig. 1, a method for wafer-level vacuum packaging of a MEMS device with two wafers includes the following steps: firstly, aligning a Cap wafer (Cap wafer)104 with a groove 103 structure with a wafer 101 to be packaged of a prepared MEMS device 102; then, bonding the cap wafer 104 and the wafer 101 to be packaged downwards in a vacuum environment, wherein the cap wafer 104 is used for completing the capping of the device, and the groove 103 forms a packaging cavity of the MEMS device 102, thereby completing the wafer-level vacuum packaging of the MEMS device 102; and then, forming an independent packaged MEMS device by scribing.

Referring to fig. 2, another wafer-level vacuum packaging method for a MEMS device using three wafers includes the following steps: firstly, aligning and bonding a second surface of a wafer 101 to be packaged of a prepared MEMS device 102 with a CMOS wafer 100 with a CMOS element 100a in a vacuum environment; then, aligning and bonding a cap wafer 104 with a groove 103 structure with the first surface of the wafer 101 to be packaged in a vacuum environment, and forming a packaging cavity of the MEMS device 102 through the groove 103, thereby completing wafer-level vacuum packaging of the MEMS device 102; and then, forming an independent packaged MEMS device by scribing.

The two packaging methods of the MEMS device have the following defects:

1. the packaging cost is high, and the market competition cannot be met;

2. all the electrical connection terminals to be exposed need to be prepared on the cap wafer 104 shown in fig. 1 or the CMOS wafer 100 shown in fig. 2, which increases the difficulty of the manufacturing process of the electrical connection terminals and the redistribution layer connected thereto, and reduces the electrical reliability of the redistribution structure;

3. as the MEMS devices tend to be complicated, the difficulty of the manufacturing process increases, and all parts of the required MEMS devices or various MEMS devices required for the manufacturing need to be manufactured on one wafer 101 to be packaged, and all circuit structures supporting the operation of the MEMS devices need to be manufactured on the wafer 101 to be packaged shown in fig. 1 or the CMOS wafer 100 shown in fig. 2.

Disclosure of Invention

The invention aims to provide a packaging method and a packaging structure, which are beneficial to simplifying the manufacturing process of a rewiring layer, reducing the manufacturing process difficulty and the packaging cost of a device and improving the electrical connection performance and the product integration level.

In order to achieve the above object, the present invention provides a packaging method, comprising the steps of:

providing a first wafer with a first device component and a second wafer with a second device component, wherein the first wafer is provided with a first surface and a second surface which are arranged in an opposite mode, the first surface of the first wafer is provided with a first electrical connection end point electrically connected with the first device component, the second wafer is provided with a first surface and a second surface which are arranged in an opposite mode, and the first surface of the second wafer is provided with a second electrical connection end point electrically connected with the second device component;

bonding the second surface of the first wafer and the first surface of the second wafer to form a wafer stacking structure, wherein projections of the first electrical connection end point and the second electrical connection end point on the first surface of the second wafer are mutually staggered;

dicing the wafer stack structure to form a stepped wafer, wherein the wafer includes a first wafer portion and a second wafer portion, the first wafer portion has the first device component and the first electrical connection terminal electrically connected with the first device component, the second wafer portion has the second device component and the second electrical connection terminal electrically connected with the second device component, and projections of the second electrical connection terminal and the first wafer portion on a first surface of the second wafer portion are mutually staggered;

providing a third wafer having a third device component, the third wafer having a bonding surface with third electrical connection terminals thereon electrically connected to the third device component, bonding the die to the bonding surface of the third wafer, the die exposing some or all of the third electrical connection terminals;

forming a packaging layer on the bonding surface of the third wafer, wherein the packaging layer at least covers the chip and the third electrical connection terminal; and the number of the first and second groups,

and forming a rewiring structure on the packaging layer, wherein the rewiring structure is electrically connected with the first electrical connection end point, the second electrical connection end point and the third electrical connection end point respectively.

The present invention also provides a package structure, which comprises a third wafer, a step-shaped chip, a package layer and a redistribution structure,

the stepped wafer comprises a first wafer part with a first device component and a second wafer part with a second device component, the first wafer part is provided with a first surface and a second surface which are arranged oppositely, the first surface of the first wafer part is provided with a first electrical connection end point which is electrically connected with the first device component, the second wafer part is provided with a first surface and a second surface which are arranged oppositely, the first surface of the second wafer part is provided with a second electrical connection end point which is electrically connected with the second device component, the second surface of the first wafer part is bonded to the first surface of the second wafer part, and the projections of the second electrical connection end point and the first wafer part on the first surface of the second wafer part are mutually staggered;

the third wafer having a third device component and a bonding surface with third electrical connection terminals thereon electrically connected to the third device component, the second side of the second wafer portion of the wafer being bonded to the bonding surface, the wafer exposing part or all of the third electrical connection terminals;

the packaging layer is formed on the bonding surface of the third wafer and at least covers the chip and the third electrical connection terminal; and the number of the first and second groups,

the redistribution structure is formed on the encapsulation layer, and the redistribution structure is electrically connected to the first electrical connection terminal, the second electrical connection terminal, and the third electrical connection terminal, respectively.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

1. the packaging method of the invention comprises bonding a first wafer with a first electrical connection end point and a first device component and a second wafer with a second electrical connection end point and a second device component by wafer level packaging, cutting to form a stepped wafer, wherein the second electrical connection end point and the first electrical connection end point are distributed in a step shape, bonding the wafer to a third wafer with a third electrical connection end point and a third device component, and exposing the third electrical connection end point, so that the first electrical connection end point, the second electrical connection end point and the third electrical connection end point are distributed in a step shape in sequence, therefore, on one hand, the depth of contact holes on the first electrical connection end point, the second electrical connection end point and the third electrical connection end point are different and the lateral distance is increased, the mechanical property of the contact hole is further enhanced, collapse is avoided, and meanwhile the subsequent routing design of the rewiring structure can be optimized, so that the manufacturing process difficulty of the rewiring structure is reduced, and the electrical connection performance of the rewiring structure is improved; on the other hand, the three wafers are loaded with the device components, so that a three-dimensional packaging scheme for integrated packaging of various devices can be realized, and the integration level of products is improved; more importantly, the packaging method can provide a thought for manufacturing a complex device in parts and recombining the parts together through a packaging process to form a complete device, which is beneficial to reducing the process difficulty for manufacturing the complex device and further improving the device integration level.

2. The packaging structure of the invention bonds the chip in a ladder shape to a third wafer with a third device component and a third electrical connection end point connected with the third device component, the chip is provided with a first wafer part and a second wafer part, the first wafer part is provided with a first device component and a first electrical connection end point electrically connected with the first device component, the second wafer part is provided with a second device component and a third electrical connection end point electrically connected with the second device component, after the chip is bonded with the third wafer, the first electrical connection end point, the second electrical connection end point and the third electrical connection end point are in a ladder shape in sequence, so that a rewiring structure can be easily and respectively connected with the first electrical connection end point, the second electrical connection end point and the third electrical connection end point for electrical connection, therefore, the invention is beneficial to optimizing the wiring design of the rewiring structure and reducing the manufacturing process difficulty of the rewiring structure, and the electrical connection performance of the rewiring structure is improved; on the other hand, the first wafer part, the second wafer part and the third wafer are loaded with the device components, so that a three-dimensional packaging scheme for integrated packaging of various devices can be realized, and the integration level of products is improved; more importantly, the packaging structure can provide a thought for manufacturing a complex device in parts and recombining the parts together through a packaging process to form a complete device, which is beneficial to reducing the process difficulty for manufacturing the complex device and further improving the device integration level.

Drawings

FIG. 1 is a schematic cross-sectional view of a conventional device for wafer-level vacuum packaging of MEMS devices with two wafers;

FIG. 2 is a schematic cross-sectional view of a conventional device for wafer-level vacuum packaging of MEMS devices with three wafers;

FIG. 3 is a flow chart of a packaging method according to an embodiment of the present invention;

fig. 4A to 4H are schematic cross-sectional views of devices during packaging according to an embodiment of the invention.

Detailed Description

In order to make the objects and features of the present invention more comprehensible, embodiments of the present invention are further described below with reference to the accompanying drawings, wherein some technical features well known in the art are not described in order to avoid confusion with the present invention. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. It will be apparent to one skilled in the art that the present invention may be practiced without one or more of these details.

Referring to fig. 3, an embodiment of the invention provides a packaging method, including the following steps:

s1, providing a first wafer with a first device component and a second wafer with a second device component, wherein the first wafer is provided with a first surface and a second surface which are arranged in an opposite way, the first surface of the first wafer is provided with a first electrical connection end point which is electrically connected with the first device component, the second wafer is provided with a first surface and a second surface which are arranged in an opposite way, and the first surface of the second wafer is provided with a second electrical connection end point which is electrically connected with the second device component;

s2, bonding the second surface of the first wafer and the first surface of the second wafer to form a wafer stacking structure, wherein the projections of the first electrical connection end point and the second electrical connection end point on the first surface of the second wafer are mutually staggered;

s3, cutting the wafer stack structure to form a chip in a ladder shape, wherein the chip includes a first wafer portion and a second wafer portion, the first wafer portion has the first device component and the first electrical connection terminal electrically connected to the first device component, the second wafer portion has the second device component and the second electrical connection terminal electrically connected to the second device component, and part or all of the second electrical connection terminal is exposed by the first wafer portion;

s4, providing a third wafer having a third device component, the third wafer having a bonding surface with a third electrical connection terminal thereon, the third electrical connection terminal being electrically connected to the third device component, bonding the chip to the bonding surface of the third wafer, the chip exposing a portion or all of the third electrical connection terminal;

s5, forming a packaging layer on the bonding surface of the third wafer, the packaging layer at least covering the chip and the third electrical connection terminal; and the number of the first and second groups,

s6, forming a redistribution structure on the package layer, wherein the redistribution structure is electrically connected to the first electrical connection terminal, the second electrical connection terminal, and the third electrical connection terminal.

The following describes the packaging method of the present invention in detail with reference to fig. 3 and fig. 4A to 4H, taking the example of the second wafer 60 having a movable electronic element such as a MEMS element.

First, referring to fig. 4A, a first Wafer 40 is provided, where the first Wafer 40 may be a Device Wafer (Device Wafer) for completing Device fabrication, and the first Wafer 40 may be fabricated according to a corresponding layout design by using an integrated circuit fabrication technology such as a CMOS fabrication technology and/or a MEMS fabrication technology, for example, first Device components 401 are formed on a first substrate 400 through ion implantation, deposition, etching, and the like, and the number thereof may be determined according to the number of chips to be subsequently cut, and is not limited to one. The first substrate 400 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III/V compound semiconductors, and the semiconductor substrate may be a multilayer structure or the like formed by stacking single-layer structures made of these materials, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-stacked germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), germanium-on-insulator (GeOI), or the like. The first device assembly 401 may be formed on the first side 400a of the first substrate 400 by a suitable process known to those skilled in the art, and the first device assembly 401 may include at least one of active devices such as a memory, a logic circuit, a power device, a bipolar device, a single MOS transistor, a micro-electro-mechanical system (MEMS), and may even include at least one of optoelectronic devices such as a light emitting diode, and passive devices such as a resistor, a capacitor, and the like. That is, in various embodiments of the present invention, one first device assembly 401 may be a chip unit formed on the first surface 400a of the first substrate 400, and the chip unit may be a chip unit including only one component, a chip unit having a plurality of components with the same structure, or a chip unit having a plurality of components with different structures and different functions. The first device package 401 may be completely buried under the first surface 400a of the first substrate 400, or may have a part or all of the structure located above the first surface 400a of the first substrate 400. In addition, in this embodiment, the first surface 400a of the first substrate 400 refers to a surface of the first substrate 400 on which the first device assembly 401 is formed, the second surface 400b of the first substrate 400 refers to a second surface opposite to the first surface 400a, and the second surface 400b of the first substrate 400 refers to a second surface of the first wafer 40. The second surface of the first wafer 40 in this embodiment is explained above without specific reference. As a non-limiting example, the first device component 401 is a four-terminal MOS transistor, and includes a gate 401g formed on the first surface 400a of the first substrate 400, a source 401s and a drain 401d formed in the first substrate 400 on both sides of the gate 401g, and a substrate lead-out region (i.e., a body terminal of the MOS transistor) 401b formed in the first substrate 400 on one side of the drain 401 d.

Then, with continued reference to fig. 4A, first electrical connection terminals 403 are formed on the first side 400a of the first substrate 400. Specifically, a corresponding interlayer dielectric layer (not shown), a contact plug (not shown) located in the interlayer dielectric layer, a metal interconnection structure (not shown), and a first electrical connection terminal 403 located at a top layer may be formed on the first side 400a of the first substrate 400 through a series of contact plugs and metal interconnection line manufacturing processes such as dielectric material deposition, etching, and metal filling, and the first electrical connection terminal 403 is electrically connected to the first device component 401 through the corresponding metal interconnection structure and contact plug. Wherein the metal interconnection structure may comprise a plurality of metal interconnection layers (e.g. a layer 1 metal interconnection layer M)₁To nth metal interconnection layer M_n) And contact plugs electrically connecting adjacent metal interconnection layers (not shown), the adjacent metal interconnection layers being separated by corresponding interlayer dielectric layers, and the first electrical connection terminal 403 can be regarded as the topmost metal interconnection layer (the nth metal interconnection layer M) in the metal interconnection structure_n) The contact plug (not shown) can be regarded as the lowest metal interconnection layer (layer 1 metal interconnection layer M) in the metal interconnection structure₁) The contact plug between the device and the device below the contact plug,for simplicity, the first electrical connection terminal 403 and the contact plug (not shown) are only schematically shown in fig. 4A, but more structures may be included in practical applications. The interlevel dielectric layer used to space adjacent ones of the metal interconnect layers and contact plugs described above is typically composed of multiple layers of the same or non-identical dielectric layers, and in one example, the material of the interlevel dielectric layer may be any suitable dielectric material known to those skilled in the art, including but not limited to silicon dioxide (SiO)₂) Silicon nitride (SiN), silicon oxynitride (SiON), fluorocarbon (CF), silicon oxide doped with carbon (SiOC), or silicon carbonitride (SiCN), among others.

Next, with continued reference to fig. 4A, a passivation layer (not shown) is formed on the first surface 400a of the first substrate 400, the passivation layer buries the first electrical connection terminal 403 therein, and specifically, a passivation material may be deposited on the surface of the interlayer dielectric layer surrounding the first electrical connection terminal 403 by a chemical vapor deposition (cvd) process, etc. to bury the first electrical connection terminal 403 therein, and the passivation layer may be further planarized by a Chemical Mechanical Polishing (CMP) process, etc. to form the passivation layer. The interlevel dielectric layer and passivation protection layer are collectively labeled 402 throughout the various figures herein, as they function together to bury the first electrical connection terminal 403 therein. That is, in this embodiment, a surface of the passivation layer facing away from the first surface 400a of the first substrate 400 is a first surface of the first wafer 40.

Then, referring to fig. 4B, a Wafer-Level Packaging (WLP) process is used to bond the first side of the first Wafer 40 to a carrier 50, where the first Wafer 40 and the carrier 50 are physically connected together. Specifically, the first side of the first wafer 40 is bonded facing the carrier 50, i.e. the passivation layer is sandwiched between the first wafer 40 and the carrier 50. The carrier 50 may be any suitable carrier material known to those skilled in the art, such as a semiconductor, glass, ceramic, etc., and any suitable bonding method may be used when bonding the carrier 50 to the first side of the first wafer 40, such as temporary bonding or bonding, for example, using fusion bonding, especially a low temperature fusion bonding process, so as to avoid the failure of the first device assembly 401 caused by the bonding process with too high temperature, wherein the temperature of the low temperature fusion bonding process may be lower than 400 ℃, for example, the temperature of the low temperature fusion bonding process is between 100 ℃ and 250 ℃. For another example, the carrier 50 and the first surface of the first wafer 40 are bonded together through a bonding process, and the bonding layer (not shown) for bonding the carrier 50 and the passivation layer may be various organic films formed of an ultraviolet-curable organic material, such as a Die Attach Film (DAF), a dry film (dryfilm), or a photoresist. The thickness of the adhesive layer is set as required, and the number of the adhesive layers is not limited to one, and may be two or more.

Next, referring to fig. 4C, the first wafer 40 and the carrier 50 are turned upside down to make the second surface 400b of the first wafer 40 face upward, and a metal bonding layer 404 is formed by using a physical vapor deposition process such as vacuum sputtering and evaporation to cover the second surface 400b of the first wafer 40, wherein the metal bonding layer 404 is used for performing electrostatic bonding (i.e., physical connection) with the second wafer 60 (shown in fig. 4E). The material of the metal bonding layer 404 may be at least one of conductive metals such as Au, Pt, Cu, Ag, Al, and W.

Referring to fig. 4D and 4E, in the present embodiment, since the second device component of the second wafer 60 includes movable electronic components such as MEMS components, the second surface 400b of the first wafer 40 needs to be processed to provide a moving space for the movable electronic components. Specifically, referring to fig. 4D, the metal bonding layer 404 and a partial thickness of the first wafer 40 are etched from the second surface 400b of the first wafer 40 to form a raised bonding ring 400E and a groove 400c surrounded by the bonding ring 400E, where the groove 400c is used to cover the MEMS element after the first wafer 40 and the second wafer 600 (shown in fig. 4E) are bonded, so as to provide a vacuum cavity required for the MEMS element to move. In this embodiment, while the groove 400c is formed by etching, a groove 400d is formed outside the bonding ring 400e for directly removing the structure above the second electrical connection terminal 603 of the second wafer 60 by a subsequent cutting process to expose the second electrical connection terminal 603.

Finally, with continued reference to fig. 4D and 4E, the first wafer 40 is separated from the carrier 50, and the carrier 500 may be removed by selecting a suitable removal method according to the bonding method used. For example, the carrier 50 may be peeled off by denaturing the adhesive layer bonding the first wafer 40 and the carrier 50 to lose its adhesiveness by means of high temperature or ultraviolet irradiation. For another example, by means of laser melting, the film layer bonding the first wafer 40 and the carrier 50 by melting is melted again to peel off the carrier 50.

Referring to fig. 4E, in step S1, in an embodiment of the invention, a second substrate 60A having a portion 601 of a second device assembly other than the movable electronic element (e.g., a circuit structure including a CMOS element for supporting the operation of the movable electronic element) and a device substrate 60B having a movable electronic element (e.g., a MEMS element) 606 are bonded by wafer level packaging to obtain a desired second wafer 60, i.e., the second device assembly in the second wafer 60 includes the movable electronic element 606 and the portion 601 other than the movable electronic element.

Specifically, referring to fig. 4E, in step S1, the step of providing the second wafer 60 includes:

first, a second substrate 60A and a device substrate 60B are provided, wherein the second substrate 60A may be a device wafer substrate (generally referred to as a CMOS wafer) for completing the fabrication of devices such as CMOS and completing the fabrication of metal interconnection structures connected to CMOS elements, and may include a semiconductor substrate (not shown), devices such as CMOS (not shown) formed on the semiconductor substrate, a dielectric layer (not shown) covering the semiconductor substrate and the devices such as CMOS, a metal interconnection structure 602 located in the dielectric layer, and a second electrical connection terminal 603, and the metal interconnection structure 602 electrically connects the devices such as CMOS and the second electrical connection terminal 603. The semiconductor substrate may be any suitable substrate material known to those skilled in the art, and the devices such as CMOS may be formed on the semiconductor substrate by any suitable semiconductor process known to those skilled in the art, wherein the CMOS elements may be individual MOS transistors, multiple NMOS transistors or multiple PMOS transistors, or a combination of NMOS and PMOS transistors. The devices in the first substrate 60A may include at least one of active devices such as a memory, a logic circuit, a power device, and a bipolar device, in addition to the CMOS element, and may further include at least one of optoelectronic devices such as a light emitting diode, and passive devices such as a resistor and a capacitor. The metal interconnection structure 602 and the second electrical connection terminal 603 are used for externally leading out signals of the CMOS or the like devices in the second substrate 60A, for supporting the operation of the movable electronic element (i.e., MEMS element or the like) 606, providing functions such as analog-to-digital conversion, amplification, storage, filtering, and the like thereto. That is to say, in this embodiment, the second substrate 60A has a first side 600A and a second side 600b opposite to each other, the first side 600A of the second substrate 60A is provided with a second electrical connection terminal 603, the second substrate 60A is formed with a circuit structure (i.e., a portion 601 of the second device assembly excluding the movable electronic component) including a CMOS component for supporting the operation of the movable electronic component, and the second electrical connection terminal 603 is electrically connected to the portion 601. The first side 600A of the second substrate 60A is used for bonding with the device substrate 60B, and the second side 600B of the second substrate 60A is used for subsequent bonding with a third wafer.

The movable electronic components 606 in the device substrate 60B may include at least one of MEMS components such as motion sensors, pressure sensors, accelerometers, gyroscopes, and microphones. In the embodiment, in the device substrate 60B, a closed ring-shaped substrate ring 605 corresponding to the bonding ring 400e on the first wafer 40 is further formed around the movable electronic element 606, the substrate ring 605 is used for separating a cavity formed subsequently from the external environment, and a through-silicon via structure 607 penetrating through the substrate ring 605 and electrically connected to the metal interconnection structure 602 is further formed in the substrate ring 605. Further, the substrate ring 605 and the through silicon via structure 607 are further formed with a conductive bump 608 for aligning with the metal bonding layer 404 on the bonding ring 400e of the first wafer 40 and forming electrostatic bonding when subsequently bonding the first wafer 40 and the second wafer 60, so that a cavity is formed between the groove 400c surrounded by the bonding ring 400e and the space surrounded by the substrate ring 605. The cavity is used to house the movable electronic component 606 and provide the space required for the movement of the movable electronic component 606.

Then, a second surface (not shown) of the device substrate 60B and the first surface 600A of the second substrate 60A are bonded by wafer-level packaging, and the surface of the device substrate 60B exposing the second electrical connection terminals 603 (i.e., the surface of the second electrical connection terminals 603 facing away from the second surface 600B of the second substrate 60A). When bonding the second surface of the device substrate 60B to the first surface of the second substrate 60A, any suitable bonding method may be used, such as temporary bonding or adhesion. For example, the second surface of the device substrate 60B and the first surface of the second substrate 60A are bonded together by an adhesive layer 604, and the adhesive layer 604 may be formed of various organic films such as a Die Attach Film (DAF), a dry film (dry film), a photoresist, and the like, for an ultraviolet-curable organic material and the like. The thickness of the adhesive layer 604 is set as desired, and the number of adhesive layers is not limited to one, and may be two or more.

In the above embodiment, the method for providing the second wafer 60 is to directly bond a second substrate 60A and a device substrate 60B by using a wafer level packaging process, but the technical solution of the present invention is not limited thereto, and the method for providing the second wafer 60 may also be to fabricate structures such as the movable electronic element 606 and the second electrical connection terminal 603 on the second substrate 60A by using a semiconductor device manufacturing process to form the desired second wafer 60. Specifically, referring to fig. 4E, in step S1, the step of providing the second wafer 60 includes:

first, a second substrate 60A having a portion 601 of a second device component except for a movable electronic element is provided, and a dielectric layer (not shown) and a metal interconnection structure 602 and a second electrical connection terminal 603 located in the dielectric layer are formed on a first surface 600A of the second substrate 60A, wherein the metal interconnection structure electrically connects the portion 601 and the second electrical connection terminal 603;

then, a movable electronic element 606 (e.g., a MEMS element, etc.) corresponding to the second electrical connection terminal 603 is formed on the dielectric layer and the metal interconnection structure 602 by deposition, etching, etc., wherein the movable electronic element 606 is electrically connected to the metal interconnection structure 602, and the surface of the second electrical connection terminal 603 is exposed by the movable electronic element 606. In various embodiments, movable electronic component 606 may include at least one of a MEMS component such as a motion sensor, pressure sensor, accelerometer, gyroscope, and microphone. Preferably, at the same time as the movable electronic element 606 is formed, a closed ring-shaped substrate ring 605 corresponding to the bonding ring 400e on the first wafer 40 is also formed around the movable electronic element 606 to isolate the subsequently formed cavity from the external environment; further forming a through-silicon via structure 607 penetrating the substrate ring 605 and electrically connected to the metal interconnection structure 602 by a through-silicon via or the like; and then forming a conductive bump 608 on the substrate ring 605 and the through-silicon-via structure 607, for aligning with the metal bonding layer 404 on the bonding ring 400e of the first wafer 40 and forming electrostatic bonding when bonding the first wafer 40 and the second wafer 60, so that a cavity is formed in the space surrounded by the substrate ring 605 and the groove 400c surrounded by the bonding ring 400 e. That is, the first side of the second wafer 60 includes the exposed first side 600A of the second substrate 60A, the movable electronic component 606, the conductive bump 608, and the surface of the adhesive layer 604

In the above embodiment, the portion 601 and the second electrical connection terminal 603 are first fabricated in the second substrate 60A, and then the movable electronic element 606 is fabricated, but the technical solution of the present invention is not limited thereto, and the portion 601 may be fabricated in the second substrate 60A, then the movable electronic element 606 is fabricated on the portion 601, and then the second electrical connection terminal 603 is fabricated.

In addition, in various embodiments, the relative positions of the movable electronic element 606 and the second electrical connection terminal 603 may be reasonably set according to the device type and size, for example, the movable electronic element 606 may be partially overlapped with the projection of the second electrical connection terminal 603 on the first surface 600A of the second substrate 60A, and preferably, the second electrical connection terminal 603 is disposed on a region other than the projection of the movable electronic element 606 on the first surface 600A of the second substrate 60A, so that the second electrical connection terminal 603 and the movable electronic element 606 are completely staggered, so as to improve the effect of the subsequent rewiring structure manufacturing process.

It should be noted that when the second device component in the second wafer 60 does not include the movable electronic component 606, the process of etching the second surface 400b of the first wafer 40 to form the recess 400c in step S1 may be omitted, thereby preventing the formation of the cavity structure after the first wafer 40 and the second wafer 60 are bonded.

With continued reference to fig. 4E, in step S2, the first wafer 40 having the first electrical connection terminals 403 and the first device components 401 and the second wafer having the second device components (including the movable electronic elements 606) and the second electrical connection terminals 603 are aligned and bonded together to form a wafer stack structure (not shown), and the projections of the first electrical connection terminals 403 on the first side of the second wafer 60 (i.e., the first side 600A of the second substrate 60A facing the second side 400b of the first wafer 40) are staggered with respect to the second electrical connection terminals 603. In this embodiment, the first wafer 40 and the second wafer 60 are temporarily bonded together to form a physical connection by electrostatic force between the metal bonding layer 404 on the second side 400b of the first wafer 40 and the conductive bump 608 on the second wafer 60, and the projections of the first electrical connection terminal 403 and the second electrical connection terminal 603 on the first side 600a of the second substrate 600 are mutually staggered. It should be noted that, in various embodiments of the present invention, the relative positions of the first electrical connection terminal 400 and the second electrical connection terminal 603 may be reasonably set according to the device type and size, for example, the projections of the first electrical connection terminal 400 and the second electrical connection terminal 603 on the first surface 600a of the second substrate 600 may overlap, or may be completely staggered. Preferably, the two are completely staggered and the distance is increased, so as to improve the execution effect of the subsequent plugging process, that is, when the projection distance of the second electrical connection terminal 603 and the first electrical connection terminal 400 on the first surface 600a of the second substrate 600 is short or partially overlapped, the problems of collapse or punch-through of the contact holes formed on the first electrical connection terminal 403 and the second electrical connection terminal 603, and the like, can be prevented, and further, the problem of short circuit between the conductive contact plugs in the subsequently formed rewiring structure can be avoided.

Referring to fig. 4E and 4F, in step S3, a first dicing is performed on the wafer stack structure from top to bottom (i.e., along a direction from the first surface of the first wafer 40 to the first surface of the second wafer 60) at the inner side of the second electrical connection point 603, and then a second dicing is performed at the outer side of the second electrical connection point 603 and the side of the second device element away from the second electrical connection point 603, wherein the dicing lane D1 of the first dicing has a shallower depth, which only cuts through the second surface 400b of the first wafer 40a, which is equivalent to dicing the first wafer 40; the depth of the scribe line D2 of the second cutting is larger, and the first surface of the first wafer 40 is cut to the second surface 600b of the second wafer 60, which is equivalent to simultaneously dicing the still connected portion of the first wafer 40 and the second wafer 60, so that the portion of the first wafer 40 on the side of the movable electronic component 606 above the second electrical connection terminal 603 (i.e. the portion above the second electrical connection terminal 603 between the scribe lines D1 and D2) can be directly removed by two cutting processes to expose the surface of the second electrical connection terminal 603, and form the chip 70 in a step shape. The stepped die 70 includes a first wafer portion 40 ' having first electrical connection terminals 403 and a first device component 401, and a second wafer portion 60 ' having second electrical connection terminals 603 and a second device component (including the portion 601 and a movable electronic component 606, etc.), with one side edges of the first wafer portion 40 ' and the second wafer portion 60 ' forming a step and the other side being flush, the second wafer portion 60 ' including the remaining second substrate portion 60A ' and the device substrate 60B '. It should be appreciated that the term "exposed surface of the second electrical connection terminal 603" as used herein does not necessarily mean directly exposing the surface of the conductive layer of the second electrical connection terminal 603, but rather, exposes the surface of the covering layer directly above the second electrical connection terminal 603, so long as the contact hole can reach deep into the surface of the conductive layer of the second electrical connection terminal 603 when the contact hole on the second electrical connection terminal 603 is formed later. Similarly, the meaning of exposing the first electrical connection terminal and the subsequent third electrical connection terminal should also be understood as: it should be noted that, in this embodiment, the second electrical connection terminal 603 is completely exposed by the first wafer portion 40 ', but the technical solution of the present invention is not limited thereto, and in other embodiments of the present invention, the first wafer portion 40' may also shield a part of the surface of the second electrical connection terminal 603.

In addition, only a region where one chip 70 having a stepped shape is fabricated is shown in fig. 4A to 4F, and it should be appreciated by those skilled in the art that, in step S1, the first wafer and the second wafer are provided to be large enough, and the stacked wafer stack structure has a plurality of regions for fabricating the chip 70 having a stepped shape, i.e., a first device component and a second device component are provided in each region, so that a plurality of the chips 70 having a stepped shape may be cut in step S3. The main purpose of steps S1-S3 is to fabricate wafer 70 in a stepped shape for subsequent packaging with devices to be integrated.

Furthermore, in order to more intuitively understand the core of the technical solution of the present invention, in fig. 4F to 4H, only the marks of the core components that can embody the encapsulation method of the present invention are retained.

Referring to fig. 4G, in step S4, a third wafer 80 having a plurality of third electrical connection terminals 802 and a plurality of third device components 801 is first provided, the third wafer 80 may be any suitable wafer material known to those skilled in the art, the third wafer 80 has first faces 800a and 800b opposite to each other, the third device components 801 are formed on the third wafer 80 through a semiconductor device manufacturing process or a packaging process (the third device components 801 may be partially embedded in the third wafer 80 or completely embedded in the third wafer 80), and the third electrical connection terminals 802 are located at the periphery of the third device components 801. The third device assembly 801 may include at least one of active devices such as memory, logic, power device, bipolar device, MOS transistor alone, MEMS, etc., and may even include at least one of optoelectronic devices such as light emitting diodes, etc., and passive devices such as resistors, capacitors, inductors, etc. That is, in various embodiments of the present invention, one third device assembly 801 may be a chip formed inside the first surface 800a of the third wafer 80, and the chip may include only one component, may include a plurality of components having the same structure, or may include a plurality of components having different structures and different functions. A metal interconnect structure (not shown) may also be formed in the third wafer 80, and the third electrical connection terminal 802 may be the topmost metal interconnect layer of the metal interconnect structure. The surface of the third electrical connection terminal 802 may be exposed by the first surface 800a of the third wafer 80, or may be buried within the first surface 800a of the third wafer 80.

Referring to fig. 4G, in step S4, one or more stepped chips 70 and other devices (not shown) to be integrated, which are different from the chips 70, may be temporarily bonded to corresponding positions of the first surface 800a of the third Wafer 80 by using a Wafer level Package in Package (WLPSIP) method through an adhesive layer or an electrostatic bonding method. The wafer level system packaging refers to a technology of integrating a plurality of active elements (including MEMS elements), passive elements, optical elements, and other elements with different functions onto one wafer, and then performing dicing to obtain individual packages. The wafer level system package has the advantages of greatly reducing the area of a package structure, reducing the manufacturing cost, optimizing the electrical performance, manufacturing in batches and the like, and can obviously reduce the workload and the requirements of equipment. In this step, after the wafer 70 is bonded to the third wafer 80, the projections of the third electrical connection terminal 802 and the second electrical connection terminal 603 on the first surface 800a of the third wafer 80 are mutually staggered, so as to provide sufficient operating space for the subsequent redistribution structure fabrication process (especially, contact plug fabrication process). It should be noted that, in various embodiments of the present invention, the relative positions of the third electrical connection terminal 802 and the second electrical connection terminal 603 may be properly set according to the device type and size, for example, the projections of the third electrical connection terminal 802 and the second electrical connection terminal 603 on the first face 800a of the third wafer 80 may be partially overlapped or completely staggered, when the two structures are completely staggered, the transverse horizontal spacing between the two structures can be further enlarged so as to improve the execution effect of the subsequent rewiring structure manufacturing process, i.e. it is thereby prevented that said second electrical connection end point 603 and third electrical connection end point 802 are close to each other or partially overlap, the contact holes formed on the third electrical connection terminal 802 and the second electrical connection terminal 603 are collapsed or penetrated, thereby avoiding the short circuit between the subsequently formed conductive contact plugs.

Referring to fig. 4H, in step S5, an encapsulation layer 90 may be covered on the first surface 800a of the third wafer 80 by an injection molding process, and the encapsulation layer 90 buries the stepped wafer 70 therein and provides a flat upper surface to provide a process surface required by a subsequent redistribution structure manufacturing process (including a contact plug process). As an example, the encapsulation layer 90 includes thermosetting resin, which can soften or flow during molding, has plasticity, can be formed into a certain shape, and simultaneously undergoes chemical reaction to be cross-linked and cured, and the encapsulation layer 90 may include at least one of thermosetting resin such as phenol resin, urea resin, melamine-formaldehyde resin, epoxy resin, unsaturated resin, polyurethane, polyimide, and the like. Among them, it is preferable to use an epoxy resin as the encapsulating layer 90, wherein the epoxy resin may be an epoxy resin with or without a filler, and further includes various additives (for example, a curing agent, a modifier, a release agent, a heat coloring agent, a flame retardant, etc.), for example, a phenol resin as the curing agent, and solid particles (for example, fine silica powder) as the filler. In other embodiments of the present invention, the encapsulation layer 90 may also be formed by a coating process or a chemical vapor deposition process, etc.

With continued reference to fig. 4H, in step S6, a redistribution structure is formed on the package layer 90 (including embedded in the package layer 90), which includes the following steps:

first, the encapsulation layer 90 may be etched through photoresist coating, exposing, developing and etching processes to form contact holes (not shown) exposing the first, second and third

electrical connection terminals

403, 603 and 802, respectively.

Then, conductive contact plugs are filled in the contact holes by metal barrier deposition, electroplating, chemical mechanical polishing, and the like, wherein the formed first conductive contact plug 91a is electrically connected to the first electrical connection terminal 403, the formed second conductive contact plug 91b is electrically connected to the second electrical connection terminal 603, and the formed third conductive contact plug 91c is electrically connected to the third electrical connection terminal 802. The process of forming each conductive contact plug is well known to those skilled in the art and will not be described herein.

Then, an inter-metal inter-layer dielectric layer 92 and a redistribution metal layer 91d are formed on the package layer 90, the first conductive contact plug 91a, the second conductive contact plug 91b and the third conductive contact plug 91c through processes of inter-metal inter-layer dielectric layer deposition, etching, metal filling and the like, and the redistribution metal layer 91d, the first conductive contact plug 91a, the second conductive contact plug 91b and the third conductive contact plug 91c form the redistribution structure of the present embodiment. The inter-metal interlayer dielectric layer 92 and the redistribution metal layer 91d may have a single-layer structure or a multi-layer stacked structure. The rewiring structure connects the die 70 packaged on the third wafer 80 and other devices to be integrated and the third device components inside the third wafer 80 in place. The process of fabricating the redistribution structure is well known to those skilled in the art and will not be described herein.

It should be appreciated from fig. 4G and 4H that, since it is necessary to form conductive contact plugs on the first electrical connection terminal 403, the second electrical connection terminal 603 and the third electrical connection terminal 802, a certain misalignment between the first electrical connection terminal 403 and the second electrical connection terminal 603 must be ensured when bonding the first wafer 40 and the second wafer 60, and a certain misalignment between the second electrical connection terminal 603 and the third electrical connection terminal 802 must be ensured when bonding the stepped chip 70 to the third wafer 80, so as to provide a space for each conductive contact plug formed in the encapsulation layer 90.

In the above embodiments, the chip in the step shape has only one step, but it should be appreciated that the embodiments only provide a concept, and those skilled in the art can further expand the concept based on the concept, which also falls into the scope covered by the technical solution of the present invention, for example, when it is necessary to further improve the integration of the product, the structure after step S6 can be regarded as a new first wafer or a new second wafer, and the above steps S1 to S6 are repeated again, so that the step shape with more steps can be manufactured by repeating the above steps cyclically.

In the above embodiments, only the first surface 800a of the third wafer 80 is processed in steps S4 to S6, and when the device integration needs to be further improved, the second surface 800b of the third wafer 80 may be utilized, for example, according to steps S4 to S6, a step of sequentially bonding a plurality of devices to be integrated including the step-shaped wafer 70 of the present invention on the second surface 800a of the third wafer 80, and a step of forming an encapsulation layer and a redistribution structure.

It should be noted that, the package can be generally divided into a fan-in type (FI) and a fan-out type (FO), if the size after the package is basically the size of the final product, the product has enough area to put all I/O interfaces in, the re-wiring structure can be manufactured by adopting a fan-in type package method, solder ball placement is further performed, the arrangement of the re-wiring structure and the distribution of the solder balls are all inside the size of the product, and finally, cutting is performed (once all), and the shipment is completed. If the number of the I/O ports of the finally manufactured product is too large, or the required I/O ports cannot be completely arranged in the size of the existing product due to the requirement of the ball pitch and the like, a fan-out packaging mode can be adopted to wrap a circle of special packaging material around the product (basically, the periphery is wrapped by the second surface with five sides) to form the packaging layer 90, the packaging layer 90 can not only protect internal devices, but also enlarge the size of the product by a circle, and route and arrange the I/O ports in the whole packaging range, so as to complete the arrangement of the re-wiring structure and the distribution of the solder balls.

Furthermore, it should be appreciated that in the packaging method of the foregoing embodiments, the first device assembly 401, the second device assembly, and the third device assembly 801 may respectively include a portion corresponding to an independent device, and after the redistribution structure is formed, the first device assembly 401, the second device assembly, and the third device assembly 801 may be electrically connected to form the independent device through the redistribution structure, the first electrical connection terminal 403, the second electrical connection terminal 603, and the third electrical connection terminal 802, for example, the second device assembly includes a MEMS component and a portion of a circuit structure supporting the operation of the MEMS component; the first device assembly 401 and the third device assembly 801 comprise a further two-part circuit structure supporting the operation of the MEMS component, whereby the first device assembly 401, the second device assembly and the third device assembly 801 may be electrically connected by the rewiring structure, the first electrical connection terminal 403, the second electrical connection terminal 603 and the third electrical connection terminal 802 to form a fully functional MEMS element. Of course, when all the parts of the respective independent devices are included in the first device assembly 401, the second device assembly, and the third device assembly 801, the first device assembly 401, the second device assembly, and the third device assembly 801 may be electrically connected through the redistribution structure, the first electrical connection terminal 403, the second electrical connection terminal 603, and the third electrical connection terminal 802, so that a product integrated with multiple functions may be formed.

Referring to fig. 4E to fig. 4H, an embodiment of the invention further provides a package structure manufactured by the packaging method of the invention, which includes a third wafer 80, a stepped chip 70 bonded to the third wafer 80, a package layer 90, and a redistribution structure. Of course, the number of the chips 70 bonded on the third wafer 80 is not limited to one, and the devices bonded on the third wafer 80 are not limited to the chips 70, but may also have other forms and functions of devices to be integrated, and these devices to be integrated may be temporarily bonded to corresponding positions on the bonding surface of the third wafer 80 by means of adhesive layer adhesion or electrostatic bonding, or the like. That is, all devices bonded on the third wafer 80 may have the same structure and function, such as the same stepped chip 70; it is also possible that the structures are identical but not identical in function, e.g. wafers that are all stepped, but that these stepped wafers differ in function, e.g. in the function of the movable electronic component 606 in each wafer.

The stepped chip 70 includes a first wafer portion 40 'and a second wafer portion 60' bonded together by bonding means such as adhesive bonding or fusion bonding. The first wafer portion 40 'has a first device component 401 and a first side 400a and a second side 400b opposite to each other, the first device component 401 may be completely buried in a region between the first side 400a and the second side 400b, and may have a portion located on the first side 400, and the first side 400a of the first wafer portion 40' has a first electrical connection terminal 403 thereon, which is electrically connected to the first device component 401. The second wafer portion 60 ' has a second device component and first and second oppositely disposed faces (not shown) and 600b, and the second device component may be completely buried in a region between the first and second faces 600b of the second wafer portion 60 ', and may be partially located on the first face of the second wafer portion 60 '. In this embodiment, one side of the first wafer portion 40 'is aligned with the second wafer portion 60', and the other side of the first wafer portion 40 'is pushed inward relative to the second wafer portion 60' to form a step, wherein the step exposes a part or all of the surface of the second electrical connection terminal 603, i.e. projections of the second electrical connection terminal 603 and the first wafer portion 40 'on the first surface of the second wafer portion 60' are mutually staggered.

The stepped chip 70 may be formed by stacking two or three wafers and then cutting the stacked wafers twice. The first wafer 40 for forming the first wafer portion 40' may be a device wafer for completing fabrication of CMOS elements and/or MEMS elements, and the first wafer 40 includes a first substrate 400 and at least one first device assembly 401 formed on the first substrate 400, and the specific structures of the first substrate 400 and the first device assembly 401 may refer to the description in step S1, which is not described herein again. The first wafer portion 40' may further include a passivation protection layer for making and protecting the first electrical connection terminals 403. The second surface 400b of the first wafer portion 40 'further has an annular bonding ring 400e and a groove 400c surrounded by the bonding ring 4004 for providing a containing space and a moving space for the movable electronic component 606 on the second wafer portion 60', so as to provide a free moving cavity for the movable electronic component 606. The bonding ring 400e is also covered with a metal bonding layer 404. In other embodiments of the present invention, the recess 400c structure on the second side 400b of the first wafer portion 40 'may be omitted when the movable electronic component 606 is not included in the second device assembly on the second wafer portion 60'.

The second wafer 60 used to form the second wafer portion 60 ' may be formed by bonding together two wafers, one wafer being a second substrate 60A for making the second substrate portion 60A ' in the second wafer portion 60 ', and the other wafer being a device substrate 60B for making the device wafer portion 60B ' in the second wafer portion 60 '. By way of example, the second substrate 60A is a device wafer for completing the fabrication of devices such as CMOS devices and/or MEMS devices, which may include a semiconductor substrate (not shown), a device portion (not shown) such as a CMOS device formed on the semiconductor substrate, a dielectric layer (not shown) covering the semiconductor substrate and the device such as the CMOS device, a metal interconnection structure 602 located in the dielectric layer, and the second electrical connection terminal 603, the metal interconnect structure 602 is electrically connected to the CMOS devices and the second electrical connection terminal 603, and accordingly, the second substrate portion 60A' of the wafer 70 includes a portion of the semiconductor substrate and a device portion, such as a CMOS device, formed on the semiconductor substrate, a dielectric layer portion, the metal interconnect structure 602, and the second electrical connection terminal 603. The specific structure of the second substrate portion 60A' can refer to the description of the second substrate 60A in step S1, and is not repeated here. The metal interconnect structure 602 and the second electrical connection terminal 603 serve to bring out said CMOS or the like devices in the second substrate portion 60A 'for supporting the operation of the movable electronic components 606 (i.e. MEMS components or the like) in said second wafer portion 60', providing functions such as analog-to-digital conversion, amplification, storage, filtering, etc. thereto. In the second wafer portion 60 ', a closed ring-shaped substrate ring 605 corresponding to the bonding ring 400e on the first wafer portion 40' is further formed around the movable electronic component 606, the substrate ring 605 is used for separating a cavity formed subsequently from the external environment, and a through-silicon via structure 607 penetrating through the substrate ring 605 and electrically connected to the metal interconnection structure 602 is further formed in the substrate ring 605; conductive bumps 608 are further formed on the substrate ring 605 and the through-silicon-via structure 607, and the metal bonding layer 404 on the bonding ring 400e of the first wafer portion 40' is aligned with the conductive bumps 608 and is electrostatically bonded together, so that a cavity is formed in the space surrounded by the groove 400c surrounded by the bonding ring 400e and the substrate ring 606. The device substrate portion 60B 'and the second substrate portion 60A' may be bonded together by temporary bonding or adhesive bonding, etc.

In other embodiments of the present invention, the second wafer portion 60 ' may also be a structure formed by fabricating a second device component and a second electrical connection terminal 603 on a second substrate portion 60A ' through a semiconductor device fabrication process, in which case the second wafer portion 60 ' includes: a second substrate portion 60A 'having a portion 601 of the second device component excluding the movable electronic element, a dielectric layer (not shown) formed on the first side 600A of the second substrate portion 60A', and the movable electronic element 606 formed on the dielectric layer (not shown), wherein a metal interconnection structure 602 and the second electrical connection terminal 603 are formed in the dielectric layer, the metal interconnection structure 602 is electrically connected to the portion 601, and the movable electronic element 606 is electrically connected to the metal interconnection structure 602 and exposes a portion or all of the surface of the second electrical connection terminal 603.

In various embodiments, the relative positions of the movable electronic element 606 and the second electrical connection terminal 603 and the relative positions of the first electrical connection terminal 403 and the second electrical connection terminal 603 may be appropriately set according to the device type and size, so that the projections of the movable electronic element 606 and the second electrical connection terminal 603 on the first face 600A of the second substrate portion 60A' may be partially overlapped or completely staggered; the projections of the first electrical connection terminal 403 and the second electrical connection terminal 603 on the first side 600A of the second substrate portion 60A' may be partially overlapped or completely staggered.

The third wafer 80 may be any suitable wafer material known to those skilled in the art, the third wafer 80 may have a third device element 801 electrically connected to a third electrical connection terminal 802 formed therein, the third wafer 80 further has first faces 800a and 800b disposed opposite to each other, and the third device element 801 may be completely buried in a region between the first faces 800a and 800b or may have a portion of its surface exposed by the first face 800 a. The third device assembly 801 may be formed on the third wafer 80 (including being embedded or completely buried in the third wafer 80) through a semiconductor device fabrication process or a packaging process, and the third electrical connection terminal 802 is located at the periphery of the third device assembly 801. The third device component 801 may have a specific structure as described above with reference to step S4, and the third electrical connection terminal 802 may be the topmost metal interconnect layer of the metal interconnect structure. The upper surface of the third electrical connection terminal 802 may be exposed by the first surface 800a of the third wafer 80, or may be buried within the first surface 800a of the third wafer 80. And the projections of the third electrical connection terminal 802 and the second electrical connection terminal 603 on the first face 800a of the third wafer 80 are mutually staggered.

The encapsulation layer 90 is formed on the first side 800a of the third wafer 80 and buries the die 70 and the third electrical connection terminals 802 therein; the encapsulation layer 90 includes a thermosetting resin, for example, at least one of a phenol resin, a urea resin, a melamine-formaldehyde resin, an epoxy resin, an unsaturated resin, a polyurethane, a polyimide, and the like. Preferably, the encapsulation layer 90 has a flat upper surface to provide a required process surface for the fabrication process of the rewiring structure (including the contact plug process). The redistribution structure is formed on the package layer 90, and includes conductive contact plugs embedded in the package layer 90, a redistribution metal layer formed on the surface of the package layer 90, and the redistribution structure is electrically connected to the first electrical connection terminals 403, the second electrical connection terminals 603, and the third electrical connection terminals 802, respectively. In this embodiment, the redistribution structure includes first to third conductive contact plugs 91a to 91c embedded in the encapsulation layer 90 and a redistribution metal layer 91d (which may be multi-layered or single-layered) formed above the encapsulation layer 90, and when there are multiple redistribution metal layers 91d, an inter-metal dielectric layer 92 is located between adjacent redistribution metal layers 91 d. The first conductive contact plug 91a is electrically connected to the first electrical connection terminal 403, the second conductive contact plug 91b is electrically connected to the second electrical connection terminal, the third conductive contact plug 91c is electrically connected to the third electrical connection terminal 802, and the redistribution metal layer 91d is electrically connected to the first to third conductive contact plugs 91a to 91 c.

It should be appreciated that in the above embodiments, the stepped chip 70 has only one step, but it should be appreciated that the embodiments only provide a concept, and those skilled in the art can further expand the concept based on the concept, which also falls within the scope covered by the technical solution of the present invention, for example, when it is necessary to further improve the integration of the product, the chip 70 having multiple steps can be manufactured by the packaging method of the present invention to be bonded to the third wafer 80 to form the packaging structure of the present invention. Of course, the chip 70 may be bonded not only to the first side of the third wafer 80, but also to the second side of the third wafer 80 in a partial number when it is required to further improve the integration of the product.

Furthermore, it should be appreciated that in the package structures of the above embodiments, the first device assembly 401, the second device assembly, and the third device assembly 801 may respectively include a portion of a separate device, and after the redistribution structure is formed, the first device assembly 401, the second device assembly, and the third device assembly 801 may be electrically connected to form the separate device through the redistribution structure, the first electrical connection terminal 403, the second electrical connection terminal 603, and the third electrical connection terminal 802, for example, the second device assembly includes a MEMS component and a portion of a circuit structure supporting the operation of the MEMS component; the first device assembly 401 and the third device assembly 801 comprise a further two-part circuit structure supporting the operation of the MEMS component, whereby the first device assembly 401, the second device assembly and the third device assembly 801 may be electrically connected by the rewiring structure, the first electrical connection terminal 403, the second electrical connection terminal 603 and the third electrical connection terminal 802 to form a fully functional MEMS element. Of course, when all the parts of the respective independent devices are included in the first device assembly 401, the second device assembly, and the third device assembly 801, the first device assembly 401, the second device assembly, and the third device assembly 801 may be electrically connected through the redistribution structure, the first electrical connection terminal 403, the second electrical connection terminal 603, and the third electrical connection terminal 802, so that a product integrated with multiple functions may be formed.

In summary, the package structure and the manufacturing method thereof of the present invention can implement a three-dimensional package scheme for integrated package of multiple devices, which is beneficial to optimizing the routing design of the rewiring structure, reducing the manufacturing process difficulty of the rewiring structure, and improving the electrical connection performance of the rewiring structure, can provide an idea of manufacturing a complex device in parts and recombining the parts together through a package process to form a complete device, and is beneficial to reducing the process difficulty of manufacturing the complex device and further improving the device integration level.

It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A method of packaging, comprising:

2. The packaging method of claim 1, wherein the first device assembly, the second device assembly, and the third device assembly each comprise a portion of a separate device, the first device assembly, the second device assembly, and the third device assembly being electrically connected by the rewiring structure, the first electrical connection terminal, the second electrical connection terminal, and the third electrical connection terminal to form the separate device; alternatively, all of the first device assembly, the second device assembly, and the third device assembly include respective individual devices.

3. The packaging method of claim 1, wherein the second device component comprises a movable electronic element.

4. The packaging method of claim 3, wherein the step of providing the first wafer comprises:

providing a first substrate with the first device assembly formed thereon, wherein the first substrate is provided with a first surface and a second surface which are oppositely arranged;

forming the first electrical connection terminals on the first side of the first substrate in electrical connection with the first device component;

forming a passivation protection layer covering the first side of the first substrate and burying the first electrical connection terminals therein;

bonding the first substrate to a carrier with the passivation protection layer sandwiched between the first substrate and the carrier;

forming a metal bonding layer to cover the second surface of the first substrate;

etching the metal bonding layer and the first substrate with partial thickness from the second surface of the first substrate to form a raised bonding ring and a groove surrounded by the bonding ring, wherein the groove is used for forming a cavity after the first wafer and the second wafer are bonded, and the cavity is used for accommodating the movable electronic element and providing a moving space for the movable electronic element; and the number of the first and second groups,

and removing the carrier to form the first wafer.

5. The packaging method according to claim 4, wherein the first side of the second wafer further has conductive bumps corresponding to the bonding rings, and the movable electronic components of the second device assembly are located inside the conductive bumps; when bonding the first wafer and the second wafer, the conductive bump and the bonding ring are aligned and bonded to form the cavity.

6. The packaging method of any of claims 1 to 5, wherein the step of providing the second wafer comprises:

providing a second substrate, wherein the second substrate is provided with a first surface and a second surface which are arranged oppositely, preparing the second device assembly in the second substrate, and forming a second electrical connection end point which is electrically connected with the second device assembly on the first surface of the second substrate; alternatively, the first and second electrodes may be,

providing a second substrate, wherein the second substrate is provided with a first surface and a second surface which are arranged in an opposite way, forming a second electrical connection terminal on the first surface of the second substrate, and preparing a second device component exposing the second electrical connection terminal on the first surface of the second substrate.

7. The packaging method of any of claims 1 to 5, wherein the step of providing the second wafer comprises:

providing a device sheet body with the second device assembly and a second substrate with a second electrical connection terminal corresponding to the second device assembly on one surface; and the number of the first and second groups,

and bonding the device sheet body to the surface of the second substrate where the second electrical connection terminal is located, wherein the device sheet body exposes the second electrical connection terminal to form the second wafer.

8. The packaging method according to any one of claims 1 to 5, wherein the step of dicing the wafer stack structure comprises: and cutting the second wafer from the second surface of the first wafer at the inner side of the second electrical connection end point and the outer side of the second electrical connection end point respectively, stopping cutting at the first surface of the second wafer from the inner side of the second electrical connection end point, stopping cutting at the second surface of the second wafer from the outer side of the second electrical connection end point so as to remove redundant parts of the first wafer and the second wafer and expose the first surface of the second electrical connection end point, thereby forming the stepped wafer.

9. The packaging method according to claim 1, wherein the die is temporarily bonded to the third wafer by adhesive bonding or electrostatic bonding.

10. The packaging method of claim 1, wherein forming the rewiring structure comprises:

etching the packaging layer to form contact holes respectively exposing the first electrical connection end point, the second electrical connection end point and the third electrical connection end point;

filling conductive contact plugs in the contact holes, wherein the conductive contact plugs are electrically connected with the first electrical connection end points, the second electrical connection end points and the third electrical connection end points;

forming an intermetallic interlayer dielectric layer on the packaging layer and the conductive contact plug; and the number of the first and second groups,

and forming a rewiring metal layer in the intermetallic interlayer dielectric layer, wherein the rewiring metal layer is electrically connected with the conductive contact plug.

11. A package structure includes a third wafer, a chip with a step shape, a package layer and a redistribution structure,

12. The package structure of claim 11, wherein the first device component, the second device component, and the third device component each comprise a portion of a separate device, the first device component, the second device component, and the third device component being electrically connected by the rewiring structure, the first electrical connection terminal, the second electrical connection terminal, and the third electrical connection terminal to form the separate device; alternatively, all of the first device assembly, the second device assembly, and the third device assembly include respective individual devices.

13. The package structure of claim 11, wherein the second device component comprises a movable electronic element.

14. The package structure of claim 13, wherein the second side of the first wafer portion further has a protruding key ring and a recess surrounded by the key ring, the recess and the first side of the second wafer portion form a cavity for accommodating the movable electronic component and providing a moving space for the movable electronic component.

15. The package structure of claim 14, wherein the raised bond ring includes a raised portion on the second side of the first wafer portion and a metal bonding layer overlying the raised portion, the first side of the first wafer portion further having a passivation layer overlying the first side of the first substrate and burying the first electrical connection terminal therein.

16. The package structure of claim 14, wherein the first side of the second wafer portion further has a conductive bump thereon corresponding to the bonding ring, the conductive bump and the bonding ring being aligned and bonded to form the cavity.

17. The package structure of any of claims 11 to 16, wherein the second wafer portion comprises: a device body having the second device component, and a second substrate having the second electrical connection terminals on a surface thereof corresponding to the second device component; the device sheet is bonded to the second substrate and exposes the second electrical connection terminal.

18. The package structure according to any one of claims 11 to 16, wherein the die is temporarily bonded to the bonding surface of the third wafer by means of adhesive layer adhesion or electrostatic bonding.

19. The package structure according to any one of claims 11 to 16, wherein the rewiring structure comprises a conductive contact plug disposed in the encapsulation layer, or comprises a conductive contact plug disposed in the encapsulation layer and a rewiring metal layer disposed on the encapsulation layer and the conductive contact plug, the rewiring metal layer electrically connecting the conductive contact plug.