CN106206624A - Wafer-level packaging cap and manufacturing method thereof - Google Patents
Wafer-level packaging cap and manufacturing method thereof Download PDFInfo
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- CN106206624A CN106206624A CN201510211866.1A CN201510211866A CN106206624A CN 106206624 A CN106206624 A CN 106206624A CN 201510211866 A CN201510211866 A CN 201510211866A CN 106206624 A CN106206624 A CN 106206624A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 36
- 238000005530 etching Methods 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 238000007363 ring formation reaction Methods 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 claims 26
- 230000008569 process Effects 0.000 abstract description 8
- 230000010354 integration Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 24
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 12
- 239000012212 insulator Substances 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 11
- 238000001312 dry etching Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 239000002086 nanomaterial Substances 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910018459 Al—Ge Inorganic materials 0.000 description 2
- 229910015363 Au—Sn Inorganic materials 0.000 description 2
- 229910017755 Cu-Sn Inorganic materials 0.000 description 2
- 229910017927 Cu—Sn Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005323 electroforming Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
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Abstract
The invention discloses a method for manufacturing a wafer-level packaging cap, which comprises the following steps: providing a first wafer, wherein the first wafer is provided with a first surface and a second surface which are opposite; forming a first structure corresponding to the device structure on the second wafer on the first surface and covering the first bonding layer; forming a second structure corresponding to the device structure on the second wafer on the second surface; bonding a third wafer on the first bonding layer, and thinning the third wafer to a preset thickness; forming a first bond ring on the third wafer around the first structure; and etching the third wafer to form a frame under the first bonding ring, and removing the first bonding layer covering the first structure. The method reduces the bonding times of the corresponding structures on the first wafer and the second wafer, has simple process and easy integration, and avoids the problem of reduced alignment precision caused by multiple bonding processes.
Description
Technical field
The invention belongs to field of manufacturing semiconductor devices, particularly relate to a kind of wafer-level packaging block and
Manufacture method.
Background technology
Wafer-level packaging (WLP, Wafer Level Packaging), is that one is cut from wafer at chip
Before getting off, the technology i.e. encapsulated in batches on wafer.This technology comes across large scale integrated circuit the earliest
Package application, highly successful on CIS (CMOS Image Sensor) imager chip subsequently, and soon
Speed is extended in the package application of various kinds of sensors chip.
In the Wafer level packaging of sensor, how with capping structure, more fragile sensitive structure to be protected
Get up.Therefore, block all has the curved cavity of certain depth, in order to accommodate structure to be protected.Now,
The making of cavity is generally formed with etching mode, and due to the restriction of existing technique, is difficult to etching shape
The structure of reprocessing micro/nano-scale in the cavity become, therefore, it is impossible to meet the demand of some special sensor parts.
In order to enable above region corresponding to senser element, the tow sides of block all process required micro-
Micro-nano structure, existing two kinds of solutions, the first is: first at the positive and negative region processing corresponding to block wafer
Required micro-nano structure, then use the mode of electroforming to process on block wafer there is certain thickness bonding material
Form required cavity.The efficiency of the method electroforming is low, with high costs, and the cavity processed is follow-up
Wafer scale bonding packaging during there will be pressurized and collapse or expansion, poor reliability.
Another kind of method is: is directly bonded one layer of band what is called ccf layer wafer in sensor wafer, is i.e. passing
Sensor region is the two-sided Window-type structure ganged up, then has two-sided micro-nano knot on ccf layer on bonding packaging
The block wafer of structure.In the method, owing to ccf layer wafer needs to keep sufficient intensity, the thickness of ccf layer
Cannot accomplish that ratio is relatively thin, limit the overall dimensions of cavity size therebetween and device, additionally, technique needs
Repeatedly to be bonded alignment, cause micro-nano structure deviation relatively big, performance impairment.
Summary of the invention
It is an object of the invention at least overcome one of above-mentioned defect of the prior art, it is provided that Yi Zhongjing
Circle level encapsulation block and preparation method thereof, technique is simple and is easily integrated.
For achieving the above object, the technical scheme is that
A kind of manufacture method of wafer-level packaging block, including: provide the first wafer, the first wafer to have
Relative first surface and second surface；Formed on the first surface and the device architecture on the second wafer
The first corresponding structure, and cover the first bonded layer；Formed on a second surface and on the second wafer
The second structure that device architecture is corresponding；First bonded layer is bonded third wafer, and third wafer subtracts
It is as thin as predetermined thickness；The third wafer of the first structure periphery is formed the first bonding ring；Etch the 3rd
Wafer, forms framework under the first bonding ring, and removes the first bonded layer covering the first structure.
Optionally, further comprise the steps of:
Thering is provided the second wafer, the second wafer is formed device architecture, device architecture is formed around
Two bonding rings；
Carry out the first bonding ring and the bonding of the second bonding ring.
Optionally, described first bonding ring and the second bonding ring are metal bonding material.
Optionally, described first wafer and third wafer are silicon wafer, and the first bonded layer is silicon oxide.
Additionally, present invention also offers a kind of wafer-level packaging block, including:
First wafer, the first wafer has relative first surface and second surface；
First structure corresponding with the device architecture on the second wafer it is formed with on first surface；
Second structure corresponding with the device architecture on the second wafer it is formed with on second surface；
Framework on the first surface of the first structure periphery, is formed with first between framework and first surface
Bonded layer；
The first bonding ring on said frame.
Optionally, also include:
Second wafer, the second wafer is formed device architecture, device architecture be formed around second
Bonding ring, the second bonding ring and the first bonding ring key close and connect.
Optionally, described first bonding ring and the second bonding ring are metal bonding material.
Optionally, the first wafer is silicon wafer, and the first bonded layer is silicon oxide, and framework is silicon.
Wafer-level packaging block that the embodiment of the present invention provides and preparation method thereof, shape on the first wafer
After becoming the structure corresponding with the device architecture on the second wafer, it is bonded another by bonded layer trimorphism
Sheet, and form framework and bonding ring by third wafer, so, reduce the first wafer and the second crystalline substance
The bonding number of times of counter structure on sheet, technique is simple and is easily integrated, it is to avoid repeatedly make in bonding process
The problem that the alignment precision become reduces.
Accompanying drawing explanation
In order to be illustrated more clearly that the technical scheme that the present invention implements, below will be to required in embodiment
The accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only the present invention
Some embodiments, for those of ordinary skill in the art, before not paying creative work
Put, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the flow chart of the manufacture method of the wafer-level packaging block according to the embodiment of the present invention；
Fig. 2-Figure 12 is in each manufacture process manufacturing wafer-level packaging block according to the embodiment of the present invention
Structural representation.
Detailed description of the invention
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, the most right
The detailed description of the invention of the present invention is described in detail.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but the present invention
Other can also be used to be different from alternate manner described here implement, those skilled in the art can be not
Doing similar popularization in the case of running counter to intension of the present invention, therefore the present invention is not by following public specific embodiment
Restriction.
Secondly, the present invention combines schematic diagram and is described in detail, when describing the embodiment of the present invention in detail, for ease of
Illustrate, represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is only
Being example, it should not limit the scope of protection of the invention at this.Additionally, should comprise in actual fabrication length,
Width and the three-dimensional space of the degree of depth.
The invention provides the manufacture method of a kind of wafer-level packaging block, including: the first wafer is provided,
First wafer has relative first surface and second surface；Formed and the second wafer on the first surface
On the first structure corresponding to device architecture, and cover the first bonded layer；On a second surface formed with
The second structure that device architecture on second wafer is corresponding；First bonded layer is bonded third wafer,
And third wafer is thinned to predetermined thickness；The third wafer of the first structure periphery is formed the first bonding
Ring；Etching third wafer, forms framework under the first bonding ring, and removes and cover the of the first structure
One bonded layer.
In the present invention, the first wafer is formed the structure corresponding with the device architecture on the second wafer it
After, it is bonded another third wafer by bonded layer, and forms framework and bonding ring by third wafer,
So, reducing the bonding number of times of counter structure on the first wafer and the second wafer, technique is simple and is prone to
Integrated, it is to avoid the problem that the alignment precision repeatedly caused in bonding process reduces.
In order to be better understood from technical scheme and technique effect, below with reference to flow chart Fig. 1 pair
Specific embodiment is described in detail.
First, it is provided that the first wafer 100, the first wafer 100 has relative first surface 1001 and
Two surfaces 1002, with reference to shown in Fig. 2.
In the present invention, the first wafer 100 is the wafer for forming block, wafer (wafer),
With the second bonding chip after the formation block of this first wafer, the second wafer being formed with device architecture, this is first years old
The structure that device architecture that wafer is simultaneously used for being formed on the second wafer is corresponding.Wherein, on the second wafer
Device architecture can be such as optical pickocff, structure for example, two-sided lens knot corresponding on the first wafer
Structure, lattice raster structure and zone plate diffractive optical grating construction etc., the device architecture on the second wafer is all right
Can be any with second for other any type of device needing block to encapsulate, the first structure and the second structure
The micro-nano structure formed above device architecture corresponding region on wafer.
In an embodiment of the present invention, the first wafer 100 can be Semiconductor substrate, can be Si substrate,
Ge substrate, SiGe substrate, it is possible to for the transparent material such as glass, quartz.In other embodiments, described
Semiconductor substrate can also be the substrate including other elemental semiconductors or compound semiconductor, such as
GaAs, InP or SiC etc., it is also possible to for laminated construction, such as Si/SiGe etc., it is also possible to outside other
Prolong structure, such as SGOI (silicon germanium on insulator) etc..
In the present embodiment, the first wafer 100 is body silicon substrate, the first wafer 100 have two relative
Surface first surface 1001 and second surface 1002, the substrate of this side, two surfaces be for respectively forming with
The structure that device architecture is corresponding.
Then, in step S02, first surface 1001 is formed and the device architecture on the second wafer
The first corresponding structure 110, and cover the first bonded layer 102, and shape on second surface 1002
Become second structure 120 corresponding with the device architecture on the second wafer, with reference to shown in Fig. 5.
In the present invention, two surfaces of this first wafer 100 define and the device junction on the second wafer
The structure that structure is corresponding.
In the present embodiment, the device architecture on the second wafer is optical sensor device, the first wafer 100
The first structure 110 on first surface 1001 is lattice raster, and this first structure 110 can be formed at
On one surface, it is also possible to be formed in the substrate of first surface side, the second surface of the first wafer 100
The second structure 120 on 1002 is lattice raster, this second structure 120 can be formed at second surface it
On, it is also possible to it is formed in the substrate of second surface side.Concrete, first, as in figure 2 it is shown, permissible
The first structure is formed by dry etching method.After forming the first structure 110, as it is shown on figure 3, permissible
Carrying out the deposit of the first bonded layer 102, this first bonded layer 102 can be oxide skin(coating), such as silicon oxide,
For with being bonded, meanwhile, as the etching stop layer in subsequent etch step of third wafer.
Then, the second structure 120 can be formed by dry etching method, as shown in Figure 4.
Then, two surfaces complete the first wafer are formed respectively the structure corresponding with device architecture it
After, carry out flatening process, for example with CMP (cmp), the first bonded layer 102 is entered
Row planarization, as it is shown in figure 5, the thickness of the first bonded layer 102 after Ping Tanhua can be 0.2～10um.
In this embodiment, suitable to the forming step of above first structure, the first bonded layer and the second structure
Sequence is not particularly limited, it is also possible to be initially formed the second structure, forms the first structure and the first knot the most again
The first bonded layer covered on structure；Or, it is initially formed the first structure, then deposits the first bonded layer and carry out
Planarization, then, forms the second structure.
Then, in step S03, the first bonded layer 102 is bonded third wafer 300, and trimorphism by the
Sheet 300 is thinned to make a reservation for, and its thickness can be 5～500um, with reference to shown in Fig. 7.
This third wafer 300 is for forming the framework of the device architecture accommodated on the second wafer.The present invention's
In embodiment, third wafer 300 can be Semiconductor substrate, can be Si substrate, Ge substrate, SiGe
Substrate, SOI (silicon-on-insulator, Silicon On Insulator) or GOI (germanium on insulator, Germanium
On Insulator) etc..In other embodiments, described Semiconductor substrate can also be for including other elements
Quasiconductor or the substrate of compound semiconductor, such as GaAs, InP or SiC etc., it is also possible to for lamination
Structure, such as Si/SiGe etc., it is also possible to other epitaxial structures, such as SGOI (silicon germanium on insulator)
Deng.
In the present embodiment, described third wafer 300 is body silicon substrate, has identical with the first wafer 100
Size, bond with the first bonded layer 102 on the first wafer by the way of diffusion interlinked, it is achieved first
Wafer 100 is bonded, as shown in Figure 6 with third wafer 300.After bonding, by third wafer 300
It is thinned to required thickness, in the way of combining with chemical attack to use mechanical reduction, third wafer can be subtracted
It is as thin as required thickness, as it is shown in fig. 7, required thickness is by the device junction on the second wafer encapsulated with it
The height of structure determines.
Then, step S04, the third wafer 300 around the first structure 110 form the first key
Cyclization 310, with reference to shown in Fig. 8.
This first bonding ring 310 is for the bonded layer with the second bonding chip, can by deposit suitably
Bonding material, then carries out patterning to form this first bonding ring 310, as shown in Figure 8.In this enforcement
In example, described first bonding ring 310 material be metal bonding material, for example, Au-Au, Au-Sn,
Au-In, Cu-Cu, Cu-Sn, Al-Ge etc. or their combination.
Then, in step S05, etch third wafer, form framework 320 310 times at the first bonding ring,
And remove the first bonded layer 102 covering the first structure 110, with reference to shown in Figure 10.
Can be by wet method or dry etching by the first superstructure, i.e. with the device architecture pair on the second wafer
The third wafer answering region is removed, thus forms framework 320, and the region in this framework 320 forms accommodating sky
Between, for accommodating the device architecture on the second wafer.Then, wet method or dry etching can be passed through by first
Superstructure, i.e. the first bonded layer 102 with the device architecture corresponding region on the second wafer are removed, cruelly
Expose the first structure 110, as shown in Figure 10.
So far, define wafer-level packaging block, this structure for further be formed with device architecture
Second wafer is bonded.
Concrete, first, it is provided that the second wafer 200, the second wafer 200 is formed with device architecture 220,
Device architecture 220 is formed around the second bonding ring 210, with reference to shown in Figure 11.
In the present invention, the second wafer 200 is the wafer for forming device architecture 220, the second wafer
200 can be Semiconductor substrate, can be Si substrate, Ge substrate, SiGe substrate, SOI (insulator
Upper silicon, Silicon On Insulator) or GOI (germanium on insulator, Germanium On Insulator)
Deng.In other embodiments, described Semiconductor substrate can also be for including other elemental semiconductors or chemical combination
The substrate of thing quasiconductor, such as GaAs, InP or SiC etc., it is also possible to for laminated construction, such as Si/SiGe
Deng, it is also possible to other epitaxial structures, such as SGOI (silicon germanium on insulator) etc..
In the present embodiment, the second wafer 200 is body silicon substrate, according to the conventional method, such as sputtering, steams
Send out or plating etc., the second wafer is formed the device in the second bonding ring 210, and the second bonding ring
Structure 220, this device architecture is optical sensor device, and described second bonding ring 210 is to be bonded ring with first
310 corresponding bonding rings, i.e. position are corresponding, material is the material that can be mutually bonded, the second bonding ring
Material is also metal bonding material, for example, Au-Au, Au-Sn, Au-In, Cu-Cu, Cu-Sn, Al-Ge
Deng or their combination.
Then, the first bonding ring 310 and bonding of the second bonding ring 210 is carried out, with reference to shown in Figure 12.
As shown in figure 11, by the first bonding surface, ring 310 place towards the second bonding surface, ring 210 place,
As required, under the conditions of vacuum or height airtight work, carry out the first bonding ring 310 and the second bonding ring
The solder bonds of 210, thus realize the block of the first wafer and the encapsulation of the second wafer, as shown in figure 12.
So far, the wafer of the wafer-level packaging block of the first wafer and the device architecture of the second wafer is completed
Level encapsulation.
Above the manufacture method of the wafer-level packaging block of the embodiment of the present invention is described in detail,
Additionally, present invention also offers the wafer-level packaging block that said method is formed, with reference to shown in Figure 12, bag
Include:
First wafer 100, the first wafer 100 has relative first surface 1001 and second surface
1002；
First structure corresponding with the device architecture on the second wafer it is formed with on first surface 1001
110；
Second structure corresponding with the device architecture on the second wafer it is formed with on second surface 1002
210；
The framework 320 on first surface around first structure 110, framework 320 and first surface 1001
Between be formed with the first bonded layer 102；
The first bonding ring 310 on described framework 320.
Further, the structure of this wafer-level packaging block with the second wafer key being formed with device architecture
Close, farther include: the second wafer 200, the second wafer 200 is formed with device architecture 220, device
Part structure 220 be formed around the second bonding ring 210, the second bonding ring 210 is bonded ring with first
310 bondings connect.
Wherein, described first bonding ring and the second bonding ring are metal bonding material, and the first wafer is silicon wafer
Sheet, the first bonded layer is silicon oxide, and framework is silicon.
The above, be only presently preferred embodiments of the present invention, not the present invention is made any in form
Restriction.
Each embodiment in this specification all uses the mode gone forward one by one to describe, phase between each embodiment
As homophase part see mutually, each embodiment stress with other embodiments
Difference.For constructive embodiment, owing to it is substantially similar to embodiment of the method,
So describing fairly simple, relevant part sees the part of embodiment of the method and illustrates.
Although the present invention discloses as above with preferred embodiment, but is not limited to the present invention.Any
Those of ordinary skill in the art, without departing under technical solution of the present invention ambit, may utilize
Technical solution of the present invention is made many possible variations and modification by method and the technology contents of stating announcement, or
It is revised as the Equivalent embodiments of equivalent variations.Therefore, every content without departing from technical solution of the present invention,
And repair any simple modification made for any of the above embodiments, equivalent variations according to the technical spirit of the present invention
Decorations, all still fall within the range of technical solution of the present invention protection.
Claims (8)
1. the manufacture method of a wafer-level packaging block, it is characterised in that include step:
The first wafer, the first wafer is provided to have relative first surface and second surface；
Form first structure corresponding with the device architecture on the second wafer on the first surface, and cover
First bonded layer, and form second corresponding with the device architecture on the second wafer on a second surface
Structure；
First bonded layer is bonded third wafer, and third wafer is thinned to predetermined thickness；
The third wafer of the first structure periphery is formed the first bonding ring；
Etching third wafer, forms framework under the first bonding ring, and removes and cover the of the first structure
One bonded layer.
Manufacture method the most according to claim 1, it is characterised in that further comprise the steps of:
Thering is provided the second wafer, the second wafer is formed device architecture, device architecture is formed around
Two bonding rings；
Carry out the first bonding ring and the bonding of the second bonding ring.
Manufacture method the most according to claim 2, it is characterised in that described first bonding ring and
Second bonding ring is metal bonding material.
Manufacture method the most according to claim 1, it is characterised in that described first wafer and
Three wafers are silicon wafer, and the first bonded layer is silicon oxide.
5. a wafer-level packaging block, it is characterised in that including:
First wafer, the first wafer has relative first surface and second surface；
First structure corresponding with the device architecture on the second wafer it is formed with on first surface；
Second structure corresponding with the device architecture on the second wafer it is formed with on second surface；
Framework on the first surface of the first structure periphery, is formed with first between framework and first surface
Bonded layer；
The first bonding ring on said frame.
Wafer-level packaging block the most according to claim 5, it is characterised in that also include:
Second wafer, the second wafer is formed device architecture, device architecture be formed around second
Bonding ring, the second bonding ring and the first bonding ring key close and connect.
Wafer-level packaging block the most according to claim 6, it is characterised in that described first key
Cyclization and the second bonding ring are metal bonding material.
Wafer-level packaging block the most according to claim 5, it is characterised in that the first wafer is
Silicon wafer, the first bonded layer is silicon oxide, and framework is silicon.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510211866.1A CN106206624A (en) | 2015-04-29 | 2015-04-29 | Wafer-level packaging cap and manufacturing method thereof |
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| CN201510211866.1A CN106206624A (en) | 2015-04-29 | 2015-04-29 | Wafer-level packaging cap and manufacturing method thereof |
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| CN111348613B (en) * | 2018-12-21 | 2023-12-26 | 中芯集成电路（宁波）有限公司 | Packaging method and packaging structure |
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Application publication date: 20161207 |