CN204332941U - A kind of 3-D stacks encapsulating structure - Google Patents
A kind of 3-D stacks encapsulating structure Download PDFInfo
- Publication number
- CN204332941U CN204332941U CN201520055824.9U CN201520055824U CN204332941U CN 204332941 U CN204332941 U CN 204332941U CN 201520055824 U CN201520055824 U CN 201520055824U CN 204332941 U CN204332941 U CN 204332941U
- Authority
- CN
- China
- Prior art keywords
- metal
- chip
- layer
- encapsulation
- interconnection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The utility model discloses a kind of 3-D stacks encapsulating structure, belong to technical field of semiconductor encapsulation.It encapsulation monomer A (10) comprising encapsulation monomers B (20) and be positioned at several stacked package below encapsulation monomers B (20), described encapsulation monomer A (is connected by link (8) between 10 and encapsulation monomers B (20) and between neighbouring two encapsulation monomer A (10), described encapsulation monomer A (10) comprises chip packing-body and lower package body, chip I (41) is positioned at the central authorities of whole chip packing-body, encapsulation monomers B (20) comprises chip packing-body and lower package body, and chip II (42) is positioned at the central authorities of whole chip packing-body.The 3-D stacks encapsulating structure that the utility model is formed does not need carrier for bearing chip, simple for structure, meets miniaturization trend.
Description
Technical field
The utility model relates to a kind of 3-D stacks encapsulating structure, belongs to technical field of semiconductor encapsulation.
Background technology
As encapsulating superintegrated major way at present, the packaging body lamination in 3-D stacks encapsulating structure has become the first-selection of industry.
In existing packaging body laminated packaging structure, as the unit of packaging body stacked package, each independently packaging body need to utilize pad pasting substrate as the support plate of encapsulation when encapsulating, in order to carry packed chip 4, complex structure.Be illustrated in figure 1 a typical two-layer stacked package design, the packaging body 13 of the second layer is welded on the packaging body 11 of ground floor by the reflux course of soldered ball 12, and more multi-layered stacked package design can repeat as above process.Disturb in order to avoid the chip 4 of ground floor and the support plate of the second layer produce, the method needs to use large-sized solder ball, and larger solder ball needs larger space, to prevent short circuit between solder ball, welding density in this approach lower, be unfavorable for reducing encapsulation volume, do not meet miniaturized packaging trend.
Summary of the invention
The purpose of this utility model is the deficiency overcoming above-mentioned packaging body laminated packaging structure, provides one not need carrier for bearing chip, simple for structure, meets the 3-D stacks encapsulating structure of trend toward miniaturization.
The purpose of this utility model is achieved in that
A kind of 3-D stacks encapsulating structure of the utility model, it comprises encapsulation monomers B and is positioned at the encapsulation monomer A of several stacked package below encapsulation monomers B, be connected by link between described encapsulation monomer A and encapsulation monomers B and between neighbouring two encapsulation monomer A
Described encapsulation monomer A comprises chip packing-body and lower package body, described chip packing-body comprises at least one chip I and interconnection metal layer again, described chip I is positioned at the central authorities of whole chip packing-body, described interconnection metal layer is more optionally arranged at the surrounding of this chip I, described chip I is connected by connector I with the nearly die terminals of interconnection metal layer again, the lower surface of described interconnection metal layer again arranges metal seed layer, and the lower input/output terminal of chip packing-body is set in the lower surface of described metal seed layer
In described chip I homonymy, the die terminals far away of described interconnection metal layer again arranges metal column II, described metal column II and again interconnection metal layer are connected, and the level height of this metal column II is higher than the level height of chip I, described interconnection metal layer again, metal column II, chip I, connector I and metal seed layer and space filling bag closure material to each other thereof, form encapsulating material layer II, described encapsulating material layer II exposes the upper surface of metal column II, forms the upper input/output terminal of chip packing-body;
Described lower package body comprises metal column I and encapsulating material layer I, described metal column I is connected with the lower input/output terminal of described chip packing-body, described encapsulating material layer I encapsulated metal post I, and expose the lower surface of metal column I, form the input/output terminal of lower package body;
Encapsulation monomers B comprises chip packing-body and lower package body, described chip packing-body comprises at least one chip II and interconnection metal layer again, described chip II is positioned at the central authorities of whole chip packing-body, described interconnection metal layer is more optionally arranged at the surrounding of this chip II, described chip II is connected by connector II with the nearly die terminals of interconnection metal layer again, the lower surface of described interconnection metal layer again arranges metal seed layer, and the lower input/output terminal of chip packing-body is set in the lower surface of described metal seed layer
Described interconnection metal layer again, chip II and metal seed layer and space filling bag closure material to each other thereof, form encapsulating material layer II;
Described lower package body comprises metal column I and encapsulating material layer I, described metal column I is connected with the lower input/output terminal of described chip packing-body, described encapsulating material layer I encapsulated metal post I, and expose the lower surface of metal column I, form the input/output terminal of lower package body.
Described connector I is identical with connector II, is the metal connecting layer on dimpling block and top thereof or is metal lead wire.
Described connector I is the metal connecting layer on dimpling block and top thereof, and connector II is metal lead wire.
Described connector I is metal lead wire, and connector II is the metal connecting layer on dimpling block and top thereof.
The circular in cross-section of described metal column I and metal column II or polygon.
Described link is soldered ball or welding block, the upper input/output terminal of the chip packing-body of its one end connection encapsulation monomer A, the input/output terminal of its other end connection encapsulation monomers B lower package body.
The height h1 scope of described metal column I is 5 ~ 100 microns.
The height h1 scope of described metal column I is 10 ~ 20 microns is good.
The scope of the height h2 of described metal column II is at 100 ~ 300 microns.
The thickness of described metal seed layer is 0.01 ~ 2 micron.
the beneficial effects of the utility model are:
The thickness of each chip packing-body of 3-D stacks encapsulating structure of the present utility model is directly or indirectly controlled by metal column, irrelevant with support plate, soldered ball etc., save space, meet the needs of miniaturization, make 3-D stacks encapsulating structure at logical circuit and memory integration field, especially manufacture the advanced mobile communication platform of high-end portable formula equipment and smart mobile phone use advantageously.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of existing laminated packaging structure;
Fig. 2 is the tangent plane schematic diagram of the embodiment one of a kind of 3-D stacks encapsulating structure of the utility model;
Fig. 3 is the distortion of Fig. 2;
Fig. 4 is the tangent plane schematic diagram of the embodiment two of a kind of 3-D stacks encapsulating structure of the utility model;
Fig. 5 is the tangent plane schematic diagram of the embodiment three of a kind of 3-D stacks encapsulating structure of the utility model;
Fig. 6 is the tangent plane schematic diagram of the embodiment four of a kind of 3-D stacks encapsulating structure of the utility model;
In figure:
Encapsulation monomer A 10
Metal column I 111
Encapsulating material layer I 112
The input/output terminal 113 of lower package body
Metal seed layer 121
Interconnection metal layer 122 again
Metal column II 123
The lower input/output terminal 124 of chip packing-body
The upper input/output terminal 125 of chip packing-body
Encapsulating material layer II 128
Encapsulation monomers B 20
Metal column I 211
Encapsulating material layer I 212
The input/output terminal 213 of lower package body
Metal seed layer 221
Interconnection metal layer 222 again
The lower input/output terminal 224 of chip packing-body
Encapsulating material layer II 228
Chip I 41
Chip II 42
Dimpling block 5
Metal connecting layer 51
Metal lead wire 6
Link 8.
Embodiment
Describe the utility model more fully hereinafter with reference to accompanying drawing now, exemplary embodiment of the present utility model shown in the drawings, thus scope of the present utility model is conveyed to those skilled in the art by the disclosure fully.But the utility model can realize in many different forms, and should not be interpreted as being limited to the embodiment set forth here.
Embodiment one, see Fig. 2
A kind of 3-D stacks encapsulating structure of the utility model comprises encapsulation monomer A 10 and encapsulation monomers B 20, and encapsulation monomer A 10 is positioned at the below of encapsulation monomers B 20.Be connected by the link such as soldered ball, welding block 8 between encapsulation monomer A 10 and encapsulation monomers B 20.
Wherein, encapsulate monomer A 10 and comprise chip packing-body and lower package body.The chip I 41 of chip packing-body is positioned at the central authorities of whole chip packing-body, then interconnection metal layer 122 is optionally distributed in the surrounding of this chip I 41.Chip I 41 can be more than one, and its model can be the same or different, and arranges on demand.Adopt chip I 41 reverse installation process, the nearly die terminals of chip I 41 and interconnection metal layer 122 is again connected with interconnection metal layer 122 upside-down mounting again by dimpling block 5 and metal connecting layer 51, formation electric interconnection.The material of interconnection metal layer 122 is a kind of or several arbitrarily combination in copper Cu, iron Fe that electric conductivity is good, nickel again.Dimpling block 5 can be column or bulk, and the Electrode connection of its one end near chip I 41 and chip I 41, it can be made up of at least one element of following elements: copper Cu, nickel, vanadium V, titanium Ti, palladium Pd, golden Au, silver-colored Ag.Metal connecting layer 51 is arranged at the top of dimpling block 5, can be made up of: tin Sn, silver-colored Ag, copper Cu, golden Au, bismuth Bi, plumbous Pd, to strengthen the firmness of connection at least one element of following elements.
Usually, then the lower surface of interconnection metal layer 122 is provided with the metal seed layer 121 that thickness is 0.01 ~ 2 micron, then interconnection metal layer 122 is formed thereon by the method for plating or chemical plating.This metal seed layer 121 can be individual layer, bilayer or multilayer, determines according to actual needs.The material of metal seed layer 121 can be the composition of a kind of or any several element in copper Cu, titanium Ti, iron Fe, cobalt Co and nickel.The lower surface of this metal seed layer 121 arranges the lower input/output terminal 124 of chip packing-body.
In the homonymy of chip I 41, metal column II 123 is arranged at the die terminals far away of interconnection metal layer 122 again, its circular in cross-section or the polygon such as quadrangle, hexagon, its number and arrangement mode design according to actual needs, and this metal column II 123 and again interconnection metal layer 122 are connected.Usually, the scope of the height h2 of metal column II 123 is at 100 ~ 300 microns.Usually be as the criterion with the level height of the level height of metal column II 123 higher than chip I 41, to hold chip I 41.A kind of or several arbitrarily combination in the material of metal column II 123 is conduction, heat conductivility is good copper Cu, iron Fe, nickel.
Encapsulating material encapsulate chip I 41, again interconnection metal layer 122, metal column II 123, dimpling block 5, metal connecting layer 51 and metal seed layer 121 and space to each other thereof, form encapsulating material layer II 128.The upper surface of metal column II 123 exposes encapsulating material layer II 128, forms the upper input/output terminal 125 of chip packing-body.
Lower package body comprises the encapsulating material layer I 112 of the metal column I 111 and encapsulated metal post I 111 be connected with the lower input/output terminal 125 of chip packing-body.The circular in cross-section of metal column I 111 or the polygon such as quadrangle, hexagon, its number and arrangement mode are also determined by actual needs.The height h1 scope of metal column I 111 is 5 ~ 100 microns, is good with 10 ~ 20 microns, to meet the trend of slimming encapsulation.A kind of or several arbitrarily combination in the material of metal column I 111 is conduction, heat conductivility is good copper Cu, iron Fe, nickel.The lower surface of metal column I 111 exposes encapsulating material layer I 112, forms the input/output terminal 113 of lower package body, to be connected with the substrate such as PCB.
Encapsulation monomers B 20 comprises chip packing-body and lower package body.Chip packing-body comprises at least one chip II 42 and interconnection metal layer 222 again, and chip II 42 is positioned at the central authorities of whole chip packing-body, then interconnection metal layer 222 is optionally arranged at the surrounding of this chip II 42.Chip II 42 also can be more than one, and its model can be the same or different, and arranges on demand.Chip II 42 adopts reverse installation process to be connected by dimpling block 5 and metal connecting layer 51 upside-down mounting with the nearly die terminals of interconnection metal layer 222 again, formation electric interconnection.The lower surface of interconnection metal layer 222 arranges metal seed layer 221 again, and the thickness of metal seed layer 221 is 0.01 ~ 2 micron.The lower surface of metal seed layer 221 arranges the lower input/output terminal 224 of chip packing-body.Interconnection metal layer 222, chip II 42 and metal seed layer 221 and space filling bag closure material to each other thereof again, forms encapsulating material layer II 228.
Lower package body comprises metal column I 211 and encapsulating material layer I 212, and metal column I 211 is connected with the lower input/output terminal 224 of chip packing-body.The circular in cross-section of metal column I 211 or the polygon such as quadrangle, hexagon, its number and arrangement mode are also determined by actual needs.Encapsulating material layer I 212 encapsulated metal post I 211, and expose the lower surface of metal column I 211, form the input/output terminal 213 of lower package body.Therefore, the upper input/output terminal 125 of the chip packing-body of one end connection encapsulation monomer A 10 of link 8, the input/output terminal 213 of its other end connection encapsulation monomers B 20 lower package body, forms electrical connection.
During actual use, encapsulation monomer A 10 can be two or more, and it is shaped by the mode of stacked package, is connected between neighbouring two encapsulation monomer A 10 by link 8.As shown in Figure 3, illustrate the 3-D stacks encapsulating structure with encapsulation monomer A 11, encapsulation monomer A 12 and encapsulation monomers B 20, encapsulation monomer A 11 is identical or similar with the encapsulating structure of encapsulation monomer A 12, and attainable function can be identical, also can be different.Certainly, encapsulate between the metal column I of monomer A 10 and metal column II and also can there is no electrical interconnection, by some metal levels of many cloth to improve the heat-sinking capability of 3-D stacks encapsulating structure.
Embodiment two, see Fig. 4
A kind of 3-D stacks encapsulating structure of the utility model comprises encapsulation monomer A 10 and encapsulation monomers B 20, and encapsulation monomer A 10 is positioned at the below of encapsulation monomers B 20.Be connected by the link such as soldered ball, welding block 8 between encapsulation monomer A 10 and encapsulation monomers B 20.
Wherein, encapsulate monomer A 10 and comprise chip packing-body and lower package body.The chip I 41 of chip packing-body is positioned at the central authorities of whole chip packing-body, then interconnection metal layer 122 is optionally distributed in the surrounding of this chip I 41.Chip I 41 can be more than one, and its model can be the same or different, and arranges on demand.Adopt chip I 41 formal dress technique, the nearly die terminals of chip I 41 and interconnection metal layer 122 is again connected with interconnection metal layer 122 formal dress again by metal lead wire 6, formation electric interconnection.The material of interconnection metal layer 122 is a kind of or several arbitrarily combination in copper Cu, iron Fe that electric conductivity is good, nickel again.The material of metal lead wire 6 is a kind of or several arbitrarily combination in the golden Au that electric conductivity is good, silver-colored Ag, copper Cu, nickel, aluminium Al.
Usually, then the lower surface of interconnection metal layer 122 is provided with the metal seed layer 121 that thickness is 0.01 ~ 2 micron, then interconnection metal layer 122 is formed thereon by the method for plating or chemical plating.This metal seed layer 121 can be individual layer, bilayer or multilayer, determines according to actual needs.The material of metal seed layer 121 can be the composition of a kind of or any several element in copper Cu, titanium Ti, iron Fe, cobalt Co and nickel.The lower surface of this metal seed layer 121 arranges the lower input/output terminal 124 of chip packing-body.
In the homonymy of chip I 41, metal column II 123 is arranged at the die terminals far away of interconnection metal layer 122 again, its circular in cross-section or the polygon such as quadrangle, hexagon, its number and arrangement mode design according to actual needs, and this metal column II 123 and again interconnection metal layer 122 are connected.Usually, the scope of the height h2 of metal column II 123 is at 100 ~ 300 microns.Usually be as the criterion with the level height of the level height of metal column II 123 higher than chip I 41, to hold chip I 41.A kind of or several arbitrarily combination in the material of metal column II 123 is conduction, heat conductivility is good copper Cu, iron Fe, nickel.
Encapsulating material encapsulate chip I 41, again interconnection metal layer 122, metal column II 123, metal lead wire 6 and metal seed layer 121 and space to each other thereof, form encapsulating material layer II 128.The upper surface of metal column II 123 exposes encapsulating material layer II 128, forms the upper input/output terminal 125 of chip packing-body.
Lower package body comprises the encapsulating material layer I 112 of the metal column I 111 and encapsulated metal post I 111 be connected with the lower input/output terminal 125 of chip packing-body.The circular in cross-section of metal column I 111 or the polygon such as quadrangle, hexagon, its number and arrangement mode are also determined by actual needs.The height h1 scope of metal column I 111 is 5 ~ 100 microns, is good with 10 ~ 20 microns, to meet the trend of slimming encapsulation.A kind of or several arbitrarily combination in the material of metal column I 111 is conduction, heat conductivility is good copper Cu, iron Fe, nickel.The lower surface of metal column I 111 exposes encapsulating material layer I 112, forms the input/output terminal 113 of lower package body, to be connected with the substrate such as PCB.
Encapsulation monomers B 20 comprises chip packing-body and lower package body.Chip packing-body comprises at least one chip II 42 and interconnection metal layer 222 again, and chip II 42 is positioned at the central authorities of whole chip packing-body, then interconnection metal layer 222 is optionally arranged at the surrounding of this chip II 42.Chip II 42 also can be more than one, and its model can be the same or different, and arranges on demand.Chip II 42 is connected by metal lead wire 6 formal dress with the nearly die terminals of interconnection metal layer 222 again, forms electric interconnection.
The lower surface of interconnection metal layer 222 arranges metal seed layer 221 again, and the thickness of metal seed layer 221 is 0.01 ~ 2 micron.The lower surface of metal seed layer 221 arranges the lower input/output terminal 224 of chip packing-body.Interconnection metal layer 222, chip II 42, metal lead wire 6 and metal seed layer 221 and space filling bag closure material to each other thereof again, forms encapsulating material layer II 228.
Lower package body comprises metal column I 211 and encapsulating material layer I 212, and metal column I 211 is connected with the lower input/output terminal 224 of chip packing-body.The circular in cross-section of metal column I 211 or the polygon such as quadrangle, hexagon, its number and arrangement mode are also determined by actual needs.Encapsulating material layer I 212 encapsulated metal post I 211, and expose the lower surface of metal column I 211, form the input/output terminal 213 of lower package body.Therefore, the upper input/output terminal 125 of the chip packing-body of one end connection encapsulation monomer A 10 of link 8, the input/output terminal 213 of its other end connection encapsulation monomers B 20 lower package body, forms electrical connection.
Embodiment three, see Fig. 5
A kind of 3-D stacks encapsulating structure of the utility model comprises encapsulation monomer A 10 and encapsulation monomers B 20, and encapsulation monomer A 10 is positioned at the below of encapsulation monomers B 20.Be connected by the link such as soldered ball, welding block 8 between encapsulation monomer A 10 and encapsulation monomers B 20.
Wherein, encapsulate monomer A 10 and comprise chip packing-body and lower package body.The chip I 41 of chip packing-body is positioned at the central authorities of whole chip packing-body, then interconnection metal layer 122 is optionally distributed in the surrounding of this chip I 41.Chip I 41 can be more than one, and its model can be the same or different, and arranges on demand.Adopt chip I 41 reverse installation process, the nearly die terminals of chip I 41 and interconnection metal layer 122 is again connected with interconnection metal layer 122 upside-down mounting again by dimpling block 5 and metal connecting layer 51, formation electric interconnection.The material of interconnection metal layer 122 is a kind of or several arbitrarily combination in copper Cu, iron Fe that electric conductivity is good, nickel again.Dimpling block 5 can be column or bulk, and the Electrode connection of its one end near chip I 41 and chip I 41, it can be made up of at least one element of following elements: copper Cu, nickel, vanadium V, titanium Ti, palladium Pd, golden Au, silver-colored Ag.Metal connecting layer 51 can be made up of at least one element of following elements: tin Sn, silver-colored Ag, copper Cu, golden Au, bismuth Bi, plumbous Pd, to strengthen the firmness of connection.
Usually, then the lower surface of interconnection metal layer 122 is provided with the metal seed layer 121 that thickness is 0.01 ~ 2 micron, then interconnection metal layer 122 is formed thereon by the method for plating or chemical plating.This metal seed layer 121 can be individual layer, bilayer or multilayer, determines according to actual needs.The material of metal seed layer 121 can be the composition of a kind of or any several element in copper Cu, titanium Ti, iron Fe, cobalt Co and nickel.The lower surface of this metal seed layer 121 arranges the lower input/output terminal 124 of chip packing-body.
In the homonymy of chip I 41, metal column II 123 is arranged at the die terminals far away of interconnection metal layer 122 again, its circular in cross-section or the polygon such as quadrangle, hexagon, its number and arrangement mode design according to actual needs, and this metal column II 123 and again interconnection metal layer 122 are connected.Usually, the scope of the height h2 of metal column II 123 is at 100 ~ 300 microns.Usually be as the criterion with the level height of the level height of metal column II 123 higher than chip I 41, to hold chip I 41.A kind of or several arbitrarily combination in the material of metal column II 123 is conduction, heat conductivility is good copper Cu, iron Fe, nickel.
Encapsulating material encapsulate chip I 41, again interconnection metal layer 122, metal column II 123, dimpling block 5, metal connecting layer 51 and metal seed layer 121 and space to each other thereof, form encapsulating material layer II 128.The upper surface of metal column II 123 exposes encapsulating material layer II 128, forms the upper input/output terminal 125 of chip packing-body.
Lower package body comprises the encapsulating material layer I 112 of the metal column I 111 and encapsulated metal post I 111 be connected with the lower input/output terminal 125 of chip packing-body.The circular in cross-section of metal column I 111 or the polygon such as quadrangle, hexagon, its number and arrangement mode are also determined by actual needs.The height h1 scope of metal column I 111 is 5 ~ 100 microns, is good with 10 ~ 20 microns, to meet the trend of slimming encapsulation.A kind of or several arbitrarily combination in the material of metal column I 111 is conduction, heat conductivility is good copper Cu, iron Fe, nickel.The lower surface of metal column I 111 exposes encapsulating material layer I 112, forms the input/output terminal 113 of lower package body, to be connected with the substrate such as PCB.
Encapsulation monomers B 20 comprises chip packing-body and lower package body.Chip packing-body comprises at least one chip II 42 and interconnection metal layer 222 again, and chip II 42 is positioned at the central authorities of whole chip packing-body, then interconnection metal layer 222 is optionally arranged at the surrounding of this chip II 42.Chip II 42 also can be more than one, and its model can be the same or different, and arranges on demand.Chip II 42 is connected by metal lead wire 6 formal dress with the nearly die terminals of interconnection metal layer 222 again, forms electric interconnection.
The lower surface of interconnection metal layer 222 arranges metal seed layer 221 again, and the thickness of metal seed layer 221 is 0.01 ~ 2 micron.The lower surface of metal seed layer 221 arranges the lower input/output terminal 224 of chip packing-body.Interconnection metal layer 222, chip II 42, metal lead wire 6 and metal seed layer 221 and space filling bag closure material to each other thereof again, forms encapsulating material layer II 228.
Lower package body comprises metal column I 211 and encapsulating material layer I 212, and metal column I 211 is connected with the lower input/output terminal 224 of chip packing-body.The circular in cross-section of metal column I 211 or the polygon such as quadrangle, hexagon, its number and arrangement mode are also determined by actual needs.Encapsulating material layer I 212 encapsulated metal post I 211, and expose the lower surface of metal column I 211, form the input/output terminal 213 of lower package body.Therefore, the upper input/output terminal 125 of the chip packing-body of one end connection encapsulation monomer A 10 of link 8, the input/output terminal 213 of its other end connection encapsulation monomers B 20 lower package body, forms electrical connection.
Embodiment four, see Fig. 6
A kind of 3-D stacks encapsulating structure of the utility model comprises encapsulation monomer A 10 and encapsulation monomers B 20, and encapsulation monomer A 10 is positioned at the below of encapsulation monomers B 20.Be connected by the link such as soldered ball, welding block 8 between encapsulation monomer A 10 and encapsulation monomers B 20.
Wherein, encapsulate monomer A 10 and comprise chip packing-body and lower package body.The chip I 41 of chip packing-body is positioned at the central authorities of whole chip packing-body, then interconnection metal layer 122 is optionally distributed in the surrounding of this chip I 41.Chip I 41 can be more than one, and its model can be the same or different, and arranges on demand.Adopt chip I 41 formal dress technique, the nearly die terminals of chip I 41 and interconnection metal layer 122 is again connected with interconnection metal layer 122 formal dress again by metal lead wire 6, formation electric interconnection.The material of interconnection metal layer 122 is a kind of or several arbitrarily combination in copper Cu, iron Fe that electric conductivity is good, nickel again.The material of metal lead wire 6 is a kind of or several arbitrarily combination in the golden Au that electric conductivity is good, silver-colored Ag, copper Cu, nickel, aluminium Al.
Usually, then the lower surface of interconnection metal layer 122 is provided with the metal seed layer 121 that thickness is 0.01 ~ 2 micron, then interconnection metal layer 122 is formed thereon by the method for plating or chemical plating.This metal seed layer 121 can be individual layer, bilayer or multilayer, determines according to actual needs.The material of metal seed layer 121 can be the composition of a kind of or any several element in copper Cu, titanium Ti, iron Fe, cobalt Co and nickel.The lower surface of this metal seed layer 121 arranges the lower input/output terminal 124 of chip packing-body.
In the homonymy of chip I 41, metal column II 123 is arranged at the die terminals far away of interconnection metal layer 122 again, its circular in cross-section or the polygon such as quadrangle, hexagon, its number and arrangement mode design according to actual needs, and this metal column II 123 and again interconnection metal layer 122 are connected.Usually, the scope of the height h2 of metal column II 123 is at 100 ~ 300 microns.Usually be as the criterion with the level height of the level height of metal column II 123 higher than chip I 41, to hold chip I 41.A kind of or several arbitrarily combination in the material of metal column II 123 is conduction, heat conductivility is good copper Cu, iron Fe, nickel.
Encapsulating material encapsulate chip I 41, again interconnection metal layer 122, metal column II 123, dimpling block 5, metal connecting layer 51 and metal seed layer 121 and space to each other thereof, form encapsulating material layer II 128.The upper surface of metal column II 123 exposes encapsulating material layer II 128, forms the upper input/output terminal 125 of chip packing-body.
Lower package body comprises the encapsulating material layer I 112 of the metal column I 111 and encapsulated metal post I 111 be connected with the lower input/output terminal 125 of chip packing-body.The circular in cross-section of metal column I 111 or the polygon such as quadrangle, hexagon, its number and arrangement mode are also determined by actual needs.The height h1 scope of metal column I 111 is 5 ~ 100 microns, is good with 10 ~ 20 microns, to meet the trend of slimming encapsulation.A kind of or several arbitrarily combination in the material of metal column I 111 is conduction, heat conductivility is good copper Cu, iron Fe, nickel.The lower surface of metal column I 111 exposes encapsulating material layer I 112, forms the input/output terminal 113 of lower package body, to be connected with the substrate such as PCB.
Encapsulation monomers B 20 comprises chip packing-body and lower package body.Chip packing-body comprises at least one chip II 42 and interconnection metal layer 222 again, and chip II 42 is positioned at the central authorities of whole chip packing-body, then interconnection metal layer 222 is optionally arranged at the surrounding of this chip II 42.Chip II 42 also can be more than one, and its model can be the same or different, and arranges on demand.Chip II 42 adopts reverse installation process to be connected by dimpling block 5 and metal connecting layer 51 upside-down mounting with the nearly die terminals of interconnection metal layer 222 again, formation electric interconnection.The lower surface of interconnection metal layer 222 arranges metal seed layer 221 again, and the thickness of metal seed layer 221 is 0.01 ~ 2 micron.The lower surface of metal seed layer 221 arranges the lower input/output terminal 224 of chip packing-body.Interconnection metal layer 222, chip II 42 and metal seed layer 221 and space filling bag closure material to each other thereof again, forms encapsulating material layer II 228.
Lower package body comprises metal column I 211 and encapsulating material layer I 212, and metal column I 211 is connected with the lower input/output terminal 224 of chip packing-body.The circular in cross-section of metal column I 211 or the polygon such as quadrangle, hexagon, its number and arrangement mode are also determined by actual needs.Encapsulating material layer I 212 encapsulated metal post I 211, and expose the lower surface of metal column I 211, form the input/output terminal 213 of lower package body.Therefore, the upper input/output terminal 125 of the chip packing-body of one end connection encapsulation monomer A 10 of link 8, the input/output terminal 213 of its other end connection encapsulation monomers B 20 lower package body, forms electrical connection.
A kind of 3-D stacks encapsulating structure of the utility model is not limited to above preferred embodiment, and the connected mode of chip and again interconnection metal layer can design according to the model of chip, size, actual needs etc.The encapsulating material of encapsulating material layer I 212, encapsulating material layer II 228, encapsulating material layer I 112, encapsulating material layer II 128 can be identical, also can be different, determines according to actual needs.Therefore; any those skilled in the art are not departing from spirit and scope of the present utility model; the any amendment done above embodiment according to technical spirit of the present utility model, equivalent variations and modification, all fall in protection range that the utility model claim defines.
Claims (10)
1. a 3-D stacks encapsulating structure, it is characterized in that: it encapsulation monomer A (10) comprising encapsulation monomers B (20) and be positioned at several stacked package below encapsulation monomers B (20), be connected by link (8) between described encapsulation monomer A (10) and encapsulation monomers B (20) and between neighbouring two encapsulation monomer A (10)
Described encapsulation monomer A (10) comprises chip packing-body and lower package body, described chip packing-body comprises at least one chip I (41) and interconnection metal layer (122) again, described chip I (41) is positioned at the central authorities of whole chip packing-body, described interconnection metal layer again (122) is optionally arranged at the surrounding of this chip I (41), described chip I (41) is connected by connector I with the nearly die terminals of interconnection metal layer (122) again, the lower surface of described interconnection metal layer again (122) arranges metal seed layer (121), and the lower input/output terminal (124) of chip packing-body is set in the lower surface of described metal seed layer (121),
In described chip I (41) homonymy, the die terminals far away of described interconnection metal layer again (122) arranges metal column II (123), described metal column II (123) and again interconnection metal layer (122) are connected, and the level height of this metal column II (123) is higher than the level height of chip I (41), described interconnection metal layer again (122), metal column II (123), chip I (41), connector I and metal seed layer (121) and space filling bag closure material to each other thereof, form encapsulating material layer II (128), described encapsulating material layer II (128) exposes the upper surface of metal column II (123), form the upper input/output terminal (125) of chip packing-body,
Described lower package body comprises metal column I (111) and encapsulating material layer I (112), described metal column I (111) is connected with the lower input/output terminal (124) of described chip packing-body, described encapsulating material layer I (112) encapsulated metal post I (111), and expose the lower surface of metal column I (111), form the input/output terminal (113) of lower package body;
Encapsulation monomers B (20) comprises chip packing-body and lower package body, described chip packing-body comprises at least one chip II (42) and interconnection metal layer (222) again, described chip II (42) is positioned at the central authorities of whole chip packing-body, described interconnection metal layer again (222) is optionally arranged at the surrounding of this chip II (42), described chip II (42) is connected by connector II with the nearly die terminals of interconnection metal layer (222) again, the lower surface of described interconnection metal layer again (222) arranges metal seed layer (221), and the lower input/output terminal (224) of chip packing-body is set in the lower surface of described metal seed layer (221),
Described interconnection metal layer again (222), chip II (42) and metal seed layer (221) and space filling bag closure material to each other thereof, form encapsulating material layer II (228);
Described lower package body comprises metal column I (211) and encapsulating material layer I (212), described metal column I (211) is connected with the lower input/output terminal (224) of described chip packing-body, described encapsulating material layer I (212) encapsulated metal post I (211), and expose the lower surface of metal column I (211), form the input/output terminal (213) of lower package body.
2. a kind of 3-D stacks encapsulating structure according to claim 1, is characterized in that: described connector I is identical with connector II, is the metal connecting layer on dimpling block and top thereof or is metal lead wire.
3. a kind of 3-D stacks encapsulating structure according to claim 1, it is characterized in that: described connector I is the metal connecting layer on dimpling block and top thereof, connector II is metal lead wire.
4. a kind of 3-D stacks encapsulating structure according to claim 1, is characterized in that: described connector I is metal lead wire, and connector II is the metal connecting layer on dimpling block and top thereof.
5. a kind of 3-D stacks encapsulating structure according to any one of claim 1 to 4, is characterized in that: the circular in cross-section of described metal column I (111,211) and metal column II (123) or polygon.
6. a kind of 3-D stacks encapsulating structure according to claim 5, it is characterized in that: described link (8) is soldered ball or welding block, the upper input/output terminal (125) of the chip packing-body of its one end connection encapsulation monomer A (10), the input/output terminal (213) of its other end connection encapsulation monomers B (20) lower package body.
7. a kind of 3-D stacks encapsulating structure according to claim 5, is characterized in that: the height h1 scope of described metal column I (111,211) is 5 ~ 100 microns.
8. a kind of 3-D stacks encapsulating structure according to claim 7, is characterized in that: the height h1 scope of described metal column I (111,211) is 10 ~ 20 microns is good.
9. a kind of 3-D stacks encapsulating structure according to claim 5, is characterized in that: the scope of the height h2 of described metal column II (123) is at 100 ~ 300 microns.
10. a kind of 3-D stacks encapsulating structure according to any one of claim 1 to 4, is characterized in that: the thickness of described metal seed layer (121,221) is 0.01 ~ 2 micron.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520055824.9U CN204332941U (en) | 2015-01-27 | 2015-01-27 | A kind of 3-D stacks encapsulating structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520055824.9U CN204332941U (en) | 2015-01-27 | 2015-01-27 | A kind of 3-D stacks encapsulating structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204332941U true CN204332941U (en) | 2015-05-13 |
Family
ID=53169266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520055824.9U Active CN204332941U (en) | 2015-01-27 | 2015-01-27 | A kind of 3-D stacks encapsulating structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204332941U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017128567A1 (en) * | 2016-01-26 | 2017-08-03 | 中芯长电半导体（江阴）有限公司 | Double-faced fan-out type wafer level packaging method and packaging structure |
-
2015
- 2015-01-27 CN CN201520055824.9U patent/CN204332941U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017128567A1 (en) * | 2016-01-26 | 2017-08-03 | 中芯长电半导体（江阴）有限公司 | Double-faced fan-out type wafer level packaging method and packaging structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104576579B (en) | A kind of 3-D stacks encapsulating structure and its method for packing | |
| CN104064551B (en) | A kind of chip stack package structure and electronic equipment | |
| US8278746B2 (en) | Semiconductor device packages including connecting elements | |
| US7880310B2 (en) | Direct device attachment on dual-mode wirebond die | |
| CN102593110B (en) | Laminated inverted chip packaging structure of ultra-fine spacing welding plates and bottom filling material preparation method | |
| CN103401438B (en) | Surface-mount bridge rectifier and manufacture method thereof | |
| CN103400823A (en) | Fine spacing laminated packaging structure containing copper pillar and packaging method | |
| CN106711118A (en) | Electronic package and manufacturing method thereof | |
| CN101241904A (en) | Square flat non-connection pin multi-chip encapsulation structure | |
| CN103311207A (en) | Stacked package structure | |
| CN206179848U (en) | PoP stacked package structure | |
| KR20070048952A (en) | Multi chip package having interconnectors | |
| CN204332941U (en) | A kind of 3-D stacks encapsulating structure | |
| CN104134641A (en) | Semiconductor package and fabrication method thereof | |
| CN204927275U (en) | Packaging structure of low -cost silica -based module | |
| KR20100066821A (en) | Package on package and the manufacturing method therof | |
| CN211295098U (en) | Packaging structure | |
| CN206789535U (en) | A kind of fan-out package structure of power electronic devices | |
| CN207624678U (en) | A kind of three-dimensional POP encapsulating structures | |
| CN110634832A (en) | Packaging structure based on through silicon via adapter plate and manufacturing method thereof | |
| CN205881899U (en) | Multichannel stacked package structure | |
| CN204464266U (en) | A kind of POP Stacked die package structure of little sphere gap | |
| CN218482223U (en) | Semiconductor packaging structure | |
| CN204927277U (en) | Packaging structure of silica -based module | |
| CN203733774U (en) | Semiconductor package-on-package packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |