KR20070048952A - Multi chip package having interconnectors - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip package having internal connection terminals. In the case of connecting the semiconductor chips using bonding wires, the present invention is expensive between the stacked semiconductor chip and the stacked semiconductor chip having the same or larger size than the stacked semiconductor chip. Since the spacers must be interposed, the multi-chip package can be implemented only when the stacked semiconductor chip is larger than the stacked semiconductor chip in order to reduce manufacturing costs. In addition, when via holes are formed in the semiconductor chip and then the semiconductor chips are stacked, the manufacturing process is complicated and the multi-chip package may be implemented only when the semiconductor chips have the same size. In order to solve this problem, the present invention uses a plurality of internal connection terminals extending from the chip pads of the semiconductor chip to connect the semiconductor chips, and using a plating film formed on the connection portions of the chip pad and the internal connection terminals, respectively. A multichip package having an internal connection terminal for electrically connecting chips is provided. According to the present invention, since the internal connection terminals are easily applicable to semiconductor chips of any size, the multi-chip package can be implemented by stacking regardless of the size of the semiconductor chips, and the semiconductor chips using the internal connection terminals formed separately. By connecting them, the manufacturing process can be simplified.

 Semiconductor chip, chip pad, internal connection terminal, first plating film, second plating film

Description

Multi-chip package with internal connection terminal {MULTI CHIP PACKAGE HAVING INTERCONNECTORS}

1 is a cross-sectional view showing a multi-chip package according to the prior art.

2 is a cross-sectional view showing another multi-chip package according to the prior art.

3 is a cross-sectional view illustrating a multichip package according to a first embodiment of the present invention.

4 is an enlarged view illustrating portion “A” of FIG. 3.

5 is a cross-sectional view illustrating a multichip package according to a second exemplary embodiment of the present invention.

6 is a cross-sectional view illustrating a multichip package according to a third exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

120, 130, 140, 220, 230, 240, 320, 330, 340: semiconductor chip

122, 132, 142, 222, 232, 242, 322, 332, 342: chip pad

152, 252, 352a, 352b: internal connection terminals

154, 254, 354 plating film

155, 255, 355: first plating film

157, 257, 357a, and 357b: second plating film

200, 300, 400: Multichip Package

The present invention relates to a semiconductor package, and more particularly to a multi-chip package having an internal connection terminal for vertically connecting a plurality of semiconductor chips.

Recently, as the size of an electronic portable device has become smaller, the semiconductor package mounted in the electronic portable device has also become smaller, thinner, and lighter. On the other hand, the capacity of the semiconductor chip mounted in the semiconductor package is increasing. Accordingly, in the past, a single chip package in which a semiconductor chip having one function is mounted has been manufactured, but recently, a multi chip package in which two or more semiconductor chips are mounted in one package; MCP) is being manufactured.

Multi-chip package technology is a semiconductor packaging technology that can be reduced in size by mounting two or more semiconductor chips on a wiring board into a single package, and is a hybrid type in which the same type of semiconductor chips are mounted or different types of semiconductor chips are mounted. The technology is developing in various directions such as hybrid type. In this case, the semiconductor chips may be mounted on the wiring board in a planar manner or vertically. The semiconductor chips are stacked vertically in accordance with the demand for miniaturization, thinning, and weight reduction of the semiconductor package.

As shown in FIG. 1, the multi-chip package 100a according to the related art is implemented in a structure in which a plurality of semiconductor chips 20, 30, and 40 having different sizes are stacked on an upper surface of the wiring board 10. The wiring board 10 and the semiconductor chips 20, 30, and 40 are electrically connected by a bonding wire 50. The semiconductor chips 20, 30, and 40 and the bonding wires 50 stacked on the upper surface of the wiring board 10 are protected from the external environment by the resin encapsulation unit 80 formed by being collectively molded through a molding process. Solder balls 60 are formed on the lower surface of the wiring board 10.

In this case, when the size of the stacked semiconductor chip is the same as or larger than that of the stacked semiconductor chip, the bonding wires drawn from the stacked semiconductor chip may come into contact with the lower surface of the stacked semiconductor chip to generate an electrical short.

As a result, the bonding wire 50 drawn from the stacked semiconductor chip 30 via the spacer 70 between the upper and lower semiconductor chips 30 and 40 is mechanically connected to the lower surface of the stacked semiconductor chip 40. Prevent contact Of course, the spacer 70 is formed to have a thickness such that the bonding wire 50 drawn from the stacked semiconductor chip 30 does not come into contact with the bottom surface of the stacked semiconductor chip 40.

By the way, since the chip attach film used as a spacer is expensive, high cost is required in manufacturing a multichip package using a spacer.

Meanwhile, another multi-chip package 100b according to the related art is implemented in a structure in which a plurality of semiconductor chips 20, 30, and 40 having via holes 90 are formed as shown in FIG. 2. do. The via hole 90 penetrates the semiconductor chips 20, 30, and 40 to connect the active and inactive surfaces of the semiconductor chips 20, 30, and 40. Solder balls 95 are formed at one end of the via hole 90 on the non-active surface. The solder balls 95 of the stacked semiconductor chip are attached to the other end of the via hole 90 of the active surface of the stacked semiconductor chip, thereby electrically connecting the semiconductor chips 20, 30, and 40.

However, the multi-chip package 10b according to the related art has a complicated manufacturing process because the via holes 90 must be formed in the semiconductor chips 20, 30, and 40. In addition, since the via hole 90 of the stacked semiconductor chip and the via hole 90 of the stacked semiconductor chip are to be formed at the same position of each of the semiconductor chips 20, 30, and 40, the semiconductor chips 20 having the same size may be used. , 30, 40) is applicable only when laminating.

Accordingly, an object of the present invention is to provide a multi-chip package having a simple manufacturing process and having internal connection terminals capable of stacking a plurality of semiconductor chips regardless of the size of the semiconductor chip.

In order to achieve the above object, the present invention provides a plurality of semiconductor chips in which a plurality of chip pads are formed along an edge region of one surface, a plurality of internal connection terminals electrically connected to each other by electrically connecting the semiconductor chips, and a chip pad and an internal portion. A plating film formed on each of the connection portions of the connection terminals, wherein the plating film includes a first plating film formed on the upper surface of the chip pad, a portion connected to the first plating film of the internal connection terminal, and a vertically neighboring interior. It provides a multi-chip package having an internal connection terminal comprising a second plating film formed on a portion connected to the connection terminal.

In the multi-chip package according to the present invention, the internal connection terminals extend from the chip pads along the sidewalls of the semiconductor chip and are exposed toward the other surface of the semiconductor chip.

In the multi-chip package according to the present invention, the form of the internal connection terminal is preferably any one of the "a, b, c or S" shape.

In the multi-chip package according to the present invention, it is preferable that the internal connection terminal is either copper (Cu) or an alloy.

In the multi-chip package according to the present invention, the first and the second plating film is any one of gold (Au), silver (Ag), tin (Sn), tin-lead (SnPb) alloy or tin-bismuth (SnBi) alloy. Is preferably.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3 is a cross-sectional view illustrating a multichip package according to a first embodiment of the present invention. 4 is an enlarged view illustrating portion “A” of FIG. 3.

3 and 4, in the multi-chip package 200 according to the first embodiment, a plurality of semiconductor chips 120, 130, and 140 are stacked in three dimensions, and the semiconductor chips 120, 130, and 140 are stacked. It has a structure connected by this internal connection terminal 152.

Referring to the multi-chip package 200 according to the first embodiment of the present invention in detail, the multi-chip package 200 is a semiconductor chip 120, 130, 140, the internal connection terminal 152 and the plating film 154 ).

A plurality of chip pads 122, 132, and 142 are formed on the upper surface of the semiconductor chips 120, 130, and 140 along the edge area. The chip pads 122, 132, and 142 are generally made of aluminum (Al). In this case, the semiconductor chips 120, 130, and 140 are all the same in size, and the number and arrangement intervals of the chip pads 122, 132, and 142 are also the same.

The internal connection terminal 152 connects the semiconductor chips 120, 130, and 140. The internal connection terminals 152 extend from the respective chip pads 122, 132, and 142 on the upper surfaces of the semiconductor chips 120, 130, and 140 along the sidewalls of the semiconductor chips 120, 130, and 140, respectively. 130, 140 are exposed toward the bottom surface. The ends of the internal connection terminals 152 exposed toward the bottom surface of the semiconductor chips 120, 130, and 140 are connected to the internal connection terminals 152 at corresponding positions of the vertically neighboring semiconductor chips 120, 130, and 140. Connected. The internal connection terminal 152 has a shape of "a" shape.

In this case, since the internal connection terminal 152 is used as a path for connecting and electrically connecting the semiconductor chips 120, 130, and 140, a material having excellent electrical conductivity, for example, copper (Cu) or an alloy, may be used. It is preferable that it is formed by either.

The plating film 154 is formed by plating the connection portions of the semiconductor chips 120, 130, and 140 and the internal connection terminals 152, respectively. The plating film 154 includes a first plating film 155 and a second plating film 157 classified according to the formation position. The first plating layer 155 is formed on the top surface of the chip pads 122, 132, and 142 of the semiconductor chips 120, 130, and 140. In addition, the second plating film 157 is a portion connected to the first plating film 155 of the internal connection terminal 152 and a portion connected to another internal connection terminal 152 which is adjacent to each other vertically, for example, a semiconductor of the upper portion. It is formed in the part connected with the internal connection terminal extended from the chip and the internal connection terminal extended from the lower semiconductor chip.

The plating layer 154 is bonded to each other by thermal compression or reflow to connect the chip pads 122, 132, and 142 to the internal connection terminals 152.

In this case, since the plating film 154 is used to improve the bonding force between the chip pads 122, 132, and 142 and the internal connection terminals 152, the plating film 154 has a lower melting point than the internal connection terminals 152. It is preferably formed of any one of a metal having, for example, gold (Au), silver (Ag), tin (Sn), tin-lead (SnPb) alloy or tin-bismuth (SnBi) alloy.

Meanwhile, the internal connection terminal 152 extending from the chip pad 122 of the lowermost semiconductor chip 120 is connected to a mother board (not shown) through soldering. Accordingly, the ends of the internal connection terminals 152 exposed toward the bottom surface of the lowermost semiconductor chip 120 are connected to the mother substrate, thereby electrically connecting the semiconductor chips 120, 130, and 140 to the mother substrate.

Meanwhile, in the above-described embodiment, only the multi-chip package having an "a" shaped internal connection terminal is disclosed, but the multi-chip package of the present invention can be implemented by using various types of internal connection terminals. 5 is an example, and FIG. 5 is a cross-sectional view illustrating a multi-chip package according to a second embodiment of the present invention.

Referring to FIG. 5, the basic structure of the multichip package 300 is the same as the multichip package 200 of the above-described embodiment. However, in the multi-chip package 300 of the present exemplary embodiment, chip pads 222, 232, and 242 are formed on the lower surfaces of the semiconductor chips 220, 230, and 240, and the “b” shaped internal connection terminals 252 are provided. The semiconductor chips 220, 230, and 240 are connected to each other.

That is, according to the second embodiment of the present invention, the semiconductor chips 220, 230, and 240 have a structure in which a plurality of chip pads 222, 232, and 242 are formed along an edge area of the lower surface. This may be implemented when the semiconductor chip having the chip pads formed on the upper surface thereof is rotated such that the upper surface thereof faces downward. In this case, the internal connection terminals 252 extend from the respective chip pads 222, 232, 242 on the bottom surfaces of the semiconductor chips 220, 230, 240 along the sidewalls of the semiconductor chips 220, 230, 240, thereby semiconductors. It is exposed toward the top surface of the chips 220, 230, 240. An end portion of the internal connection terminal 252 exposed toward the upper surface of the semiconductor chip 220, 230, 240 may be connected to the internal connection terminal 252 at a corresponding position of the vertically neighboring semiconductor chip 220, 230, 240. The plating film 254 is connected via a medium. The internal connection terminal 252 has a shape of "b" shape.

In addition, the multi-chip package of the present invention may be implemented by using an internal connection terminal having a "c or S" shape in addition to the "a or b" shaped internal connection terminals of the above-described embodiments.

Meanwhile, in the above-described embodiment, only the multi-chip package in which semiconductor chips of the same size are stacked is disclosed. However, the multi-chip package of the present invention may be implemented by stacking semiconductor chips having different sizes. 6 is an example, and FIG. 6 is a cross-sectional view illustrating a multichip package according to a third exemplary embodiment of the present invention.

Referring to FIG. 6, the basic structure of the multi chip package 400 is the same as the multi chip package of the above-described embodiments. However, the multichip package 400 according to the present exemplary embodiment has a structure in which the semiconductor chips 320, 330, and 340 are connected by various types of internal connection terminals 352a and 352b.

That is, according to the third embodiment of the present invention, the semiconductor chips 320, 330, and 340 have different sizes. The size of the stacked semiconductor chip 340 may be larger than that of the stacked semiconductor chip 330, or the size of the stacked semiconductor chip 330 may be smaller than that of the stacked semiconductor chip 320. In this case, by connecting the semiconductor chips 320, 330, 340 by using the internal connection terminals 352a, 352b having any one of the shape of "a, b, c or S", the multi-chip package of the present invention 400 may be implemented. In addition, two or more internal connection terminals 352a and 352b having different shapes may be used in one multi-chip package 400.

For example, an internal connection terminal 352a having a 'c' shape is connected to the lowermost semiconductor chip 320, and an internal connection having an 's' shape is connected to the intermediate semiconductor chip 330 having a smaller size than the lowermost semiconductor chip 320. By connecting the terminals 352b, two semiconductor chips 320 and 330 having a smaller size than the stacked semiconductor chip 320 may be stacked. In addition, the uppermost semiconductor chip 340 having a larger size than the intermediate semiconductor chip 330 is connected to an internal connection terminal 352a having a “c” shape, so that the size of the stacked semiconductor chip 340 is increased. Two semiconductor chips 330 and 340 larger than the 330 may be stacked.

Meanwhile, although the above-described embodiments disclose a multi-chip package having a structure in which three semiconductor chips are stacked, two or more semiconductor chips may be stacked to implement the multi-chip package of the present invention.

Therefore, according to the structure of the present invention, it is possible to easily apply to any size semiconductor chip by connecting the semiconductor chips using the internal connection terminal having any one of the form "a, b, c or S" shape. Therefore, the multi-chip package may be implemented by stacking a plurality of semiconductor chips regardless of the size of the semiconductor chips.

In addition, by connecting the inner connection terminals formed separately to the chip pad of the semiconductor chip, by connecting the inner connection terminals extending from the respective semiconductor chips to the vertical neighboring inner connection terminals, by stacking a plurality of semiconductor chips vertically In addition, the multi-chip package according to the present invention may be manufactured according to a simple manufacturing process as compared with the manufacturing process of the multi-chip package according to the prior art in which a via hole is formed in a semiconductor chip and then the semiconductor chips are stacked.

Claims (5)

A plurality of semiconductor chips in which a plurality of chip pads are formed along an edge region of one surface; A plurality of internal connection terminals electrically connecting the semiconductor chips and connected to each other; And A plating film formed on each of the connection portions of the chip pad and the internal connection terminals; The plating film, A first plating film formed on an upper surface of the chip pad; And And a second plating film formed on a portion of the internal connection terminal connected to the first plating film and a portion of the internal connection terminal connected to the vertically neighboring internal connection terminal. . The method of claim 1, And the internal connection terminal extends along the sidewall of the semiconductor chip from the chip pad to be exposed toward the other surface of the semiconductor chip. The method of claim 2, The form of the internal connection terminal is a multi-chip package having an internal connection terminal, characterized in that any one of the "b, b, c or S" shape. The method of claim 1, The internal connection terminal is a multi-chip package having an internal connection terminal, characterized in that any one of copper (Cu) or alloy (alloy). The method of claim 1, The first and second plating layers may be any one of gold (Au), silver (Ag), tin (Sn), tin-lead (SnPb) alloys, or tin-bismuth (SnBi) alloys. Having a multi-chip package.

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