CN104134641A - Semiconductor package and fabrication method thereof - Google Patents

Semiconductor package and fabrication method thereof Download PDF

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Publication number
CN104134641A
CN104134641A CN201310174210.8A CN201310174210A CN104134641A CN 104134641 A CN104134641 A CN 104134641A CN 201310174210 A CN201310174210 A CN 201310174210A CN 104134641 A CN104134641 A CN 104134641A
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CN
China
Prior art keywords
semiconductor package
layer
line layer
packing colloid
making
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201310174210.8A
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Chinese (zh)
Inventor
张翊峰
王隆源
蔡芳霖
刘正仁
陈宏棋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
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Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN104134641A publication Critical patent/CN104134641A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor package and a method for fabricating the same, the semiconductor package comprising: the first packaging colloid is provided with a first surface and a second surface which are opposite; a plurality of conductors formed in the first encapsulant and having first and second connection portions respectively exposed on the first and second surfaces; a plurality of connecting pads formed in the first packaging colloid and exposed out of the second surface of the first packaging colloid; a chip embedded in the first packaging adhesive and arranged on the connecting pad; and a first circuit layer formed on the first surface of the first encapsulant and electrically connected to the first connection portion of the conductor. Therefore, the thickness of the semiconductor packaging piece can be reduced, so that the size of the semiconductor packaging piece is reduced.

Description

Semiconductor package part and method for making thereof
Technical field
The present invention relates to a kind of semiconductor package part and method for making thereof, refer to especially a kind of semiconductor package part and the method for making thereof of chip in packing colloid that be embedded into.
Background technology
Along with semiconductor technology make rapid progress and electronic product towards the trend of slimming, size or the volume of semiconductor package part also constantly dwindle thereupon, use and make this semiconductor package part reach compact object.
Figure 1A is the cross-sectional schematic that illustrates semiconductor package part 1 in No. 201208021 TaiWan, China patent of prior art.As shown in the figure, semiconductor package part 1 comprises: hard plate 10, a plurality of the first soldered ball 11, chip 12, coating layer 13, dielectric layer 14, tertiary circuit layer 153, first are refused layer 161, second and refused layer 162 and a plurality of the second soldered ball 171.
This hard plate 10 has relative first surface 10a and second surface 10b, is formed with respectively the first line layer 151 and the second line layer 152 on this first surface 10a and second surface 10b.This first line layer 151 is electrically connected this second line layer 152, and has a plurality of connection gaskets 154, and this first soldered ball 11 is arranged on this connection gasket 154.
This chip 12 is arranged on the first surface 10a of this hard plate 10, and has acting surface 121 and non-acting surface 122.This acting surface 121 is provided with a plurality of electronic padses 123, and connects on the first surface 10a that is placed in this hard plate 10 with this non-acting surface 122.
This coating layer 13 is formed on the first surface 10a of this hard plate 10, for being coated this first soldered ball 11 and this chip 12, and exposes outside the acting surface 121 of this first soldered ball 11 and chip 12.This dielectric layer 14 is formed on this coating layer 13, and has a plurality of perforates to expose outside the electronic pads 123 on the acting surface 121 of this first soldered ball 11 and this chip 12.
This tertiary circuit layer 153 is formed on this dielectric layer 14 to be electrically connected this first soldered ball 11 and this electronic pads 123.This first is refused layer 161 and is formed on this dielectric layer 14 and tertiary circuit layer 153, and this tertiary circuit layer 153 of exposed parts.This second is refused on second surface 10b and the second line layer 152 that layer 162 is formed at this hard plate 10, and exposes outside this second line layer 152 of part.
Figure 1B is for illustrating the cross-sectional schematic of another semiconductor package part 1' in No. 201208021 TaiWan, China patent of prior art according to Figure 1A.As shown in the figure, semiconductor package part 1', except comprising the semiconductor package part 1 of Figure 1A, also comprises semiconductor device 18 and a plurality of the 3rd soldered ball 172.This semiconductor device 18 can be semiconductor package, and it is connect and be placed in this and first refuse tertiary circuit layer 153, the three soldered ball 172 that layer 161 exposes and connect and be placed in this and second refuse on the second line layer 152 that layer 162 exposes by this second soldered ball 171.
The shortcoming of above-mentioned semiconductor package part, is the chip being coated in coating layer to be arranged on hard plate, makes the integral thickness of this semiconductor package part thicker, causes that the size of this semiconductor package part or volume are large, material cost is also higher.
Therefore, how to overcome the problem of above-mentioned prior art, become in fact the problem of desiring most ardently at present solution.
Summary of the invention
In view of the disadvantages of above-mentioned prior art, main purpose of the present invention is to provide a kind of semiconductor package part and method for making thereof, to reduce the thickness of semiconductor package part, and dwindles the size of this semiconductor package part.
Semiconductor package part of the present invention, it comprises: the first packing colloid, it has relative first surface and second surface; A plurality of electric conductors, it is formed in this first packing colloid, and has the first connecting portion and the second connecting portion that exposes to respectively this first surface and this second surface; A plurality of connection gaskets, it is formed in this first packing colloid, and exposes to the second surface of this first packing colloid; Chip, it is embedded in this first packing colloid, and is arranged on this connection gasket; And first line layer, it is formed on the first surface of this first packing colloid, and is electrically connected the first connecting portion of this electric conductor.
This semiconductor package part can comprise: surface-treated layer, it is formed on this first line layer.
This semiconductor package part can comprise: first refuses layer, and it is formed on this first line layer, and exposes outside this first line layer of part; Electronic building brick and a plurality of conductive component, this electronic building brick is arranged at this and first refuses on layer, and is electrically connected this first line layer by this conductive component; And second packing colloid, it is formed at this first packing colloid top, and coated this first line layer, first is refused layer, electronic building brick and conductive component.
This semiconductor package part can comprise: the second line layer, and it is formed on the second surface of this first packing colloid, and is electrically connected the second connecting portion and this connection gasket of this electric conductor; Second refuses layer, and it is formed on this second line layer, and exposes outside this second line layer of part; Electronic building brick and a plurality of conductive component, this electronic building brick is arranged at this and second refuses on layer, and is electrically connected this second line layer by this conductive component; And second packing colloid, it is formed at this first packing colloid top, and coated this second line layer, second is refused layer, electronic building brick and conductive component.
The present invention also provides a kind of method for making of semiconductor package part, and it comprises: the bearing part with metal level is provided; Form a plurality of connection gaskets and a plurality of electric conductor higher than this connection gasket on this metal level; Chip is set on this connection gasket; Form the first packing colloid on this metal level, to be coated this connection gasket, electric conductor and chip, and expose outside the connecting portion of this electric conductor; And form the first line layer on this first packing colloid to be electrically connected the connecting portion of this electric conductor.
The step that forms this connection gasket can comprise: form and have a plurality of first first resistance layer of boring a hole on this metal level, this first perforating exposed goes out this metal level of part; Forming this connection is padded in this first perforation to connect this metal level; And remove this first resistance layer.
The step that forms this electric conductor can comprise: form and have a plurality of biperforate the second resistance layers on this metal level, this second perforation is higher than this connection gasket and expose outside this metal level of part; Form this electric conductor in this second perforation in to connect this metal level; And remove this second resistance layer.
The method for making of this semiconductor package part can comprise: form surface-treated layer on this first line layer.
The method for making of this semiconductor package part can comprise: form first and refuse layer on this first line layer and expose outside this first line layer of part; Electronic building brick is set and in this, first refuses on layer, and be electrically connected this first line layer by a plurality of conductive components; And form the second packing colloid in this first packing colloid top, to be coated this first line layer, first, refuse layer, electronic building brick and conductive component.
The method for making of this semiconductor package part can comprise: remove this bearing part; This metal level of patterning is to form the second line layer; Forming second refuses layer on this second line layer and exposes outside this second line layer of part; Electronic building brick is set and in this, second refuses on layer, and be electrically connected this second line layer by a plurality of conductive components; And form the second packing colloid in this first packing colloid top, to be coated this second line layer, second, refuse layer, electronic building brick and conductive component.
Above-mentioned electronic building brick can be semiconductor chip or semiconductor package.
As from the foregoing, semiconductor package part of the present invention and method for making thereof, mainly electric conductor and connection gasket are formed at respectively in packing colloid, and by chip embedding bury in this packing colloid to be arranged on this connection gasket, and the connecting portion of this electric conductor is exposed to the surface of this packing colloid, then line layer is formed on the surface of this packing colloid to be electrically connected the connecting portion of this electric conductor.Thus, the present invention can reduce the thickness of this semiconductor package part, to dwindle size or the volume of this semiconductor package part, and then reduces the material cost of this semiconductor package part.
Accompanying drawing explanation
Figure 1A is the cross-sectional schematic that illustrates semiconductor package part in No. 201208021 TaiWan, China patent of prior art;
Figure 1B is for illustrating the cross-sectional schematic of another semiconductor package part in No. 201208021 TaiWan, China patent of prior art according to Figure 1A;
Fig. 2 A to Fig. 2 O is the cross-sectional schematic that illustrates the first embodiment of semiconductor package part of the present invention and method for making thereof, and wherein, Fig. 2 K' is another embodiment of Fig. 2 K;
Fig. 3 is for illustrating the cross-sectional schematic of the second embodiment of semiconductor package part of the present invention according to Fig. 2 O;
Fig. 4 is for illustrating the cross-sectional schematic of the 3rd embodiment of semiconductor package part of the present invention according to Fig. 2 O;
Fig. 5 is for illustrating the cross-sectional schematic of the 4th embodiment of semiconductor package part of the present invention according to Fig. 2 O; And
Fig. 6 is for illustrating the cross-sectional schematic of the 5th embodiment of semiconductor package part of the present invention according to Fig. 2 O.
Symbol description
1,1' semiconductor package part
10 hard plates
10a first surface
10b second surface
11 first soldered balls
12 chips
121 acting surfaces
122 non-acting surfaces
123 electronic padses
13 coating layers
14 dielectric layers
151 first line layers
152 second line layers
153 tertiary circuit layers
154 connection gaskets
161 first refuse layer
162 second refuse layer
171 second soldered balls
172 the 3rd soldered balls
18 semiconductor devices
2,3,4,5,6 semiconductor package parts
20 bearing parts
201 metal levels
21 first resistance layers
211 first perforation
212 connection gaskets
22 second resistance layers
221 second perforation
222 electric conductors
223 first connecting portions
224 second connecting portions
23 chips
24 first packing colloids
241 first surfaces
242 second surfaces
25 first line layers
251 first openings
26 surface-treated layers
27 first refuse layer
271 second openings
28 second line layers
281 the 3rd openings
29 second refuse layer
291 the 4th openings
30,301 electronic building bricks
31,311 bonding wires
32 second packing colloids
33 soldered balls
34 conductive components.
Embodiment
By particular specific embodiment, embodiments of the present invention are described below, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.
Notice, appended graphic the illustrated structure of this specification, ratio, size etc., equal contents for coordinating specification to disclose only, understanding and reading for those skilled in the art, be not intended to limit the enforceable qualifications of the present invention, so technical essential meaning of tool not, the adjustment of the modification of any structure, the change of proportionate relationship or size, not affecting under the effect that the present invention can produce and the object that can reach, all should still drop on disclosed technology contents and obtain in the scope that can contain.
Simultaneously, in this specification, quote as " on ", the term such as " ", " first ", " second ", " surface " and " connecting portion ", also only for ease of understanding of narrating, but not for limiting the enforceable scope of the present invention, the change of its relativeness or adjustment, under without essence change technology contents, when being also considered as the enforceable category of the present invention.
Fig. 2 A to Fig. 2 O is the cross-sectional schematic that illustrates the first embodiment of semiconductor package part of the present invention and method for making thereof, and wherein, Fig. 2 K' is another embodiment of Fig. 2 K.
As shown in Figure 2 A, provide the bearing part 20 with metal level 201.
As shown in Figure 2 B, formation has the first resistance layer 21 of a plurality of the first perforation 211 on this metal level 201, and this first perforation 211 exposes outside this metal level 201 of part.
As shown in Figure 2 C, form this connection gasket 212 in this first perforation 211 in to connect this metal level 201.
As shown in Figure 2 D, remove this first resistance layer 21, to expose outside this connection gasket 212.
As shown in Figure 2 E, form there are a plurality of the second perforation 221 the second resistance layer 22 on this metal level 201, the height of this second perforation 221 is higher than the height of this connection gasket 212 and expose outside this metal level 201 of part.
As shown in Figure 2 F, forming the electric conductor 222 with the first connecting portion 223 and the second connecting portion 224 second bores a hole in 221 to be connected this metal level 201 in this.This electric conductor 222 can be metal column, projection, soldered ball or stitch (pin) etc.
As shown in Figure 2 G, remove this second resistance layer 22, to expose outside this connection gasket 212 and this electric conductor 222.
As shown in Fig. 2 H, chip 23 is set on this connection gasket 212.
As shown in Fig. 2 I, form the first packing colloid 24 on this metal level 201, to be coated this connection gasket 212, electric conductor 222 and chip 23.
As shown in Fig. 2 J, the thickness of this first packing colloid 24 of thinning, to expose outside the first connecting portion 223 of this electric conductor 222.This first packing colloid 24 has the relative first surface 241 and second surface 242 that exposes outside respectively this first connecting portion 223 and this second connecting portion 224.
As shown in Fig. 2 K, by modes such as electroless-platings (electroless plating), form the first line layer 25 on this first packing colloid 24, to be electrically connected the first connecting portion 223 of this electric conductor 222.This first line layer 25 has a plurality of the first openings 251 this first packing colloid 24 of exposed portions serve in addition.
In addition,, in another embodiment as shown in Fig. 2 K', also can form surface-treated layer 26 on the first line layer 25 of Fig. 2 K and expose outside this first opening 251.This surface-treated layer 26 can by nickel, palladium, gold (Ni/Pd/Au) formed the alloy of group or multiple layer metal wherein one formed.
As shown in Fig. 2 L, formation has first of a plurality of the second openings 271 and refuses layer 27 (or insulating barrier) on the first line layer 25 and the first opening 251 of Fig. 2 K, and this second opening 271 exposes outside this first line layer 25 of part.But in other embodiments, also can first form this and first refuse layer 27 on the surface-treated layer 26 of Fig. 2 K', make this second opening 271 expose outside this surface-treated layer 26 (not illustrating in figure) of part.
As shown in Fig. 2 M, remove this bearing part 20, to expose outside this metal level 201.
As shown in Fig. 2 N, this metal level 201 of patterning has a plurality of the 3rd openings 281 the second line layer 28, the three openings 281 to form expose outside the partly second surface 242 of this first packing colloid 24.
As shown in Figure 2 O, formation has second of a plurality of the 4th openings 291 and refuses layer 29 (or insulating barrier) on this second line layer 28 and the 3rd opening 281, and the 4th opening 291 exposes outside this second line layer 28 of part.
The present invention separately provides a kind of semiconductor package part 2, as shown in Figure 2 O.This semiconductor package part 2 comprises the first packing colloid 24, a plurality of electric conductor 222, a plurality of connection gasket 212, chip 23 and the first line layer 25.
This first packing colloid 24 has relative first surface 241 and second surface 242.This electric conductor 222 is formed in this first packing colloid 24, and has the first connecting portion 223 and the second connecting portion 224 that exposes to respectively this first surface 241 and this second surface 242.This connection gasket 212 is formed in this first packing colloid 24, and exposes to the second surface 242 of this first packing colloid 24.This chip 23 is embedded in this first packing colloid 24, and is arranged on this connection gasket 212.
This first line layer 25 is formed on the first surface 241 of this first packing colloid 24, and be electrically connected the first connecting portion 223 of this electric conductor 222, and this first line layer 25 has the first surface 241 of this first packing colloid 24 of exposed portions serve beyond a plurality of the first openings 251.
This semiconductor package part 2 can comprise that having first of a plurality of the second openings 271 refuses layer 27, is formed on this first line layer 25 and this first opening 251, and this second opening 271 exposes outside this first line layer 25 of part.
This semiconductor package part 2 can comprise second line layer 28 with a plurality of the 3rd openings 281, be formed on the second surface 242 of this first packing colloid 24, and the second connecting portion 224 that is electrically connected this electric conductor 222 exposes outside the partly second surface 242 of this first packing colloid 24 with these connection gasket 212, the three openings 281.
This semiconductor package part 2 can comprise that having second of a plurality of the 4th openings 291 refuses layer 29, and it is formed on this second line layer 28 and the 3rd opening 281, and the 4th opening 291 exposes outside this second line layer 28 of part.
In addition, as shown in Fig. 2 K', this semiconductor package part 2 also can comprise surface-treated layer 26, it is formed on this first line layer 25, and expose outside the first opening 251 of this first line layer 25, and first refusing layer 27 and also can first be formed on this surface-treated layer 26 of Fig. 2 L makes this second opening 271 expose outside this surface-treated layer 26 (not illustrating in figure) of part.
Fig. 3 is for illustrating the cross-sectional schematic of the second embodiment of semiconductor package part of the present invention according to Fig. 2 O.As shown in the figure, semiconductor package part 3, except comprising the semiconductor package part 2 of Fig. 2 O, also comprises electronic building brick 30, electronic building brick 301, a plurality of bonding wire 31, a plurality of bonding wire 311, the second packing colloid 32 and a plurality of soldered ball 33.
This electronic building brick 30 all can be chip with this electronic building brick 301, and is sequentially arranged at this and second refuses on layer 29.This electronic building brick 30 is electrically connected by this bonding wire 31 the second line layer 28 that the 4th opening 291 exposes, and this electronic building brick 301 is electrically connected this electronic building brick 30 by this bonding wire 311.
This second packing colloid 32 is formed at this first packing colloid 24 tops, and coated this second line layer 28, second is refused layer 29, electronic building brick 30, electronic building brick 301, bonding wire 31 and bonding wire 311.This soldered ball 33 connects and is placed on the first line layer 25 that this second opening 271 exposes.
The method for making of above-mentioned semiconductor package part 3, except comprising the method for making of Fig. 2 A to Fig. 2 O, also comprise that this electronic building brick 30 and this electronic building brick 301 are sequentially set second to be refused on layer 29 in this, and the second line layer 28 exposing by this this electronic building brick 30 of bonding wire 31 electric connections and the 4th opening 291, and be electrically connected this electronic building brick 301 and this electronic building brick 30 by this bonding wire 311, form again this second packing colloid 32 in these the first packing colloid 24 tops, to be coated this second line layer 28, second refuses layer 29, electronic building brick 30 and electronic building brick 301, separately connect and put on the first line layer 25 that this soldered ball 33 exposes in this second opening 271.
Fig. 4 is for illustrating the cross-sectional schematic of the 3rd embodiment of semiconductor package part of the present invention according to Fig. 2 O.As shown in the figure, semiconductor package part 4, except comprising the semiconductor package part 2 of Fig. 2 O, also comprises electronic building brick 30, a plurality of soldered ball 33 and a plurality of conductive component 34.
This electronic building brick 30 can be semiconductor chip or semiconductor package, and it is arranged at this and second refuses on layer 29, and is electrically connected by this conductive component 34 the second line layer 28 that the 4th openings 291 expose.This soldered ball 33 connects and is placed on the first line layer 25 that this second opening 271 exposes.This conductive component 34 can be soldered ball or projection etc.
The method for making of above-mentioned semiconductor package part 4, except comprising the method for making of Fig. 2 A to Fig. 2 O, also comprise that this electronic building brick 30 is set second to be refused on layer 29 in this, and be electrically connected this electronic building brick 30 and the second line layer 28 that the 4th opening 291 exposes by this conductive component 34, separately connect and put on the first line layer 25 that this soldered ball 33 exposes in this second opening 271.
Fig. 5 is for illustrating the cross-sectional schematic of the 4th embodiment of semiconductor package part of the present invention according to Fig. 2 O.As shown in the figure, semiconductor package part 5, except comprising the semiconductor package part 2 of Fig. 2 O, also comprises electronic building brick 30, a plurality of conductive component 34, the second packing colloid 32 and a plurality of soldered ball 33.
This electronic building brick 30 can be semiconductor chip or semiconductor package, and it is arranged at this and second refuses on layer 29, and is electrically connected by this conductive component 34 the second line layer 28 that the 4th openings 291 expose.This conductive component 34 can be soldered ball or projection etc.This second packing colloid 32 is formed at this first packing colloid 24 tops, and coated this second line layer 28, second is refused layer 29, electronic building brick 30 and conductive component 34.This soldered ball 33 connects and is placed on the first line layer 25 that this second opening 271 exposes.
The method for making of above-mentioned semiconductor package part 5, except comprising the method for making of Fig. 2 A to Fig. 2 O, also comprise that this electronic building brick 30 is set second to be refused on layer 29 in this, and the second line layer 28 exposing by this this electronic building brick 30 of conductive component 34 electric connections and the 4th opening 291, form again this second packing colloid 32 in these the first packing colloid 24 tops, to be coated this second line layer 28, second, refuse layer 29 and electronic building brick 30, separately connect and put on the first line layer 25 that this soldered ball 33 exposes in this second opening 271.
Fig. 6 is for illustrating the cross-sectional schematic of the 5th embodiment of semiconductor package part of the present invention according to Fig. 2 O.As shown in the figure, semiconductor package part 6 is except comprising the semiconductor package part 2 of Figure 20 and by its turned upside down, also comprising electronic building brick 30, a plurality of conductive component 34, the second packing colloid 32 and a plurality of soldered ball 33.
This electronic building brick 30 can be semiconductor chip or semiconductor package, and it is arranged at this and first refuses on layer 27, and is electrically connected by this conductive component 34 the first line layer 25 that these second openings 271 expose.This conductive component 34 can be soldered ball or projection etc.This second packing colloid 32 is formed at this first packing colloid 24 tops, and coated this first line layer 25, first is refused layer 27, electronic building brick 30 and conductive component 34.This soldered ball 33 connects and is placed on the second line layer 28 that the 4th opening 291 exposes.
The method for making of above-mentioned semiconductor package part 6, except comprising the method for making of Fig. 2 A to Fig. 2 O and by semiconductor package part 2 turned upside down, also comprise that this electronic building brick 30 is set first to be refused on layer 27 in this, and the first line layer 25 exposing by this this electronic building brick 30 of conductive component 34 electric connections and this second opening 271, form again this second packing colloid 32 in these the first packing colloid 24 tops, to be coated this first line layer 25, first refuses layer 27, electronic building brick 30 and conductive component 34, separately connect and put on the second line layer 28 that this soldered ball 33 exposes in the 4th opening 291.
As from the foregoing, semiconductor package part of the present invention and method for making thereof, mainly electric conductor and connection gasket are formed at respectively in packing colloid, and by chip embedding bury in this packing colloid to be arranged on this connection gasket, and the connecting portion of this electric conductor is exposed to the surface of this packing colloid, then line layer is formed on the surface of this packing colloid to be electrically connected the connecting portion of this electric conductor.Thus, the present invention can omit the hard plate of prior art, so can reduce the thickness of this semiconductor package part, to dwindle size or the volume of this semiconductor package part, and then reduces the material cost of this semiconductor package part.
Above-described embodiment is only for illustrative principle of the present invention and effect thereof, but not for limiting the present invention.Any those skilled in the art all can, under spirit of the present invention and category, modify to above-described embodiment.So the scope of the present invention, should be as listed in claims.

Claims (22)

1. a semiconductor package part, it comprises:
The first packing colloid, it has relative first surface and second surface;
A plurality of electric conductors, it is formed in this first packing colloid, and has the first connecting portion and the second connecting portion that exposes to respectively this first surface and this second surface;
A plurality of connection gaskets, it is formed in this first packing colloid, and exposes to the second surface of this first packing colloid;
Chip, it is embedded in this first packing colloid, and is arranged on this connection gasket; And
The first line layer, it is formed on the first surface of this first packing colloid, and is electrically connected the first connecting portion of this electric conductor.
2. semiconductor package part according to claim 1, is characterized in that, this semiconductor package part also comprises surface-treated layer, and it is formed on this first line layer.
3. semiconductor package part according to claim 1, is characterized in that, this semiconductor package part also comprises that first refuses layer, and it is formed on this first line layer, and exposes outside this first line layer of part.
4. semiconductor package part according to claim 3, is characterized in that, this semiconductor package part also comprises electronic building brick and a plurality of conductive component, and this electronic building brick is arranged at this and first refuses on layer, and is electrically connected this first line layer by this conductive component.
5. semiconductor package part according to claim 4, is characterized in that, this semiconductor package part also comprises the second packing colloid, and it is formed at this first packing colloid top, and coated this first line layer, first is refused layer, electronic building brick and conductive component.
6. semiconductor package part according to claim 1, is characterized in that, this semiconductor package part also comprises the second line layer, and it is formed on the second surface of this first packing colloid, and is electrically connected the second connecting portion and this connection gasket of this electric conductor.
7. semiconductor package part according to claim 6, is characterized in that, this semiconductor package part also comprises that second refuses layer, and it is formed on this second line layer, and exposes outside this second line layer of part.
8. semiconductor package part according to claim 7, is characterized in that, this semiconductor package part also comprises electronic building brick and a plurality of conductive component, and this electronic building brick is arranged at this and second refuses on layer, and is electrically connected this second line layer by this conductive component.
9. semiconductor package part according to claim 8, is characterized in that, this semiconductor package part also comprises the second packing colloid, and it is formed at this first packing colloid top, and coated this second line layer, second is refused layer, electronic building brick and conductive component.
10. according to the semiconductor package part described in claim 4 or 8, it is characterized in that, this electronic building brick is semiconductor chip or semiconductor package.
The method for making of 11. 1 kinds of semiconductor package parts, it comprises:
The bearing part with metal level is provided;
Form a plurality of connection gaskets and a plurality of electric conductor higher than this connection gasket on this metal level;
Chip is set on this connection gasket;
Form the first packing colloid on this metal level, to be coated this connection gasket, electric conductor and chip, and expose outside the connecting portion of this electric conductor; And
Form the first line layer on this first packing colloid to be electrically connected the connecting portion of this electric conductor.
The method for making of 12. semiconductor package parts according to claim 11, is characterized in that, the step that forms this connection gasket comprises:
Formation has the first resistance layer of a plurality of the first perforation on this metal level, and this first perforating exposed goes out this metal level of part;
Forming this connection is padded in this first perforation to connect this metal level; And
Remove this first resistance layer.
The method for making of 13. semiconductor package parts according to claim 11, is characterized in that, the step that forms this electric conductor comprises:
Formation has a plurality of biperforate the second resistance layers on this metal level, and this second perforation is higher than this connection gasket and expose outside this metal level of part;
Form this electric conductor in this second perforation in to connect this metal level; And
Remove this second resistance layer.
The method for making of 14. semiconductor package parts according to claim 11, is characterized in that, this method for making also comprises that formation surface-treated layer is on this first line layer.
The method for making of 15. semiconductor package parts according to claim 11, is characterized in that, this method for making also comprises that forming first refuses layer on this first line layer and expose outside this first line layer of part.
The method for making of 16. semiconductor package parts according to claim 15, is characterized in that, this method for making also comprises that electronic building brick is set first to be refused on layer in this, and is electrically connected this first line layer by a plurality of conductive components.
The method for making of 17. semiconductor package parts according to claim 16, is characterized in that, this method for making also comprises and forms the second packing colloid in this first packing colloid top, to be coated this first line layer, first, refuses layer, electronic building brick and conductive component.
The method for making of 18. semiconductor package parts according to claim 11, is characterized in that, this method for making also comprises:
Remove this bearing part; And
This metal level of patterning is to form the second line layer.
The method for making of 19. semiconductor package parts according to claim 18, is characterized in that, this method for making also comprises that forming second refuses layer on this second line layer and expose outside this second line layer of part.
The method for making of 20. semiconductor package parts according to claim 19, is characterized in that, this method for making also comprises that electronic building brick is set second to be refused on layer in this, and is electrically connected this second line layer by a plurality of conductive components.
The method for making of 21. semiconductor package parts according to claim 20, is characterized in that, this method for making also comprises and forms the second packing colloid in this first packing colloid top, to be coated this second line layer, second, refuses layer, electronic building brick and conductive component.
22. according to the method for making of the semiconductor package part described in claim 16 or 20, it is characterized in that, this electronic building brick is semiconductor chip or semiconductor package.
CN201310174210.8A 2013-05-03 2013-05-13 Semiconductor package and fabrication method thereof Pending CN104134641A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106129052A (en) * 2016-08-10 2016-11-16 江阴芯智联电子科技有限公司 Two-way integrated embedded type chip reroutes board structure and preparation method thereof
CN109427714A (en) * 2017-08-24 2019-03-05 日月光半导体制造股份有限公司 Semiconductor packages and its manufacturing method
CN109524378A (en) * 2017-09-18 2019-03-26 台湾积体电路制造股份有限公司 Encapsulating structure
CN113628980A (en) * 2021-10-13 2021-11-09 华宇华源电子科技（深圳）有限公司 Board level packaging method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI555153B (en) * 2014-12-19 2016-10-21 恆勁科技股份有限公司 Substrate structure and method of fabricating the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1790651A (en) * 2004-12-07 2006-06-21 新光电气工业株式会社 Manufacturing method of chip integrated substrate
US20070052083A1 (en) * 2005-08-23 2007-03-08 Shinko Electric Industries Co., Ltd. Semiconductor package and manufacturing method thereof
US20100134991A1 (en) * 2008-12-01 2010-06-03 Samsung Electro-Mechanics Co., Ltd. Chip embedded printed circuit board and manufacturing method thereof
US20120038044A1 (en) * 2010-08-12 2012-02-16 Siliconware Precision Industries Co., Ltd. Chip scale package and fabrication method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1790651A (en) * 2004-12-07 2006-06-21 新光电气工业株式会社 Manufacturing method of chip integrated substrate
US20070052083A1 (en) * 2005-08-23 2007-03-08 Shinko Electric Industries Co., Ltd. Semiconductor package and manufacturing method thereof
US20100134991A1 (en) * 2008-12-01 2010-06-03 Samsung Electro-Mechanics Co., Ltd. Chip embedded printed circuit board and manufacturing method thereof
US20120038044A1 (en) * 2010-08-12 2012-02-16 Siliconware Precision Industries Co., Ltd. Chip scale package and fabrication method thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106129052A (en) * 2016-08-10 2016-11-16 江阴芯智联电子科技有限公司 Two-way integrated embedded type chip reroutes board structure and preparation method thereof
CN109427714A (en) * 2017-08-24 2019-03-05 日月光半导体制造股份有限公司 Semiconductor packages and its manufacturing method
CN109427714B (en) * 2017-08-24 2023-09-08 日月光半导体制造股份有限公司 Semiconductor package and method of manufacturing the same
CN109524378A (en) * 2017-09-18 2019-03-26 台湾积体电路制造股份有限公司 Encapsulating structure
CN109524378B (en) * 2017-09-18 2023-05-23 台湾积体电路制造股份有限公司 Package structure and method for manufacturing the same
CN113628980A (en) * 2021-10-13 2021-11-09 华宇华源电子科技（深圳）有限公司 Board level packaging method
CN113628980B (en) * 2021-10-13 2022-02-08 华宇华源电子科技（深圳）有限公司 Board level packaging method

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