CN113628980A - Board level packaging method - Google Patents
Board level packaging method Download PDFInfo
- Publication number
- CN113628980A CN113628980A CN202111189993.8A CN202111189993A CN113628980A CN 113628980 A CN113628980 A CN 113628980A CN 202111189993 A CN202111189993 A CN 202111189993A CN 113628980 A CN113628980 A CN 113628980A
- Authority
- CN
- China
- Prior art keywords
- carrier
- conductive metal
- metal layer
- chip
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 52
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims abstract description 59
- 239000002184 metal Substances 0.000 claims abstract description 59
- 238000009713 electroplating Methods 0.000 claims abstract description 23
- 229910000679 solder Inorganic materials 0.000 claims abstract description 22
- 238000003825 pressing Methods 0.000 claims abstract description 13
- 238000003466 welding Methods 0.000 claims abstract description 11
- 239000011248 coating agent Substances 0.000 claims abstract description 9
- 238000000576 coating method Methods 0.000 claims abstract description 9
- 238000010030 laminating Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 65
- 239000010949 copper Substances 0.000 claims description 28
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 24
- 229910052802 copper Inorganic materials 0.000 claims description 24
- 239000012790 adhesive layer Substances 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 238000012858 packaging process Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 230000003014 reinforcing effect Effects 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 229910000831 Steel Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000003486 chemical etching Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 239000011368 organic material Substances 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 239000010959 steel Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000004381 surface treatment Methods 0.000 claims description 3
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 239000005022 packaging material Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 7
- 238000005553 drilling Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000011093 chipboard Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000010137 moulding (plastic) Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/89—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
The invention relates to a method for packaging board level, step 1, prepare a strippable first carrier; step 2, preparing a second peelable carrier; step 3, pasting a layer of photosensitive film on the first conductive metal layer of the first carrier, and forming at least two isolated bonding pads on the first carrier in a pattern and electroplating mode; step 4, carrying out mounting and welding of at least one chip on one bonding pad of the first carrier; step 5, generating at least two connectors on the surface of the second conductive metal layer of the second carrier for welding, wherein the height of at least one connector is matched with the thickness of the chip; step 6, a laminating sheet is used for windowing at the position corresponding to the chip and the bonding pad; step 7, respectively coating solder on the chip of the first carrier and the other bonding pads; and 8, sleeving the chip and the bonding pad of the first carrier with a pressing sheet, pressing the pressing sheet together relative to the connector of the second carrier, and welding to form the packaging body.
Description
Technical Field
The invention relates to the technical field of chip board level packaging, in particular to a board level packaging method.
Background
In the existing panel level packaging process flow, the following defects exist in the lead-out mode of the chip electrode:
(1) for the laser drilling blind hole and the copper deposition electroplating mode, the main problems are high cost (laser drilling equipment is more expensive), high requirement on a chip bonding pad (common materials cannot tolerate laser and are easy to damage) and large limitation.
(2) The Bump (value ball) process mode mainly has the problems that firstly, the cost is high when a chip is used for manufacturing the Bump, and the mounting difficulty is high after the chip is used for manufacturing the Bump; the chip and the bonding pad to be interconnected with the chip are required to have the same height, and the process is difficult to realize;
(3) in the Cu Clip (copper sheet) process mode, firstly, a separate manufacturing tool is needed for manufacturing the Clip, the cost is high, the tolerance of the process on the height difference between a chip and a bonding pad is poor, and when the height difference between the chip and the bonding pad is large, the process cannot process;
(4) in addition to the above problems, the existing board level packaging process is affected by the interconnection mode, and the problems of poor heat dissipation and large internal resistance are also significant, which seriously affects the performance index of the device.
In order to overcome the existing problems, a board level packaging method is invented.
Disclosure of Invention
The invention aims to solve the problems that the existing lead-out mode of a chip electrode has high cost, high requirements on a chip bonding pad and large limitation in a laser blind hole drilling and copper deposition electroplating mode, a Bump process mode has high cost and large mounting difficulty, a Cu Clip process mode has high cost, and the chip and the bonding pad cannot be processed when the height difference is large. The concrete solution is as follows:
a method for board level packaging is carried out according to the following steps:
step 1, preparing a first strippable carrier;
the first carrier comprises a first carrier plate, a first conductive metal layer and a first bonding layer, wherein the first bonding layer is used for temporarily bonding the first conductive metal layer and the first carrier plate together;
step 2, preparing a second peelable carrier;
the second carrier comprises a second carrier plate, a second conductive metal layer and a second adhesive layer, and the second adhesive layer is used for temporarily adhering the second conductive metal layer and the second carrier plate together;
step 3, pasting a layer of photosensitive film on the first conductive metal layer of the first carrier, and forming at least two isolated bonding pads on the first carrier in a pattern and electroplating mode;
step 4, coating solder on a corresponding position on a pad of the first carrier, and carrying out surface mounting and welding on at least one chip;
step 5, generating at least two connectors on the surface of the second conductive metal layer of the second carrier for welding, wherein the height of at least one connector is matched with the thickness of the chip;
step 6, a laminating sheet is used for windowing at the position corresponding to the chip and the bonding pad;
step 7, respectively coating solder on the chip of the first carrier and the other bonding pads;
step 8, sleeving a chip and a bonding pad of the first carrier with a pressing sheet, pressing the pressing sheet together relative to a connector of the second carrier, and welding to form a packaging body;
step 9, stripping the second carrier from the packaging body, only keeping the connector and the second conductive metal layer on the packaging body, carrying out pattern processing on the second conductive metal layer, and etching off redundant metal to realize interconnection of chip electrodes;
and step 12, performing chemical tin surface treatment on the surface of the external bonding pad to finish the whole board-level packaging process.
Further, the first carrier plate and the second carrier plate are made of any one of organic materials, metal steel plates, aluminum plates or FR4 plates.
Furthermore, the first conductive metal layer and the second conductive metal layer have good conductivity and can be removed by chemical etching or grinding, and the first conductive metal layer and the second conductive metal layer are made of copper.
Further, the first adhesive layer and the second adhesive layer are materials which can be pyrolyzed, photolyzed or directly mechanically peeled.
Further, the laminating sheet is any one of a prepreg or a plastic-packaging material sheet.
Further, the solder is any one of tin paste, conductive adhesive or silver paste.
Further, the solder has good conductivity and bonding ability.
Further, the thickness of the coating solder in the step 7 is larger than at least 20 μm, so that the solder has a buffer effect and makes up height errors between the bonding pad and the chip and between the connector and the bonding pad caused by process capability.
Alternative 1:
the method for forming the connecting body in the step 5 comprises the following steps:
step 511, attaching a layer of photosensitive film on the surface of the second conductive metal layer of the second carrier, and forming at least two isolated pads on the second carrier by means of patterning and electroplating;
step 512, a layer of photosensitive film is attached to the surface of the second conductive metal layer of the second carrier, and at least one pad on the second carrier is heightened through a pattern and electroplating mode, wherein the heightened height of the pad is equal to the thickness of the chip.
Alternative 2:
the method for forming the connecting body in the step 5 comprises the following steps: at least two copper strips with different heights are welded on the surface of the second conductive metal layer of the second carrier, and the height difference of the copper strips is equal to the thickness of the chip.
In summary, the technical scheme of the invention has the following beneficial effects:
the invention solves the problems that the existing lead-out mode of the chip electrode has high cost of laser drilling blind holes and copper deposition electroplating, high requirements on chip bonding pads and large limitations, a Bump process mode has high cost and large mounting difficulty, a Cu Clip process mode has high cost, and the chip and the bonding pads cannot be processed when the height difference is large. The invention has the following advantages:
1. compared with a method for leading out an electrode by laser drilling, the method has the advantages of high processing efficiency, no need of expensive equipment and low requirement on the property of a bonding pad of a chip.
2. The scheme of the invention solves the problems of high processing cost and large chip mounting difficulty of the Bump process.
3. The scheme of the invention has no requirement on the height difference between the chip and the bonding pad needing interconnection, and can be compatible with larger height difference.
4. According to the scheme, the electrodes are interconnected through the copper bar or the thickened electroplating pad, the copper bar or the thickened electroplating pad is welded above the chip, the heat dissipation capacity of the device is greatly improved, the cross section area of the copper bar or the thickened electroplating pad is large, the conductivity is good, and the internal resistance value of the device can be reduced to the maximum extent.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
FIG. 1 is a diagram of a first carrier of a method of board level packaging according to the present invention;
FIG. 2 is a diagram of a second carrier of the method of board level packaging of the present invention;
FIG. 3 is a diagram of a first carrier plated pad configuration of a method of board level packaging according to the present invention;
FIG. 4 is a block diagram of a first carrier mounted chip of a method of board level packaging of the present invention;
FIG. 5 is a structural view of a second carrier plating pad of embodiment 1;
FIG. 6 is a diagram of a lamination sheet of a method of board level packaging according to the present invention;
FIG. 7 is a schematic view of a pressing apparatus for a method of board level packaging according to the present invention;
FIG. 8 is a diagram of a laminated package structure according to a method of board level packaging of the present invention;
fig. 9 is a structural diagram of an external bonding pad of a device formed by secondary plastic packaging and processing after the first carrier and the second carrier are peeled off from the package body;
FIG. 10 is a structural view of a second carrier solder copper bar of example 2;
FIG. 11 is a structural view of a three pin package of embodiment 3;
FIG. 12 is a cross-sectional view taken along line B-B of FIG. 11;
FIG. 13 is a cross-sectional view taken along line A-A of FIG. 11;
fig. 14 is a top structural view of a chip of embodiment 3.
Description of reference numerals:
10-a first carrier, 11-a first carrier, 12-a first conductive metal layer, 13-a first adhesive layer, 14-a pad, 15-solder, 20-a second carrier, 21-a second carrier, 22-a second conductive metal layer, 23-a second adhesive layer, 24-a thickened electroplated pad, 25-a copper strip, 30-a chip, 31-a pin, 40-a laminated sheet, 41-a window, 50-a reinforcing layer, 100-a package body, 101-an external pad.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1:
as shown in fig. 1 to 9: a method for board level packaging is carried out according to the following steps:
step 1, preparing a first peelable carrier 10;
the first carrier 10 comprises a first carrier 11 with better rigidity, a first conductive metal layer 12 and a first adhesive layer 13, wherein the first adhesive layer 13 is used for temporarily adhering the first conductive metal layer 12 and the first carrier 11 together;
step 2, preparing a second peelable carrier 20;
the second carrier 20 comprises a second carrier 21 with better rigidity, a second conductive metal layer 22 and a second adhesive layer 23, wherein the second adhesive layer 23 is used for temporarily adhering the second conductive metal layer 22 and the second carrier 21 together;
step 3, pasting a layer of photosensitive film on the first conductive metal layer 12 of the first carrier 10, and forming at least two isolated pads 14 (namely electroplating pads) on the first carrier 10 in a pattern and electroplating manner;
step 4, coating solder 15 on a corresponding position on a pad of the first carrier 10, and carrying out surface mounting and welding on at least one chip 30;
step 5, generating at least two connectors on the surface of the second conductive metal layer 22 of the second carrier 20 for soldering, wherein the height of at least one connector (i.e. the longer connector) matches with the thickness of the chip 30; (Note: the difference in height between the longer and shorter connectors is equal to the thickness of the chip 30)
Optionally, the method for forming the connecting body comprises:
step 511, pasting a photosensitive film on the surface of the second conductive metal layer 22 of the second carrier 20, and forming at least two isolated pads 14 on the second carrier 20 by means of patterning and electroplating;
step 512, a photosensitive film is further attached to the surface of the second conductive metal layer 22 of the second carrier 20, and at least one bonding pad 14 on the second carrier 20 is heightened through a pattern and electroplating manner to become a thickened electroplating bonding pad 24, wherein the heightened height of the bonding pad (i.e., the thickened electroplating bonding pad 24) is equal to the thickness of the chip 30.
Step 6, a laminating sheet 40 is used for windowing 41 (such as rectangular windowing) at the position corresponding to the chip 30 and the bonding pad 14;
step 7, respectively coating solder 15 on the chip 30 and the additional bonding pad 14 of the first carrier 10;
step 8, sleeving the chip 30 and the bonding pad 14 of the first carrier 10 on a pressing sheet 40, pressing the pressing sheet 40 together relative to the connector of the second carrier 20, and welding to form a packaging body 100; the lamination process of the lamination sheet 40 is to perform a plastic package.
Step 9, stripping the second carrier 20 from the package body 100, only keeping the connector and the second conductive metal layer 22 on the package body 100, performing pattern processing on the second conductive metal layer 22, and etching away excess metal to realize interconnection of the electrodes of the chip 30;
and step 12, performing chemical tin surface treatment on the surface of the external bonding pad 101 to complete the whole board-level packaging process.
Specifically, the first carrier plate 11 and the second carrier plate 21 are made of any one of an organic material, a metal steel plate, an aluminum plate, or an FR4 plate.
Specifically, the first conductive metal layer 12 and the second conductive metal layer 22 have good conductivity and can be removed by chemical etching or grinding, and the first conductive metal layer 12 and the second conductive metal layer 22 are preferably copper (other metals may be used instead according to actual situations). The first adhesive layer 13 and the second adhesive layer 23 are materials that can be pyrolyzed, photolyzed, or directly mechanically peeled off. The laminate 40 is any one of a prepreg and a sheet of plastic molding. The solder 15 is any of a solder paste, a conductive paste, or a silver paste. The solder 15 has good conductivity and adhesion ability.
Specifically, the thickness of the applied solder 15 in step 7 is greater than at least 20 μm, so that the solder 15 has a buffer effect to compensate for the height error between the pad (including the pad 14, the thickened plated pad 24, and the copper bar 25 in example 2) and the chip 30, and the longer connector (the thickened plated pad 24 or the tall copper bar 25 in example 2) and the pad 14 due to the process capability.
Example 2:
as shown in fig. 10, unlike example 1, the method for forming the linker in step 5 is: at least two copper strips 25 with different heights are welded on the surface of the second conductive metal layer 22 of the second carrier 20, and the height difference of the copper strips 25 is equal to the thickness of the chip 30. The rest of the contents are completely the same as embodiment 1, and are not described again here.
Example 3:
as shown in fig. 11 to 14, different from embodiment 1, the chip 30 in embodiment 1 has one upper pin and one lower pin, the chip 30 in embodiment 3 has one bottom pin and two top pins 31, accordingly, three pads 14 are provided on the first carrier 10, four connectors (for example, four pads 14 and two thickened plating pads 24 are provided) are provided on the second carrier 20, and accordingly, three external pads 101 are provided on the lower portion of the package 100 as the pins of the device. The rest of the description is identical to (or similar in principle to) embodiment 1, and will not be described herein again.
In summary, the technical scheme of the invention has the following beneficial effects:
the invention solves the problems that the existing lead-out mode of the chip electrode has high cost of laser drilling blind holes and copper deposition electroplating, high requirements on chip bonding pads and large limitations, a Bump process mode has high cost and large mounting difficulty, a Cu Clip process mode has high cost, and the chip and the bonding pads cannot be processed when the height difference is large. The invention has the following advantages:
1. compared with a method for leading out an electrode by laser drilling, the method has the advantages of high processing efficiency, no need of expensive equipment and low requirement on the property of a bonding pad of a chip.
2. The scheme of the invention solves the problems of high processing cost and large chip mounting difficulty of the Bump process.
3. The scheme of the invention has no requirement on the height difference between the chip and the bonding pad needing interconnection, and can be compatible with larger height difference.
4. According to the scheme, the electrodes are interconnected through the copper bar or the thickened electroplating pad, the copper bar or the thickened electroplating pad is welded above the chip, the heat dissipation capacity of the device is greatly improved, the cross section area of the copper bar or the thickened electroplating pad is large, the conductivity is good, and the internal resistance value of the device can be reduced to the maximum extent.
The above-described embodiments do not limit the scope of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the above-described embodiments should be included in the protection scope of the technical solution.
Claims (10)
1. A method of board level packaging, comprising the steps of:
step 1, preparing a first strippable carrier;
the first carrier comprises a first carrier plate, a first conductive metal layer and a first bonding layer, wherein the first bonding layer is used for temporarily bonding the first conductive metal layer and the first carrier plate together;
step 2, preparing a second peelable carrier;
the second carrier comprises a second carrier plate, a second conductive metal layer and a second adhesive layer, and the second adhesive layer is used for temporarily adhering the second conductive metal layer and the second carrier plate together;
step 3, pasting a layer of photosensitive film on the first conductive metal layer of the first carrier, and forming at least two isolated bonding pads on the first carrier in a pattern and electroplating mode;
step 4, coating solder on a corresponding position on a pad of the first carrier, and carrying out surface mounting and welding on at least one chip;
step 5, generating at least two connectors on the surface of the second conductive metal layer of the second carrier for welding, wherein the height of at least one connector is matched with the thickness of the chip;
step 6, a laminating sheet is used for windowing at the position corresponding to the chip and the bonding pad;
step 7, respectively coating solder on the chip of the first carrier and the other bonding pads;
step 8, sleeving a chip and a bonding pad of the first carrier with a pressing sheet, pressing the pressing sheet together relative to a connector of the second carrier, and welding to form a packaging body;
step 9, stripping the second carrier from the packaging body, only keeping the connector and the second conductive metal layer on the packaging body, carrying out pattern processing on the second conductive metal layer, and etching off redundant metal to realize interconnection of chip electrodes;
step 10, carrying out secondary plastic package on the whole device, protecting the interconnected graphs and using the protected graphs as a reinforcing layer of the whole structure;
step 11, stripping the first carrier from the packaging body, and carrying out patterning and etching processing on the first conductive metal layer to form an external bonding pad of the device;
and step 12, performing chemical tin surface treatment on the surface of the external bonding pad to finish the whole board-level packaging process.
2. The method of board level packaging according to claim 1, wherein: the first carrier plate and the second carrier plate are made of any one of organic materials, metal steel plates, aluminum plates or FR4 plates.
3. The method of board level packaging according to claim 1, wherein: the first conductive metal layer and the second conductive metal layer have good conductivity and can be removed by chemical etching or grinding, and the first conductive metal layer and the second conductive metal layer are made of copper.
4. The method of board level packaging according to claim 1, wherein: the first adhesive layer and the second adhesive layer are materials which can be pyrolyzed, photolyzed or directly peeled off mechanically.
5. The method of board level packaging according to claim 1, wherein: the laminating sheet is any one of a prepreg or a plastic-packaging material sheet.
6. The method of board level packaging according to claim 1, wherein: the solder is any one of tin paste, conductive adhesive or silver paste.
7. The method of board level packaging according to claim 6, wherein: the solder has good conductivity and bonding capability.
8. The method of board level packaging according to claim 1, wherein: and 7, the thickness of the coating solder is more than at least 20 μm, so that the solder has a buffer effect and makes up height errors between the bonding pad and the chip and between the connector and the bonding pad caused by process capability.
9. The method for board level packaging according to claim 1, wherein the method for forming the connector in step 5 comprises:
step 511, attaching a layer of photosensitive film on the surface of the second conductive metal layer of the second carrier, and forming at least two isolated pads on the second carrier by means of patterning and electroplating;
step 512, a layer of photosensitive film is attached to the surface of the second conductive metal layer of the second carrier, and at least one pad on the second carrier is heightened through a pattern and electroplating mode, wherein the heightened height of the pad is equal to the thickness of the chip.
10. The method for board level packaging according to claim 1, wherein the method for forming the connector in step 5 comprises: at least two copper strips with different heights are welded on the surface of the second conductive metal layer of the second carrier, and the height difference of the copper strips is equal to the thickness of the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111189993.8A CN113628980B (en) | 2021-10-13 | 2021-10-13 | Board level packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111189993.8A CN113628980B (en) | 2021-10-13 | 2021-10-13 | Board level packaging method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113628980A true CN113628980A (en) | 2021-11-09 |
| CN113628980B CN113628980B (en) | 2022-02-08 |
Family
ID=78391267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111189993.8A Active CN113628980B (en) | 2021-10-13 | 2021-10-13 | Board level packaging method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113628980B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113628980B (en) * | 2021-10-13 | 2022-02-08 | 华宇华源电子科技（深圳）有限公司 | Board level packaging method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030036220A1 (en) * | 2001-08-20 | 2003-02-20 | Gorou Ikegami | Printed circuit board having plating conductive layer with bumps and its manufacturing method |
| US20070196999A1 (en) * | 2004-07-30 | 2007-08-23 | Semiconductor Energy Laboratory Co., Ltd. | Method For Manufacturing Semiconductor Device |
| US20140264795A1 (en) * | 2011-11-28 | 2014-09-18 | Jiangsu Changjiang Electronics Technology Co., Ltd. | No-exposed-pad quad flat no-lead (qfn) packaging structure and method for manufacturing the same |
| CN104134641A (en) * | 2013-05-03 | 2014-11-05 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| US20190035642A1 (en) * | 2015-09-10 | 2019-01-31 | Sj Semiconductor (Jiangyin) Corporation | Chip packaging method |
| CN111627865A (en) * | 2019-02-27 | 2020-09-04 | 恒劲科技股份有限公司 | Semiconductor packaging structure and manufacturing method thereof |
| CN111916359A (en) * | 2019-05-09 | 2020-11-10 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113628980B (en) * | 2021-10-13 | 2022-02-08 | 华宇华源电子科技（深圳）有限公司 | Board level packaging method |
-
2021
- 2021-10-13 CN CN202111189993.8A patent/CN113628980B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030036220A1 (en) * | 2001-08-20 | 2003-02-20 | Gorou Ikegami | Printed circuit board having plating conductive layer with bumps and its manufacturing method |
| US20070196999A1 (en) * | 2004-07-30 | 2007-08-23 | Semiconductor Energy Laboratory Co., Ltd. | Method For Manufacturing Semiconductor Device |
| US20140264795A1 (en) * | 2011-11-28 | 2014-09-18 | Jiangsu Changjiang Electronics Technology Co., Ltd. | No-exposed-pad quad flat no-lead (qfn) packaging structure and method for manufacturing the same |
| CN104134641A (en) * | 2013-05-03 | 2014-11-05 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| US20190035642A1 (en) * | 2015-09-10 | 2019-01-31 | Sj Semiconductor (Jiangyin) Corporation | Chip packaging method |
| CN111627865A (en) * | 2019-02-27 | 2020-09-04 | 恒劲科技股份有限公司 | Semiconductor packaging structure and manufacturing method thereof |
| CN111916359A (en) * | 2019-05-09 | 2020-11-10 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113628980B (en) * | 2021-10-13 | 2022-02-08 | 华宇华源电子科技（深圳）有限公司 | Board level packaging method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113628980B (en) | 2022-02-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103167727B (en) | Circuit board and manufacture method thereof | |
| CN101820728B (en) | Technological method for processing printed circuit board (PCB) with stepped groove | |
| CN106409688A (en) | Processing method of ultrathin coreless package substrate and structure | |
| JP2006108211A (en) | Wiring board, multilayered wiring circuit board using the board, and method of manufacturing the multilayered wiring circuit board | |
| CN105789173B (en) | Integrate wiring board of intermediary layer and double wire structures and preparation method thereof | |
| CN106879188B (en) | A kind of production method and circuit board of built-in component type circuit board | |
| US8421204B2 (en) | Embedded semiconductor power modules and packages | |
| CN106340461A (en) | Processing method of ultra-thin coreless encapsulation substrate and ultra-thin coreless encapsulation substrate structure | |
| CN103635036A (en) | Flexible multilayer circuit board and method of manufacturing same | |
| CN104347267A (en) | Method of producing electronic components and method of producing substrate-type terminals | |
| CN113628980B (en) | Board level packaging method | |
| KR20090105661A (en) | Multilayer printed circuit board and a fabricating method of the same | |
| JPH08148828A (en) | Thin film multilayered circuit board and its manufacture | |
| JP2022042482A (en) | Connector achieving versatile interconnection and manufacturing method thereof | |
| CN110972413B (en) | Composite circuit board and manufacturing method thereof | |
| CN101578929A (en) | Printed wiring board and method for manufacturing the same | |
| CN217825568U (en) | Double-layer flexible circuit board | |
| CN201717256U (en) | Passive device and circuit board embedded with same | |
| CN113161241B (en) | Preparation method of discrete semiconductor packaging support | |
| CN216775119U (en) | Pcb stiffening plate | |
| CN114900994B (en) | Embedded circuit type circuit board and preparation method thereof | |
| CN103531483A (en) | Bearing part and manufacturing method of coreless packaging substrate | |
| CN216113505U (en) | High-power LED lamp strip | |
| WO2023116595A1 (en) | Double-layer flexible circuit board and method for manufacturing same | |
| WO2022065395A1 (en) | Electronic component module and method for manufacturing electronic component module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |