CN107611152A - The method for packing of back-illuminated type cmos sensor - Google Patents
The method for packing of back-illuminated type cmos sensor Download PDFInfo
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- CN107611152A CN107611152A CN201710792005.6A CN201710792005A CN107611152A CN 107611152 A CN107611152 A CN 107611152A CN 201710792005 A CN201710792005 A CN 201710792005A CN 107611152 A CN107611152 A CN 107611152A
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- type cmos
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Abstract
The present invention provides a kind of method for packing of back-illuminated type cmos sensor, including：Re-wiring layer；Back-illuminated type cmos sensor structure, it is fixedly connected on the second face of the re-wiring layer；Logic chip, it is arranged at the first face of the re-wiring layer；Encapsulating material, it is coated on the logic chip；Perforation, is formed in the encapsulating material；Metal lead wire structure, it is made in the perforation, to realize the re-wiring layer, the back-illuminated type cmos sensor structure and the electrical extraction of the logic chip.The present invention realizes the electrical connection between back-illuminated type cmos sensor, the logic chip and the metal lead wire structure using the method for re-wiring layer, has the advantages of encapsulation volume is small, sensing capabilities and high device reliability；Only metal column need to be made in encapsulating material in advance can realize the electrical extraction of re-wiring layer, it is not necessary to carry out the techniques such as silicon perforation, can greatly save process costs.
Description
Technical field
The invention belongs to field of semiconductor package, more particularly to a kind of method for packing of back-illuminated type cmos sensor.
Background technology
As the function of integrated circuit is increasingly stronger, performance and integrated level more and more higher, and new integrated circuit goes out
Existing, encapsulation technology plays more and more important role in IC products, shared in the value of whole electronic system
Ratio it is increasing.Meanwhile as integrated circuit feature size reaches nanoscale, transistor to more high density, it is higher when
Clock frequency develops, and encapsulation also develops to more highdensity direction.
Because fan-out wafer level encapsulates (fowlp) technology due to having the advantages that miniaturization, low cost and high integration, with
And the energy efficiency with better performance and Geng Gao, fan-out wafer level encapsulation (fowlp) technology as high request movement/
The important method for packing of the electronic equipments such as wireless network, it is one of encapsulation technology most with prospects at present.
Existing image sensor chip encapsulation is generally thicker with thickness, and silicon perforation process costs are higher, metal connecting line
It is easily broken off, the overall more low shortcomings of yield.
In addition, image sensor chip, such as back-illuminated type cmos image sensing chip, it usually needs collocation chip set logic
Into use, existing preparation method is to enter individually packaged image sensor chip with logic chip by SUB substrates etc.
Row is electrically connected with, and needs to realize the electrical extraction of device by silicon perforation technique.This method for packing causes the body of device
Product is larger, and packaging technology process is complex, and silicon perforation process costs are higher, causes the cost of final products higher.
Based on described above, there is provided one kind can be with effective integration back-illuminated type cmos sensor and logic chip, and effectively drops
Low encapsulating structure volume and device stability, and effectively reduce the encapsulating structure of cost and method for packing is necessary.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of back-illuminated type cmos sensor
Method for packing, for solution, the encapsulation volume of image sensor chip and logic chip is larger in the prior art, device stability
The problem of low and product yield is relatively low.
In order to achieve the above objects and other related objects, the present invention provides a kind of encapsulation side of back-illuminated type cmos sensor
Method, the method for packing include：1) support substrate is provided, separating layer is formed in the support substrate surface；2) in described point
Metal lead wire structure is formed on absciss layer；3) offer and logic chip, the logic chip is adhered in the separating layer, its
In, the logic chip has the one of electric deriving structure facing to the separating layer；4) using encapsulating material to the logic core
Piece is packaged；5) encapsulating material and the support substrate are separated based on the separating layer；6) in the encapsulating material and
Re-wiring layer is made on logic chip, to realize the electrical connection between the logic chip and the metal lead wire structure；With
And 7) a back-illuminated type cmos sensor structure is provided, the back-illuminated type cmos sensor structure is fixed on the rewiring
Layer, to realize electrically connecting between the back-illuminated type cmos sensor structure, the logic chip and the metal lead wire structure
Connect；Wherein, the step of preparation method also includes making the metal lead wire structure be exposed to the encapsulating material.
Preferably, the support substrate includes glass substrate, metal substrate, Semiconductor substrate, polymer substrate and ceramics
One kind in substrate；The separating layer includes one kind in adhesive tape and polymeric layer, and the polymeric layer uses spin coating work first
Skill is coated on the support substrate surface, then makes its curing molding using ultra-violet curing or heat curing process.
Preferably, the height of the metal lead wire structure is more than the thickness of the logic chip.
Preferably, step 7) includes：7-1) providing a front has the wafer of imaging sensor, by the front of the wafer
After being adhered to a protective layer, the wafer is thinned from the back side；A transparent cover plate 7-2) is provided, by the transparent cover plate key
Together in the back side of the wafer；The protective layer 7-3) is peeled off, exposes the imaging sensor of the wafer frontside, with described in acquisition
Back-illuminated type cmos sensor structure；And 7-4) the back-illuminated type cmos sensor structure is exposed to the one side for having imaging sensor
The re-wiring layer is fixed on, to realize that the back-illuminated type cmos sensor structure, the logic chip are drawn with the metal
Electric connection between cable architecture.
Preferably, step 7-1) in, the thickness of the wafer after being thinned is no more than 3 μm, to improve described image biography
The photosensitive intensity in the back side of sensor.
Preferably, step 7-2) in, the transparent cover plate is bonded to the back side of the wafer based on golden tin bonded layer.
Preferably, step 4) includes compression forming, transfer modling using the method for the encapsulating material encapsulation logic chip
One kind in shaping, fluid-tight shaping, vacuum lamination and spin coating, the encapsulating material include polyimides, silica gel and asphalt mixtures modified by epoxy resin
One kind in fat.
Preferably, step 6) makes the re-wiring layer as alternately following steps：Using chemical vapor deposition work
Skill or physical gas-phase deposition form dielectric layer in the plane of the logic chip and encapsulating material, and the dielectric layer is entered
Row etching forms patterned dielectric layer；Using chemical vapor deposition method, evaporation process, sputtering technology, electroplating technology or change
Learn depositing process and form metal level in the patterned media layer surface, and the metal level is performed etching to form patterned gold
Belong to wiring layer.
Preferably, the material of the dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass,
One or both of fluorine-containing glass combination of the above, the material of the metal wiring layer are included in copper, aluminium, nickel, gold, silver, titanium
One or more combination.
Preferably, the metal lead wire structure is formed folded including metal column, solder ball and metal column with solder bump
One kind in layer.
Preferably, make the metal lead wire structure be exposed to the method for the encapsulating material to be in step 4), step 5), walk
It is rapid that 6) or in step 7) encapsulating material is thinned.
As described above, the method for packing of the back-illuminated type cmos sensor of the present invention, has the advantages that：
1) present invention realizes back-illuminated type cmos sensor, the logic chip and the gold using the method for re-wiring layer
Belong to the electrical connection between pin configuration, there is the advantages of encapsulation volume is small, sensing capabilities and high device reliability；
2) present invention only need to make metal column in encapsulating material in advance can realize the electrical extraction of re-wiring layer, no
Need to carry out the techniques such as silicon perforation, process costs can be greatlyd save；
3) present invention process is simple, can effectively improve the encapsulation performance of back-illuminated type cmos sensor and logic chip, half
Conductor encapsulation field is with a wide range of applications.
Brief description of the drawings
The structure that each step of method for packing that Fig. 1~Figure 15 is shown as the back-illuminated type cmos sensor of the present invention is presented is shown
It is intended to.
Component label instructions
101 support substrates
102 separating layers
103 metal lead wire structures
104 wafers
1041 imaging sensors
105 logic chips
106 encapsulating materials
107 re-wiring layers
108 transparent cover plates
109 gold medal tin bonded layers
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Refer to Fig. 1~Figure 15.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, the component relevant with the present invention is only shown in illustrating then rather than according to package count during actual implement
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
As shown in Fig. 1~Figure 15, the present embodiment provides a kind of method for packing of back-illuminated type cmos sensor, the encapsulation side
Method includes：
As shown in Fig. 1~Fig. 2, step 1) is carried out first, there is provided a support substrate 101, in support substrate surface shape
Into separating layer 102.
As an example, the support substrate 101 include glass substrate, metal substrate, Semiconductor substrate, polymer substrate and
One kind in ceramic substrate.In the present embodiment, the support substrate 101 is from being glass substrate, the glass substrate cost
It is relatively low, separating layer 102 easily is formed on its surface, and the difficulty of follow-up stripping technology can be reduced.
As an example, the separating layer 102 includes one kind in adhesive tape and polymeric layer, the polymeric layer uses first
Spin coating proceeding is coated on the surface of support substrate 101, then makes its curing molding using ultra-violet curing or heat curing process.
In the present embodiment, for the separating layer 102 from being adhesive tape, the adhesive tape cost is relatively low, and in follow-up separation
Only need to apply a power in technique and raised, adhesion and separating technology are all relatively simple, can greatly save whole technique
Cost.
As shown in figure 3, step 2) is then carried out, in formation metal lead wire structure 103 in the separating layer 102.
As an example, the metal lead wire structure 103 includes metal column, solder ball and metal column and solder bump institute group
Into lamination in one kind.The shape of the metal lead wire can be adjusted according to the design of follow-up re-wiring layer 107, finally
Described image sensor chip 104 and logic chip 105 are electrically led into encapsulating material by the re-wiring layer 107
106 surface, it is not necessary to electricity can be achieved using expensive silicon perforation technology and draw.
As an example, the height of the metal lead wire structure 103 is more than the thickness of logic chip 105, in order to subsequently will
The metal lead wire structure 103 is exposed to encapsulating material 106.
In the present embodiment, the metal lead wire structure 103 is from being the good copper post of electric conductivity, further to save
Process costs.
As shown in figure 4, then carry out step 3), there is provided logic chip 105, the logic chip 105 is adhered to described
In separating layer 102, wherein, the logic chip 105 has the one of electric deriving structure facing to the separating layer 102.
The quantity of the logic chip 105 can also be one or two or it is multiple, can be according to the performance requirement of device
Selected.
As shown in figure 5, then carrying out step 4), addressed logic chip 105 is packaged using encapsulating material 106.
As an example, the method for the logic chip 105 is encapsulated using encapsulating material 106 includes compression forming, transmission mould
The one kind being moulded into type, fluid-tight shaping, vacuum lamination and spin coating, the encapsulating material 106 include polyimides, silica gel and ring
One kind in oxygen tree fat.
As an example, thickness of the thickness of the encapsulating material 106 at least above addressed logic chip 105.
As shown in fig. 6, then carrying out step 5), the encapsulating material 106 and the branch are separated based on the separating layer 102
Support substrate 101.
As an example, the encapsulating material 106 is raised from the separating layer 102 by applying a power, you can realize and divide
From.
As shown in fig. 7, as an example, also make described including the back side of the encapsulating material 106 is thinned after separation
Metal lead wire structure 103 is exposed to the step of encapsulating material 106.
As shown in figure 8, step 6) is then carried out, in making rewiring on the encapsulating material 106 and logic chip 105
Layer 107, to realize the electrical connection between the logic chip 105 and the metal lead wire structure 103.
Specifically, making the re-wiring layer 107 includes：
Step a), using chemical vapor deposition method or physical gas-phase deposition in the encapsulating material 106 and logic
Dielectric layer is formed on chip 105, and the dielectric layer is performed etching to form patterned dielectric layer.
As an example, the material of the dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorus silicon glass
One or both of glass, fluorine-containing glass combination of the above.In the present embodiment, it is silica that the dielectric layer, which is selected,.
Step b), using chemical vapor deposition method, evaporation process, sputtering technology, electroplating technology or chemical plating process in
The patterned media layer surface forms metal level, and the metal level is performed etching to form patterned metal wiring layer.
As an example, the material of the metal wiring layer is included more than one or both of copper, aluminium, nickel, gold, silver, titanium
Combination.In the present embodiment, the material selection of the metal wiring layer is copper.
It should be noted that the re-wiring layer 107 can include the multiple dielectric layers stacked gradually and multiple gold
Belong to wiring layer, according to line demand, each layer metal wiring layer is realized by each dielectric layer being patterned or being made through hole
Between interconnection, to realize the line demand of difference in functionality.
As shown in Fig. 9~Figure 14, step 7) is then carried out, there is provided a back-illuminated type cmos sensor structure, by the back-illuminated
Formula cmos sensor structure is fixed on the second face of the re-wiring layer 107, to realize the back-illuminated type cmos sensor knot
Electric connection between structure, the logic chip 105 and the metal lead wire structure 103.
As an example, step 6) includes：
As shown in Fig. 9~Figure 11, step 6-1 is carried out first), there is provided a front has the wafer of imaging sensor 1041
104, after the front of the wafer 104 is adhered into a protective layer 110, the wafer 104 is thinned from the back side.
As an example, step 7-1) in, the thickness of the wafer 104 after being thinned is no more than 3 μm, to improve the figure
As the photosensitive intensity in the back side of sensor 1041.
As shown in figure 12, step 7-2 is then carried out), there is provided a transparent cover plate 108, the transparent cover plate 108 is bonded to
The back side of the wafer 104.
As an example, step 7-2) in, the transparent cover plate 108 is bonded to the wafer 104 based on golden tin bonded layer 109
The back side.In the present embodiment, it is glass cover-plate that the transparent cover plate 108, which is selected,.
As shown in figure 13, step 7-3 is then carried out), the protective layer 110 is peeled off, exposes the 104 positive figure of wafer
As sensor 1041, to obtain the back-illuminated type cmos sensor structure.
As shown in figure 14, step 7-4 is finally carried out), the back-illuminated type cmos sensor structure, which is exposed, image sensing
The one side of device 1041 is fixed on the second face of the re-wiring layer 107, to realize the back-illuminated type cmos sensor structure, institute
State the electric connection between logic chip 105 and the metal lead wire structure 103.
In addition, it is solder ball that the metal lead wire structure 103, which can also be selected, then the structure ultimately formed such as Figure 15 institutes
Show.
As described above, the method for packing of the back-illuminated type cmos sensor of the present invention, has the advantages that：
1) present invention realizes back-illuminated type cmos sensor, the logic chip and the gold using the method for re-wiring layer
Belong to the electrical connection between pin configuration, there is the advantages of encapsulation volume is small, sensing capabilities and high device reliability；
2) present invention only need to make metal column in encapsulating material in advance can realize the electrical extraction of re-wiring layer, no
Need to carry out the techniques such as silicon perforation, process costs can be greatlyd save；
3) present invention process is simple, can effectively improve the encapsulation performance of back-illuminated type cmos sensor and logic chip, half
Conductor encapsulation field is with a wide range of applications.
So the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (11)
1. a kind of method for packing of back-illuminated type cmos sensor, it is characterised in that the method for packing includes：
1) support substrate is provided, separating layer is formed in the support substrate surface；
2) in formation metal lead wire structure in the separating layer；
3) offer and logic chip, the logic chip is adhered in the separating layer, wherein, the logic chip has electricity
The one of deriving structure is facing to the separating layer；
4) logic chip is packaged using encapsulating material；
5) encapsulating material and the support substrate are separated based on the separating layer；
6) in making re-wiring layer on the encapsulating material and logic chip, to realize that the logic chip draws with the metal
Electrical connection between cable architecture；And
7) a back-illuminated type cmos sensor structure is provided, the back-illuminated type cmos sensor structure is fixed on the rewiring
Layer, to realize electrically connecting between the back-illuminated type cmos sensor structure, the logic chip and the metal lead wire structure
Connect；
Wherein, the step of preparation method also includes making the metal lead wire structure be exposed to the encapsulating material.
2. the method for packing of back-illuminated type cmos sensor according to claim 1, it is characterised in that：The support substrate bag
Include one kind in glass substrate, metal substrate, Semiconductor substrate, polymer substrate and ceramic substrate；The separating layer includes glue
One kind in band and polymeric layer, the polymeric layer are coated on the support substrate surface using spin coating proceeding first, then
Its curing molding is made using ultra-violet curing or heat curing process.
3. the method for packing of back-illuminated type cmos sensor according to claim 1, it is characterised in that：The metal lead wire knot
The height of structure is more than the thickness of the logic chip.
4. the method for packing of back-illuminated type cmos sensor according to claim 1, it is characterised in that：Step 7) includes：
7-1) providing a front has the wafer of imaging sensor, after the front of the wafer is adhered into a protective layer, from the back of the body
It is thinned in face of the wafer；
One transparent cover plate 7-2) is provided, the transparent cover plate is bonded to the back side of the wafer；
The protective layer 7-3) is peeled off, exposes the imaging sensor of the wafer frontside, is sensed with obtaining the back-illuminated type CMOS
Device structure；And
The one side that 7-4) exposing the back-illuminated type cmos sensor structure has imaging sensor is fixed on the re-wiring layer,
To realize electrically connecting between the back-illuminated type cmos sensor structure, the logic chip and the metal lead wire structure
Connect.
5. the method for packing of back-illuminated type cmos sensor according to claim 4, it is characterised in that：Step 7-1) in, subtract
The thickness of the wafer after thin is no more than 3 μm, to improve the photosensitive intensity in the back side of described image sensor.
6. the method for packing of back-illuminated type cmos sensor according to claim 4, it is characterised in that：Step 7-2) in, institute
State the back side that transparent cover plate is bonded to the wafer based on golden tin bonded layer.
7. the method for packing of back-illuminated type cmos sensor according to claim 1, it is characterised in that：Step 4) is using encapsulation
The method of logic chip described in material package is included in compression forming, Transfer molding, fluid-tight shaping, vacuum lamination and spin coating
One kind, the encapsulating material include polyimides, silica gel and epoxy resin in one kind.
8. the method for packing of back-illuminated type cmos sensor according to claim 1, it is characterised in that：Described in step 6) makes
Re-wiring layer is alternately following steps：
Formed using chemical vapor deposition method or physical gas-phase deposition in the plane of the logic chip and encapsulating material
Dielectric layer, and the dielectric layer is performed etching to form patterned dielectric layer；
Using chemical vapor deposition method, evaporation process, sputtering technology, electroplating technology or chemical plating process in graphical Jie
Matter layer surface forms metal level, and the metal level is performed etching to form patterned metal wiring layer.
9. the method for packing of back-illuminated type cmos sensor according to claim 8, it is characterised in that：The material of the dielectric layer
Material includes one or both of epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, fluorine-containing glass above group
Close, the material of the metal wiring layer includes one or both of copper, aluminium, nickel, gold, silver, titanium combination of the above.
10. the method for packing of back-illuminated type cmos sensor according to claim 1, it is characterised in that：The metal lead wire
Structure includes one kind in the lamination that metal column, solder ball and metal column are formed with solder bump.
11. the method for packing of integrated image sensor chip according to claim 1 and logic chip, it is characterised in that：
The metal lead wire structure is set to be exposed to the method for the encapsulating material as in step 4), step 5), step 6) or step 7)
The encapsulating material is thinned.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710792005.6A CN107611152B (en) | 2017-09-05 | 2017-09-05 | Packaging method of back-illuminated CMOS sensor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710792005.6A CN107611152B (en) | 2017-09-05 | 2017-09-05 | Packaging method of back-illuminated CMOS sensor |
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| CN107611152B CN107611152B (en) | 2020-02-04 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101292352A (en) * | 2005-09-01 | 2008-10-22 | 美光科技公司 | Microelectronic imaging units and methods of manufacturing microelectronic imaging units at the wafer level |
| CN105161431A (en) * | 2015-08-12 | 2015-12-16 | 中芯长电半导体（江阴）有限公司 | Packaging method of wafer-level chip |
| CN105514087A (en) * | 2016-01-26 | 2016-04-20 | 中芯长电半导体（江阴）有限公司 | Double-faced fan-out type wafer-level packaging method and packaging structure |
-
2017
- 2017-09-05 CN CN201710792005.6A patent/CN107611152B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101292352A (en) * | 2005-09-01 | 2008-10-22 | 美光科技公司 | Microelectronic imaging units and methods of manufacturing microelectronic imaging units at the wafer level |
| CN105161431A (en) * | 2015-08-12 | 2015-12-16 | 中芯长电半导体（江阴）有限公司 | Packaging method of wafer-level chip |
| CN105514087A (en) * | 2016-01-26 | 2016-04-20 | 中芯长电半导体（江阴）有限公司 | Double-faced fan-out type wafer-level packaging method and packaging structure |
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Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |