CN107611045A - A kind of three-dimensional chip encapsulating structure and its method for packing - Google Patents
A kind of three-dimensional chip encapsulating structure and its method for packing Download PDFInfo
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- CN107611045A CN107611045A CN201710909208.9A CN201710909208A CN107611045A CN 107611045 A CN107611045 A CN 107611045A CN 201710909208 A CN201710909208 A CN 201710909208A CN 107611045 A CN107611045 A CN 107611045A
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- nude film
- dimensional chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The present invention provides a kind of three-dimensional chip encapsulating structure and its method for packing; the encapsulating structure is using package substrate, perforation silicon intermediary layer, the packing forms of die stack; and the protection of nude film is realized using plastic packaging layer; wherein, nude film can be connected with perforation silicon intermediary layer by conductive projection and re-wiring layer.The encapsulating structure has the advantages of simple in construction, higher I/O density, faster efficiency of transmission.The method for packing adheres to perforation silicon intermediary layer first on bearing substrate, then nude film face down is installed on perforation silicon intermediary layer, and in the plastic packaging layer that the covering nude film and the perforation silicon intermediary layer are formed on adhesion layer, then bearing substrate and adhesion layer are removed, obtain the three-dimensional chip module for including perforation silicon intermediary layer, nude film and plastic packaging layer, one package substrate is finally provided, the one side that three-dimensional chip module has perforation silicon intermediary layer is installed on package substrate.The method for packing process complexity is relatively low, advantageously reduces production cost and improves encapsulation yield.
Description
Technical field
The invention belongs to field of semiconductor package, is related to a kind of method for packing of three-dimensional chip encapsulating structure.
Background technology
Semi-conductor industry is close to continue to improve the integration of various electronic component by lasting reduction minimum feature size
Degree so that can integrate more electronic components under given area.At present, state-of-the-art encapsulation solution includes wafer
Level chip scale package (Wafer level chip-scale package), fan-out-type wafer-level packaging (Fan-out wafer
Level package) flip-chip (Flip chip) and stack type package (Package on Package, POP) etc..
Traditional fan-out-type wafer-level packaging (Fan-out wafer level packaging, FOWLP) generally comprise as
Under several steps：Single microchip is cut from wafer, and picked up using standard and to put equipment chip front side is pasted to load down first
On the adhesive-layer of body；Then plastic packaging layer is formed, chip is embedded in plastic packaging layer；After the solidification of plastic packaging layer, carrier and viscose glue are removed
Layer, then carry out redistributing lead layer process and plant ball reflux technique, finally cut and tested.Redistribute trace layer
(Redistribution Layers, RDL) is the connection interface between flip-chip assembly chips and encapsulation.Redistribution is drawn
Line layer is an extra metal level, is made up of core metal top trace, all for the I/O pads of nude film to be outwards tied to
Such as bump pad other positions.Salient point generally arranges that each salient point is cast with two pads, and (one is being pushed up with comb mesh pattern
Portion, one in bottom), they connect redistribution trace layer and package substrate respectively.Traditional fan-out-type wafer-level packaging is easy
Cause to shift between chip and RDL layer, cause yield relatively low.
Stack type package (Package on Package, PoP) can make the multiple chips of vertical stack in single package body,
The logical sum being longitudinally separated storage ball grid array is combined, by standard interface come transmission signal between each packaging body of stacking,
So as to realize the multiplication of component density, single package body is realized more functions, be widely used in mobile phone, personal digital assistant
(PDA), the field such as digital camera.
In Advanced Packaging, silicon hole technology (Through-silicon via, TSV) has significant impact, and it is to penetrate base
The vertical electric connection technology of piece (particularly silicon chip).TSV can almost replace the wire bonding (Wire- in all encapsulation
Bonding place), the electric property of all kinds chip package is improved, including improves integrated level, reduce chip size, it is special
It is not to encapsulate (System-in-Packaging, SiP) in system collection, wafer level packaging (Wafer-Level Packaging-
WLP) and among three-dimensional perpendicular stacked package (3D Packaging) these Advanced Packagings.TSV manufacture includes through hole
Manufacture, the deposition of insulating barrier and connect up techniques such as (RDL) at the filling of through hole and follow-up CMP (CMP) again.
Traditional stack type package is related to TSV techniques, it is necessary to the manufacturing process of a series of complex, cause higher production cost and compared with
Low yield.
Therefore, how a kind of new three-dimensional chip encapsulating structure and its method for packing are provided, to improve I/O density, is reduced
Production cost, yield is improved, turns into those skilled in the art's important technological problems urgently to be resolved hurrily.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of three-dimensional chip encapsulating structure and
Its method for packing, for solving the problems, such as that encapsulating structure I/O density of the prior art is low, method for packing is complicated.
In order to achieve the above objects and other related objects, the present invention provides a kind of encapsulation side of three-dimensional chip encapsulating structure
Method, comprise the following steps：
One bearing substrate is provided；
In forming adhesion layer on the bearing substrate；
In adhesion perforation silicon intermediary layer on the adhesion layer, the perforation silicon intermediary layer include insulated substrate and it is multiple up and down
Through the conductive pole of the insulated substrate；
At least one nude film is provided, the nude film face down is installed on the perforation silicon intermediary layer；
In the plastic packaging layer that the covering nude film and the perforation silicon intermediary layer are formed on the adhesion layer；
The bearing substrate and adhesion layer are removed, obtains including perforation silicon intermediary layer, the nude film and the plastic packaging
The three-dimensional chip module of layer；
One package substrate is provided, there is the one side of the perforation silicon intermediary layer to be installed in the three-dimensional chip module described
On package substrate.
Alternatively, there is gap between the three-dimensional chip module and the package substrate；By the three-dimensional chip module
After being installed on the package substrate, also it is included in the gap the step of forming protective layer.
Alternatively, after the perforation silicon intermediary layer is adhered on the adhesion layer, also it is included in the perforation silicon intermediary
The step of re-wiring layer being formed on layer, so that the nude film is electrical by the re-wiring layer and the perforation silicon intermediary layer
Connection.
Alternatively, the re-wiring layer includes at least one layer of patterned dielectric layer and at least one layer of patterned metal
Wiring layer.
Alternatively, the front of the nude film carries conductive projection, the nude film by the conductive projection with it is described again
Wiring layer is electrically connected with.
Alternatively, after re-wiring layer is formed on the perforation silicon intermediary layer, also it is included in the re-wiring layer
The step of upper formation projection cube structure, so that the nude film is electrically connected with by the projection cube structure and the re-wiring layer.
Alternatively, the projection cube structure includes metal column and the solder bump being connected to above the conductive pole, Huo Zhesuo
Stating projection cube structure only includes solder bump.
Alternatively, the one side of the conductive pole towards the adhesion layer is connected with conductive salient point, in viscous on the adhesion layer
During attached perforation silicon intermediary layer, the conductive salient point is embedded in the adhesion layer.
Alternatively, the perforation silicon intermediary layer is obtained by cutting perforation silicon intermediary wafer.
The present invention also provides a kind of three-dimensional chip encapsulating structure, including package substrate and is electrically connected at the package substrate
The three-dimensional chip module of top, wherein, the three-dimensional chip module includes：
Perforation silicon intermediary layer, including insulated substrate and multiple conductive poles for running through the insulated substrate up and down, the conduction
Post is electrically connected with the package substrate；
At least one nude film, the nude film face down are installed on the perforation silicon intermediary layer；
Plastic packaging layer, cover the nude film and the perforation silicon intermediary layer.
Alternatively, there is gap, formed with guarantor in the gap between the three-dimensional chip module and the package substrate
Sheath.
Alternatively, formed with re-wiring layer between the nude film and the perforation silicon intermediary layer, so that the nude film leads to
The re-wiring layer is crossed to be electrically connected with the perforation silicon intermediary layer.
Alternatively, the re-wiring layer includes at least one layer of patterned dielectric layer and at least one layer of patterned metal
Wiring layer.
Alternatively, the front of the nude film carries conductive projection, the nude film by the conductive projection with it is described again
Wiring layer is electrically connected with.
Alternatively, be provided with projection cube structure on the re-wiring layer so that the nude film by the projection cube structure with
The re-wiring layer is electrically connected with；The solder that the projection cube structure includes metal column and is connected to above the metal column is convex
Point, or the projection cube structure only include solder bump.
Alternatively, the conductive pole is electrically connected with by conductive salient point and the package substrate.
As described above, the three-dimensional chip encapsulating structure and its method for packing of the present invention, have the advantages that：The present invention
Three-dimensional chip encapsulating structure using package substrate, TSI perforation silicon intermediary layer, the packing forms of die stack, and use plastic packaging
Layer realizes the protection of nude film, wherein, nude film can be connected with TSI perforation silicon intermediary layers by conductive projection and re-wiring layer.This
The three-dimensional chip encapsulating structure of invention has the advantages of simple in construction, higher I/O density, faster efficiency of transmission.The three of the present invention
The method for packing of dimension chip-packaging structure adheres to TSI perforation silicon intermediary layers first on bearing substrate, is then just facing nude film
Under be installed on the perforation silicon intermediary layer, and cover the nude film and the perforation silicon intermediary layer in being formed on the adhesion layer
Plastic packaging layer, then remove the bearing substrate and adhesion layer, obtain including the perforation silicon intermediary layer, the nude film and described
The three-dimensional chip module of plastic packaging layer, finally provides a package substrate, and the three-dimensional chip module is had into the perforation silicon intermediary
The one side of layer is installed on the package substrate.The present invention three-dimensional chip encapsulating structure method for packing process complexity compared with
It is low, advantageously reduce production cost and improve encapsulation yield.
Brief description of the drawings
Fig. 1 is shown as the process chart of the method for packing of the three-dimensional chip encapsulating structure of the present invention.
Fig. 2 is shown as the schematic diagram of method for packing one bearing substrate of offer of the three-dimensional chip encapsulating structure of the present invention.
Fig. 3 is shown as the method for packing of the three-dimensional chip encapsulating structure of the present invention in forming adhesion layer on the bearing substrate
Schematic diagram.
Fig. 4 is shown as the method for packing of the three-dimensional chip encapsulating structure of the present invention in adhesion perforation silicon on the adhesion layer
The schematic diagram of interlayer.
The method for packing that Fig. 5 is shown as the three-dimensional chip encapsulating structure of the present invention is obtained by cutting perforation silicon intermediary wafer
The schematic diagram of the perforation silicon intermediary layer.
The method for packing that Fig. 6 is shown as the three-dimensional chip encapsulating structure of the present invention provides at least one nude film, will be described naked
Piece face down is installed in the schematic diagram on the perforation silicon intermediary layer.
Fig. 7 is shown as the method for packing of the three-dimensional chip encapsulating structure of the present invention in described in formation covering on the adhesion layer
The schematic diagram of the plastic packaging layer of nude film and the perforation silicon intermediary layer.
The method for packing that Fig. 8 is shown as the three-dimensional chip encapsulating structure of the present invention removes the bearing substrate and adhesion layer,
Obtain the schematic diagram for including the three-dimensional chip module of the perforation silicon intermediary layer, the nude film and the plastic packaging layer.
The method for packing that Fig. 9 is shown as the three-dimensional chip encapsulating structure of the present invention provides a package substrate, by the three-dimensional
There is chip module the one side of the perforation silicon intermediary layer to be installed in the schematic diagram on the package substrate.
Figure 10 be shown as the present invention three-dimensional chip encapsulating structure method for packing in the three-dimensional chip module with it is described
The schematic diagram of protective layer is formed in gap between package substrate.
Component label instructions
S1~S7 steps
1 bearing substrate
2 adhesion layers
3 perforation silicon intermediary layers
301 insulated substrates
302 conductive poles
303 conductive salient points
4 perforation silicon intermediary wafers
5 nude films
6 conductive projections
7 plastic packaging layers
8 package substrates
9 soldered balls
10 protective layers
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Fig. 1 is referred to Figure 10.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, the component relevant with the present invention is only shown in schema then rather than according to package count during actual implement
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
The present invention provides a kind of method for packing of three-dimensional chip encapsulating structure, referring to Fig. 1, being shown as the method for packing
Process chart, comprise the following steps：
As shown in Fig. 2 perform step S1：One bearing substrate 1 is provided.
Specifically, the bearing substrate 1, which can be follow-up making adhesion layer 2 and adhesion perforation silicon intermediary layer 3, provides rigidity
Structure or matrix, its material may be selected from least one of metal, semiconductor (such as Si), polymer or glass.As showing
Example, the carrier 1 select glass.
As shown in figure 3, perform step S2：In formation adhesion layer 2 on the bearing substrate 1.
Specifically, the adhesion layer 2 in subsequent technique as perforation silicon intermediary layer 3 and bearing substrate 1 between separation
Layer, it is preferably made from the jointing material with smooth finish surface, and its silicon intermediary layer 3 of must and perforating has certain combination
Power, to ensure that perforation silicon intermediary layer 3 will not produce situations such as mobile in subsequent technique, in addition, it also has with bearing substrate 1
Stronger adhesion, in general, the adhesion of itself and bearing substrate 1 need to be more than the adhesion with silicon intermediary layer of perforating.Institute
It can be single or multiple lift structure to state adhesion layer 2, be the situation of double-decker shown in Fig. 3.As an example, the adhesion layer 2
Material be selected from the two-sided adhesive tape for being respectively provided with viscosity or the adhesive glue etc. made by spin coating proceeding.The adhesive tape preferably uses UV
Adhesive tape, it is easy to pull off after UV light irradiations.
As shown in figure 4, perform step S3：In (the Through Silicon of adhesion perforation silicon intermediary layer 3 on the adhesion layer 2
Interposer, abbreviation TSI), the perforation silicon intermediary layer 3 includes insulated substrate 301 and multiple runs through the insulation base up and down
The conductive pole 302 of plate.
Specifically, as shown in figure 5, the perforation silicon intermediary layer 3 can be obtained by cutting perforation silicon intermediary wafer 4.
As an example, the one side of the conductive pole 302 towards the adhesion layer 2 is connected with conductive salient point 303, in described viscous
When the perforation silicon intermediary layer 3 is adhered on attached layer 2, the conductive salient point 303 is embedded in the adhesion layer 2.
As shown in fig. 6, perform step S4：At least one nude film 5 (Die) is provided, the face down of nude film 5 is installed in
On the perforation silicon intermediary layer 3.Herein, the front of the nude film 5 refers to that the nude film 5 is drawn formed with device and electrode
One side.
Specifically, the type and quantity of the nude film 5 can variations.For example, the nude film 5 includes but is not limited to store
The devices such as device, display device, input module, discrete component, power supply, voltage-stablizer.The quantity of the nude film 5 can be one or
It is multiple, until the quantity of nude film 5 that a perforation silicon intermediary layer 3 can carry.
As an example, in above-mentioned steps S3 after the perforation silicon intermediary layer 3 is adhered on the adhesion layer 2, in addition to
In the step that re-wiring layer (Redistribution layer, abbreviation RDL) (not shown) is formed on the perforation silicon intermediary layer 3
Suddenly, so that the nude film 5 is electrically connected with by the re-wiring layer and the perforation silicon intermediary layer 3.
As an example, the re-wiring layer is made as alternately following steps：Using chemical vapor deposition method or
Physical gas-phase deposition performs etching to form figure in forming dielectric layer on the perforation silicon intermediary layer 3 to the dielectric layer
The dielectric layer of shape；Using physical gas-phase deposition, chemical vapor deposition method, evaporation process, sputtering technology, electroplating technology
Or chemical plating process in patterned dielectric layer surface formed metal level, and the metal level is performed etching to be formed it is patterned
Metal wiring layer, the metal wiring layer is with passing through patterned dielectric layer, to be electrical connected with the perforation silicon intermediary layer 3.
The material of the dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, one kind in fluorine-containing glass
Or two or more combinations, the material of the metal wiring layer include one or both of copper, aluminium, nickel, gold, silver, titanium above group
Close.
Specifically, the re-wiring layer includes at least one layer of patterned dielectric layer and at least one layer of patterned metal
Wiring layer.That is, the re-wiring layer can include the multiple dielectric layers stacked gradually and multiple metal wiring layers,
According to line demand, by each dielectric layer is patterned or made through hole realize it is mutual between each layer metal wiring layer
Even, to realize the line demand of difference in functionality.
Specifically, the nude film 5 can be the nude film (Bumped Die) that front carries conductive projection 6, the nude film leads to
The conductive projection is crossed to be electrically connected with the re-wiring layer.
As an example, will be with projection nude film (Bumped by engaging (bond-on-trace, abbreviation BOT) method on trace
Die) it is bonded on re-wiring layer.The material of the conductive projection can include but is not limited to copper (Cooper), nickel
(Nickel), Xi Yin (Tin-Silver).
In another embodiment, after re-wiring layer is formed on the perforation silicon intermediary layer 3, also it is included in described heavy
The step of projection cube structure being formed on new route layer, so that the nude film 5 passes through the projection cube structure and re-wiring layer electricity
Property connection.
As an example, the preparation method of the projection cube structure includes step：A) using galvanoplastic in the re-wiring layer
The metal line layer surface that top is exposed forms copper post；B) using galvanoplastic in the copper post surface formed metal barrier (
Metal barrier can not be made)；C) solder metal is formed in the metal barrier layer surface using galvanoplastic, and is returned using high temperature
Flow technique and form solder bump in the metal barrier layer surface.Further, the metal barrier includes nickel dam, the weldering
The material of material salient point includes one kind in lead, tin and silver or includes the alloy of any one above-mentioned solder metal.
In other embodiments, the projection cube structure can also only include solder bump, for example, the projection cube structure is tin
Ball, directly it is made in the metal line layer surface exposed at the top of the re-wiring layer.
As shown in fig. 7, performing step S5, the nude film 5 and the perforation silicon intermediary are covered in being formed on the adhesion layer 2
The plastic packaging layer 7 of layer 3.
Specifically, the plastic packaging layer 7 is used to protect the nude film 5 and the perforation silicon intermediary layer 3 so that encapsulating structure is not
Easily split.As an example, the plastic packaging layer 7 select in thermosets, such as silica gel, epoxy resin, polyimides one
The conventional capsulation materials such as kind.The method for forming the plastic packaging layer 7 may be selected from but be not limited to compression molding (compressive
Molding (paste printing), transfer molding (transfer molding), hydraulic seal shaping (liquid), are printed
Encapsulant molding), vacuum pressing-combining (vacuum lamination), spin coating (spin coating) the methods of in
Any one.
For example, transfer molding (transfer molding) is one of manufacturing process of plastics, it is by the gold after closure
Belonging to model heating, the method for being allowed to hardening shaping from tubule cast gate press-in molten resin is high compared with the forming accuracy of compression molding,
And the formed products of extremely complex shape can be generated.And loading resin progress once-through operation can be simultaneously in the gold of connection at one
Several formed products are obtained in category mould.This manufacturing process is mainly used in phenolic resin, urea resin, melamine, epoxy resin with gathering
The shaping of the thermosetting resins such as ester, so the also referred to as injection pressure shaping of thermosetting resin.
As shown in figure 8, perform step S6：The bearing substrate 1 and adhesion layer 2 are removed, obtains including in the perforation silicon
The three-dimensional chip module of interlayer 3, the nude film 5 and the plastic packaging layer 7.
Specifically, separate the adhesion layer 2 is selected from, but not limited to, chemical corruption with perforation silicon intermediary layer 3, the method for plastic packaging layer 7
In erosion, mechanical stripping, mechanical lapping, hot baking, ultraviolet light, laser ablation, chemically mechanical polishing and wet method stripping extremely
Few one kind.If for example, the adhesion layer 2 uses UV adhesive tapes, the UV adhesive tapes viscosity drop can be made using ultraviolet light first
It is low, the bearing substrate 1 and the adhesion layer 2 is departed from the perforation silicon intermediary layer 3 and plastic packaging by way of tearing off
Layer 7, relative to reduction process, such as grind, for corrosion, this separation method is more simple, easily operated, can drop significantly
Low process costs.
As shown in figure 9, perform step S7：One package substrate 8 is provided, the three-dimensional chip module is had into the perforation silicon
The one side of intermediary layer 3 is installed on the package substrate 8.
Specifically, the package substrate 8 includes but is not limited to pcb board, conductive interconnecting structure is provided with, the back side, which is provided with, draws
Go out the soldered ball 9 of conductive interconnecting structure.
Specifically, after the three-dimensional chip module is installed on the package substrate 8, the three-dimensional chip module with
There is gap between the package substrate 8；In the method for packing of the three-dimensional chip encapsulating structure of the present invention, by the three-dimensional chip
After module is installed on the package substrate 8, also it is included in the gap the step of forming protective layer 10 (such as Figure 10 institutes
Show).The protective layer 10 can use polymeric material, and it surrounds the conductive salient point 303, on the one hand can increase the conductive stud
Bond strength between point 303 and the package substrate 8, prevents it from rocking or dropping, on the other hand it can be protected,
The influence to conductive salient point 303 and the package substrate of lower section 8 such as anti-oxidation and steam.
So far, the encapsulation of three-dimensional chip encapsulating structure is completed.The method for packing of the three-dimensional chip encapsulating structure of the present invention
TSI perforation silicon intermediary layers are adhered to first on bearing substrate, nude film face down is then installed in the perforation silicon intermediary layer
On, and in the plastic packaging layer that the covering nude film and the perforation silicon intermediary layer are formed on the adhesion layer, then held described in removal
Carried base board and adhesion layer, the three-dimensional chip module for including the perforation silicon intermediary layer, the nude film and the plastic packaging layer is obtained, most
After a package substrate is provided, by the three-dimensional chip module have it is described perforation silicon intermediary layer one side be installed in the encapsulation base
On plate.The method for packing process complexity of the three-dimensional chip encapsulating structure of the present invention is relatively low, advantageously reduces production cost and carries
Height encapsulation yield.
Embodiment two
The present invention also provides a kind of three-dimensional chip encapsulating structure, as shown in Figure 10, is shown as the three-dimensional chip encapsulating structure
Structural representation, including package substrate 8 and the three-dimensional chip module for being electrically connected at the top of the package substrate 8, wherein, institute
Stating three-dimensional chip module includes：
Perforation silicon intermediary layer 3, including insulated substrate 301 and multiple conductive poles for running through the insulated substrate 301 up and down
302, the conductive pole 302 is electrically connected with the package substrate 8；
At least one nude film 5, the face down of nude film 5 are installed on the perforation silicon intermediary layer 3；
Plastic packaging layer 7, cover the nude film 5 and the perforation silicon intermediary layer 3.
As an example, the package substrate 8 includes but is not limited to pcb board, conductive interconnecting structure is provided with, the back side is provided with
Draw the soldered ball 9 of conductive interconnecting structure.
As an example, have gap between the three-dimensional chip module and the package substrate 8, in the gap formed with
Protective layer 10.The protective layer 10 can use polymeric material, and it surrounds the conductive salient point 303, on the one hand can increase described
Bond strength between conductive salient point 303 and the package substrate 8, prevent it from rocking or dropping, on the other hand it can be entered
Row protection, the influence to conductive salient point 303 and the package substrate of lower section 8 such as anti-oxidation and steam
It is pointed out that the front of the nude film 5 refers to one that the nude film 5 is drawn formed with device and electrode
Face.As an example, formed with re-wiring layer between the nude film 5 and the perforation silicon intermediary layer 3, so that the nude film logical 5
The re-wiring layer is crossed to be electrically connected with the perforation silicon intermediary layer 3.The re-wiring layer may include at least one layer of figure
The dielectric layer of change and at least one layer of patterned metal wiring layer.For example, the re-wiring layer can include what is stacked gradually
Multiple dielectric layers and multiple metal wiring layers are logical by the way that each dielectric layer is patterned or made according to line demand
The interconnection between each layer metal wiring layer is realized in hole, to realize the line demand of difference in functionality.
As an example, the type and quantity of the nude film 5 can variations.For example, the nude film 5 includes but is not limited to deposit
The devices such as memory device, display device, input module, discrete component, power supply, voltage-stablizer.The quantity of the nude film 5 can be one
Or it is multiple, until the quantity of nude film 5 that a perforation silicon intermediary layer 3 can carry.
As an example, the nude film 5 can be the nude film (Bumped Die) that front carries conductive projection 6, the nude film
It is electrically connected with by the conductive projection 6 and the re-wiring layer.
As an example, projection cube structure (not shown) is provided with the re-wiring layer, so that the nude film 5 is by described
Projection cube structure is electrically connected with the re-wiring layer.The projection cube structure includes metal column and is connected to above the metal column
Solder bump, or the projection cube structure only includes solder bump.
As an example, the conductive pole 302 is electrically connected with by conductive salient point 303 and the package substrate.
The three-dimensional chip encapsulating structure of the present invention is using package substrate, TSI perforation silicon intermediary layer, the encapsulation shape of die stack
Formula, and the protection of nude film is realized using plastic packaging layer, wherein, nude film and TSI perforation silicon intermediary layer can by conductive projection and again
Wiring layer connects.The three-dimensional chip encapsulating structure of the present invention has simple in construction, higher I/O density, faster efficiency of transmission is excellent
Point.
In summary, the method for packing of three-dimensional chip encapsulating structure of the invention adheres to TSI first on bearing substrate and worn
Hole silicon intermediary layer, then nude film face down is installed on the perforation silicon intermediary layer, and covered in being formed on the adhesion layer
The plastic packaging layer of the nude film and the perforation silicon intermediary layer is covered, the bearing substrate and adhesion layer is then removed, obtains including institute
The three-dimensional chip module of perforation silicon intermediary layer, the nude film and the plastic packaging layer is stated, a package substrate is finally provided, by described three
The one side that dimension chip module has the perforation silicon intermediary layer is installed on the package substrate.The three-dimensional chip encapsulation of the present invention
The method for packing process complexity of structure is relatively low, advantageously reduces production cost and improves encapsulation yield.The three-dimensional core of the present invention
Chip package is using package substrate, TSI perforation silicon intermediary layer, the packing forms of die stack, and it is naked to use plastic packaging layer to realize
The protection of piece, wherein, nude film can be connected with TSI perforation silicon intermediary layers by conductive projection and re-wiring layer.The three of the present invention
Dimension chip-packaging structure has the advantages of simple in construction, higher I/O density, faster efficiency of transmission.So the present invention effectively overcomes
Various shortcoming of the prior art and have high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (16)
1. a kind of method for packing of three-dimensional chip encapsulating structure, it is characterised in that comprise the following steps：
One bearing substrate is provided；
In forming adhesion layer on the bearing substrate；
In adhesion perforation silicon intermediary layer on the adhesion layer, the perforation silicon intermediary layer includes insulated substrate and multiple run through up and down
The conductive pole of the insulated substrate；
At least one nude film is provided, the nude film face down is installed on the perforation silicon intermediary layer；
In the plastic packaging layer that the covering nude film and the perforation silicon intermediary layer are formed on the adhesion layer；
The bearing substrate and adhesion layer are removed, obtains including the perforation silicon intermediary layer, the nude film and the plastic packaging layer
Three-dimensional chip module；
One package substrate is provided, the one side that the three-dimensional chip module has the perforation silicon intermediary layer is installed in the encapsulation
On substrate.
2. the method for packing of three-dimensional chip encapsulating structure according to claim 1, it is characterised in that：The three-dimensional chip mould
There is gap between block and the package substrate；After the three-dimensional chip module is installed on the package substrate, also wrap
Include the step of protective layer is formed in the gap.
3. the method for packing of three-dimensional chip encapsulating structure according to claim 1, it is characterised in that：In on the adhesion layer
After adhering to the perforation silicon intermediary layer, also it is included in the step of forming re-wiring layer on the perforation silicon intermediary layer, so that
The nude film is electrically connected with by the re-wiring layer and the perforation silicon intermediary layer.
4. the method for packing of three-dimensional chip encapsulating structure according to claim 3, it is characterised in that：The re-wiring layer
Including at least one layer of patterned dielectric layer and at least one layer of patterned metal wiring layer.
5. the method for packing of three-dimensional chip encapsulating structure according to claim 3, it is characterised in that：The front of the nude film
With conductive projection, the nude film is electrically connected with by the conductive projection and the re-wiring layer.
6. the method for packing of three-dimensional chip encapsulating structure according to claim 3, it is characterised in that：In the perforation silicon
Formed on interlayer after re-wiring layer, be also included on the re-wiring layer the step of forming projection cube structure, so that described
Nude film is electrically connected with by the projection cube structure and the re-wiring layer.
7. the method for packing of three-dimensional chip encapsulating structure according to claim 6, it is characterised in that：The projection cube structure bag
Metal column and the solder bump being connected to above the conductive pole are included, or the projection cube structure only includes solder bump.
8. the method for packing of three-dimensional chip encapsulating structure according to claim 1, it is characterised in that：The conductive pole towards
The one side of the adhesion layer is connected with conductive salient point, when adhesion perforation silicon intermediary layer on the adhesion layer, the conductive salient point
In the embedded adhesion layer.
9. the method for packing of three-dimensional chip encapsulating structure according to claim 1, it is characterised in that：By cutting silicon of perforating
Intermediary's wafer obtains the perforation silicon intermediary layer.
10. a kind of three-dimensional chip encapsulating structure, including package substrate and the three-dimensional core that is electrically connected above the package substrate
Piece module, it is characterised in that the three-dimensional chip module includes：
Perforate silicon intermediary layer, including insulated substrate and it is multiple up and down run through the insulated substrate conductive pole, the conductive pole with
The package substrate is electrically connected with；
At least one nude film, the nude film face down are installed on the perforation silicon intermediary layer；
Plastic packaging layer, cover the nude film and the perforation silicon intermediary layer.
11. three-dimensional chip encapsulating structure according to claim 10, it is characterised in that：The three-dimensional chip module with it is described
There is gap between package substrate, matcoveredn is formed in the gap.
12. three-dimensional chip encapsulating structure according to claim 10, it is characterised in that：In the nude film and the perforation silicon
Formed with re-wiring layer between interlayer, so that the nude film is electrical by the re-wiring layer and the perforation silicon intermediary layer
Connection.
13. three-dimensional chip encapsulating structure according to claim 12, it is characterised in that：The re-wiring layer is included at least
The dielectric layer of one layer pattern and at least one layer of patterned metal wiring layer.
14. three-dimensional chip encapsulating structure according to claim 12, it is characterised in that：The front of the nude film is with conduction
Projection, the nude film are electrically connected with by the conductive projection and the re-wiring layer.
15. three-dimensional chip encapsulating structure according to claim 12, it is characterised in that：It is provided with the re-wiring layer
Projection cube structure, so that the nude film is electrically connected with by the projection cube structure and the re-wiring layer；The projection cube structure bag
Metal column and the solder bump being connected to above the metal column are included, or the projection cube structure only includes solder bump.
16. three-dimensional chip encapsulating structure according to claim 1, it is characterised in that：The conductive pole passes through conductive salient point
It is electrically connected with the package substrate.
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