CN207250493U - A kind of three-dimensional chip encapsulating structure - Google Patents
A kind of three-dimensional chip encapsulating structure Download PDFInfo
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- CN207250493U CN207250493U CN201721271536.2U CN201721271536U CN207250493U CN 207250493 U CN207250493 U CN 207250493U CN 201721271536 U CN201721271536 U CN 201721271536U CN 207250493 U CN207250493 U CN 207250493U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Abstract
The utility model provides a kind of three-dimensional chip encapsulating structure, including package substrate and the three-dimensional chip module that is electrically connected above the package substrate, wherein, the three-dimensional chip module includes：Perforation silicon intermediary layer, the perforation silicon intermediary layer include insulated substrate and multiple conductive columns for running through the insulated substrate up and down, and the conductive column and the package substrate are electrically connected；At least one nude film, the nude film face down are installed on the perforation silicon intermediary layer；Plastic packaging layer, covers the nude film and the perforation silicon intermediary layer.The encapsulating structure uses package substrate, perforation silicon intermediary layer, the packing forms of die stack, and the protection of nude film is realized using plastic packaging layer, wherein, nude film can be connected with perforation silicon intermediary layer by conductive bump and re-wiring layer.The encapsulating structure has the advantages that simple in structure, higher I/O density, faster efficiency of transmission, and process complexity is relatively low in its manufacturing process, advantageously reduces production cost and improves encapsulation yield.
Description
Technical field
The utility model belongs to field of semiconductor package, is related to a kind of method for packing of three-dimensional chip encapsulating structure.
Background technology
Semi-conductor industry is close to continue to improve the integration of various electronic component by lasting reduction minimum feature size
Degree so that can integrate more electronic components under given area.At present, state-of-the-art encapsulation solution includes wafer
Level chip scale package (Wafer level chip-scale package), fan-out-type wafer-level packaging (Fan-out wafer
Level package) flip-chip (Flip chip) and stack type package (Package on Package, POP) etc..
Traditional fan-out-type wafer-level packaging (Fan-out wafer level packaging, FOWLP) generally comprise as
Under several steps：Single microchip is cut from wafer, and picked up using standard and to put equipment chip front side is pasted to load downward first
On the adhesive-layer of body；Then plastic packaging layer is formed, chip is embedded in plastic packaging layer；After the curing of plastic packaging layer, carrier and viscose glue are removed
Layer, then carries out redistribution lead layer process and plants ball reflux technique, finally cut and tested.Redistribute trace layer
(Redistribution Layers, RDL) is the connection interface between flip-chip assembly chips and encapsulation.Redistribution is drawn
Line layer is an extra metal layer, is made of core metal top trace, all for the I/O pads of nude film to be outwards tied to
Such as bump pad other positions.Salient point usually arranges that each salient point is cast with two pads, and (one is being pushed up with comb mesh pattern
Portion, one in bottom), they connect redistribution trace layer and package substrate respectively.Traditional fan-out-type wafer-level packaging is easy
Cause to shift between chip and RDL layer, cause yield relatively low.
Stack type package (Package on Package, PoP) can make the multiple chips of vertical stack in single package body,
The logic being longitudinally separated and storage ball grid array are combined, by standard interface come transmission signal between each packaging body of stacking,
So as to fulfill the multiplication of component density, single package body is realized more functions, be widely used in mobile phone, personal digital assistant
(PDA), the field such as digital camera.
In Advanced Packaging, silicon hole technology (Through-silicon via, TSV) has significant impact, it is to penetrate base
The vertical electric connection technology of piece (particularly silicon chip).TSV can almost replace the wire bonding (Wire- in all encapsulation
Bonding place), improves the electric property of all kinds chip package, including improves integrated level, reduces chip size, special
It is not to encapsulate (System-in-Packaging, SiP) in system collection, wafer level packaging (Wafer-Level Packaging-
WLP) and among three-dimensional perpendicular stacked package (3D Packaging) these Advanced Packagings.The manufacture of TSV includes through hole
Manufacture, the deposition of insulating layer and connect up techniques such as (RDL) at the filling of through hole and follow-up chemical mechanical planarization (CMP) again.
Traditional stack type package is related to TSV techniques, it is necessary to the manufacturing process of a series of complex, cause higher production cost and compared with
Low yield.
Therefore, how a kind of new three-dimensional chip encapsulating structure is provided, to improve I/O density, reduces production cost, improves
Yield, becomes those skilled in the art's important technological problems urgently to be resolved hurrily.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of encapsulation of three-dimensional chip to tie
Structure, for solving the problems, such as that encapsulating structure I/O density of the prior art is low, method for packing is complicated.
In order to achieve the above objects and other related objects, the utility model provides a kind of three-dimensional chip encapsulating structure, including
Package substrate and the three-dimensional chip module being electrically connected above the package substrate, wherein, the three-dimensional chip module includes：
Perforation silicon intermediary layer, including insulated substrate and multiple conductive columns for running through the insulated substrate up and down, the conduction
Column is electrically connected with the package substrate；
At least one nude film, the nude film face down are installed on the perforation silicon intermediary layer；
Plastic packaging layer, covers the nude film and the perforation silicon intermediary layer.
Alternatively, there is gap, formed with guarantor in the gap between the three-dimensional chip module and the package substrate
Sheath.
Alternatively, formed with re-wiring layer between the nude film and the perforation silicon intermediary layer, so that the nude film leads to
The re-wiring layer is crossed to be electrically connected with the perforation silicon intermediary layer.
Alternatively, the re-wiring layer includes at least one layer of patterned dielectric layer and at least one layer of patterned metal
Wiring layer.
Alternatively, the front of the nude film carries conductive bump, the nude film by the conductive bump with it is described again
Wiring layer is electrically connected.
Alternatively, be provided with projection cube structure on the re-wiring layer so that the nude film by the projection cube structure with
The re-wiring layer is electrically connected.
Alternatively, the projection cube structure includes metal column and the solder bump being connected to above the metal column.
Alternatively, the projection cube structure only includes solder bump.
Alternatively, the conductive column is electrically connected by conductive salient point and the package substrate.
Alternatively, the package substrate back side is equipped with multiple soldered balls.
As described above, the three-dimensional chip encapsulating structure of the utility model, has the advantages that：The three of the utility model
Chip-packaging structure is tieed up using package substrate, TSI perforation silicon intermediary layer, the packing forms of die stack, and using plastic packaging layer reality
The protection of existing nude film, wherein, nude film can be connected with TSI perforation silicon intermediary layers by conductive bump and re-wiring layer.This practicality
New three-dimensional chip encapsulating structure has the advantages that simple in structure, higher I/O density, faster efficiency of transmission, and it made
Process complexity is relatively low in journey, advantageously reduces production cost and improves encapsulation yield.
Brief description of the drawings
Fig. 1 is shown as a kind of process flow chart of the method for the three-dimensional chip encapsulating structure for making the utility model.
Fig. 2 is shown as the schematic diagram that the method provides a bearing substrate.
Fig. 3 is shown as the method in the schematic diagram that adhesion layer is formed on the bearing substrate.
Fig. 4 is shown as the method in the schematic diagram of adhesion perforation silicon intermediary layer on the adhesion layer.
Fig. 5 is shown as the method and obtains the schematic diagram of the perforation silicon intermediary layer by cutting perforation silicon intermediary wafer.
Fig. 6 is shown as the method and provides at least one nude film, and the nude film face down is installed in the perforation silicon
Schematic diagram on intermediary layer.
Fig. 7 is shown as the method in the modeling that the covering nude film and the perforation silicon intermediary layer are formed on the adhesion layer
The schematic diagram of sealing.
Fig. 8 is shown as the method and removes the bearing substrate and adhesion layer, obtains including the perforation silicon intermediary layer, institute
State the schematic diagram of the three-dimensional chip module of nude film and the plastic packaging layer.
Fig. 9 is shown as the method and provides a package substrate, and the three-dimensional chip module is had the perforation silicon intermediary
The one side of layer is installed in the schematic diagram on the package substrate.
Figure 10 is shown as being formed in gap of the method between the three-dimensional chip module and the package substrate and protects
The schematic diagram of sheath.
Component label instructions
S1~S7 steps
1 bearing substrate
2 adhesion layers
3 perforation silicon intermediary layers
301 insulated substrates
302 conductive columns
303 conductive salient points
4 perforation silicon intermediary wafers
5 nude films
6 conductive bumps
7 plastic packaging layers
8 package substrates
9 soldered balls
10 protective layers
Embodiment
Illustrate the embodiment of the utility model below by way of specific instantiation, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints with answering
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Please refer to Fig.1 to Figure 10.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, the then only display component related with the utility model rather than during according to actual implementation in schema
Component count, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation
Become, and its assembly layout kenel may also be increasingly complex.
Embodiment one
The utility model provides a kind of three-dimensional chip encapsulating structure, as shown in Figure 10, is shown as three-dimensional chip encapsulation knot
The structure diagram of structure, including package substrate 8 and the three-dimensional chip module for being electrically connected at the top of package substrate 8, wherein,
The three-dimensional chip module includes：
Perforation silicon intermediary layer 3, including insulated substrate 301 and multiple conductive columns for running through the insulated substrate 301 up and down
302, the conductive column 302 is electrically connected with the package substrate 8；
At least one nude film 5,5 face down of nude film are installed on the perforation silicon intermediary layer 3；
Plastic packaging layer 7, covers the nude film 5 and the perforation silicon intermediary layer 3.
As an example, the package substrate 8 includes but not limited to pcb board, conductive interconnecting structure is provided with, the back side is equipped with
Draw the soldered ball 9 of conductive interconnecting structure.
As an example, have gap between the three-dimensional chip module and the package substrate 8, in the gap formed with
Protective layer 10.The protective layer 10 can use polymeric material, it surrounds the conductive salient point 303, on the one hand can increase described
Bond strength between conductive salient point 303 and the package substrate 8, prevents it from rocking or dropping, on the other hand can to its into
Row protection, prevents the influence to the package substrate 8 of conductive salient point 303 and lower section such as oxidation and steam.
It is pointed out that the front of the nude film 5 refers to one that the nude film 5 is drawn formed with device and electrode
Face.As an example, formed with re-wiring layer between the nude film 5 and the perforation silicon intermediary layer 3, so that the nude film leads to 5
The re-wiring layer is crossed to be electrically connected with the perforation silicon intermediary layer 3.The re-wiring layer may include at least one layer of figure
The dielectric layer of change and at least one layer of patterned metal wiring layer.For example, the re-wiring layer can include what is stacked gradually
Multiple dielectric layers and multiple metal wiring layers are logical by the way that each dielectric layer is patterned or is made according to line demand
The interconnection between each layer metal wiring layer is realized in hole, to realize the line demand of difference in functionality.
As an example, the type and quantity of the nude film 5 can variations.For example, the nude film 5 includes but not limited to deposit
The devices such as memory device, display device, input module, discrete component, power supply, voltage-stablizer.The quantity of the nude film 5 can be one
Or it is multiple, until 5 quantity of nude film that a perforation silicon intermediary layer 3 can carry.
As an example, the nude film 5 can be the nude film (Bumped Die) that front carries conductive bump 6, the nude film
It is electrically connected by the conductive bump 6 and the re-wiring layer.
As an example, projection cube structure (not shown) is provided with the re-wiring layer, so that the nude film 5 is by described
Projection cube structure is electrically connected with the re-wiring layer.The projection cube structure includes metal column and is connected to above the metal column
Solder bump, or the projection cube structure only includes solder bump.
As an example, the conductive column 302 is electrically connected by conductive salient point 303 and the package substrate.
The three-dimensional chip encapsulating structure of the utility model is using package substrate, TSI perforation silicon intermediary layer, the envelope of die stack
Dress form, and the protection of nude film is realized using plastic packaging layer, wherein, nude film and TSI perforation silicon intermediary layer can by conductive bump and
Re-wiring layer connects.The three-dimensional chip encapsulating structure of the utility model has simple in structure, higher I/O density, faster transmits
The advantages of efficiency.
Embodiment two
The present embodiment provides a kind of method for the encapsulating structure for making the utility model, referring to Fig. 1, being shown as this method
Process flow chart, comprise the following steps：
As shown in Fig. 2, perform step S1：One bearing substrate 1 is provided.
Specifically, the bearing substrate 1, which can be follow-up making adhesion layer 2 and adhesion perforation silicon intermediary layer 3, provides rigidity
Structure or matrix, its material may be selected from least one of metal, semiconductor (such as Si), polymer or glass.As showing
Example, the carrier 1 select glass.
As shown in figure 3, perform step S2：In formation adhesion layer 2 on the bearing substrate 1.
Specifically, the adhesion layer 2 in subsequent technique as perforation silicon intermediary layer 3 and bearing substrate 1 between separation
Layer, it preferably selects the jointing material with smooth finish surface to be made, its silicon intermediary layer 3 of must and perforating has certain combination
Power, to ensure that perforation silicon intermediary layer 3 will not produce situations such as mobile in subsequent technique, in addition, it also has with bearing substrate 1
Stronger combination power, in general, the combination power of itself and bearing substrate 1 needs to be more than and the combination power for silicon intermediary layer of perforating.Institute
It can be single or multi-layer structure to state adhesion layer 2, be the situation of double-decker shown in Fig. 3.As an example, the adhesion layer 2
Material be selected from the two-sided adhesive tape for being respectively provided with viscosity or the adhesive glue etc. made by spin coating proceeding.The adhesive tape preferably uses UV
Adhesive tape, it is easy to pull off after the irradiation of UV light.
As shown in figure 4, perform step S3：In 3 (Through Silicon of adhesion perforation silicon intermediary layer on the adhesion layer 2
Interposer, abbreviation TSI), the perforation silicon intermediary layer 3 includes insulated substrate 301 and multiple runs through the insulation base up and down
The conductive column 302 of plate.
Specifically, as shown in figure 5, the perforation silicon intermediary layer 3 can be obtained by cutting perforation silicon intermediary wafer 4.
As an example, the one side of the conductive column 302 towards the adhesion layer 2 is connected with conductive salient point 303, in described viscous
When the perforation silicon intermediary layer 3 is adhered on attached layer 2, the conductive salient point 303 is embedded in the adhesion layer 2.
As shown in fig. 6, perform step S4：At least one nude film 5 (Die) is provided, 5 face down of nude film is installed in
On the perforation silicon intermediary layer 3.Herein, the front of the nude film 5 refers to that the nude film 5 is drawn formed with device and electrode
One side.
Specifically, the type and quantity of the nude film 5 can variations.For example, the nude film 5 includes but not limited to store
The devices such as device, display device, input module, discrete component, power supply, voltage-stablizer.The quantity of the nude film 5 can be one or
It is multiple, until 5 quantity of nude film that a perforation silicon intermediary layer 3 can carry.
As an example, further included in above-mentioned steps S3 after the perforation silicon intermediary layer 3 is adhered on the adhesion layer 2
In the step that re-wiring layer (Redistribution layer, abbreviation RDL) (not shown) is formed on the perforation silicon intermediary layer 3
Suddenly, so that the nude film 5 is electrically connected by the re-wiring layer and the perforation silicon intermediary layer 3.
As an example, the re-wiring layer is made as alternately following steps：Using chemical vapor deposition method or
Physical gas-phase deposition performs etching to form figure in forming dielectric layer on the perforation silicon intermediary layer 3 to the dielectric layer
The dielectric layer of shape；Using physical gas-phase deposition, chemical vapor deposition method, evaporation process, sputtering technology, electroplating technology
Or chemical plating process in patterned dielectric layer surface formed metal layer, and the metal layer is performed etching to be formed it is patterned
Metal wiring layer, the metal wiring layer is with passing through patterned dielectric layer, to be electrical connected with the perforation silicon intermediary layer 3.
The material of the dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, one kind in fluorine-containing glass
Or two or more combinations, the material of the metal wiring layer include one or both of copper, aluminium, nickel, gold, silver, titanium above group
Close.
Specifically, the re-wiring layer includes at least one layer of patterned dielectric layer and at least one layer of patterned metal
Wiring layer.That is, the re-wiring layer can include the multiple dielectric layers stacked gradually and multiple metal wiring layers,
According to line demand, by each dielectric layer is patterned or made through hole realize it is mutual between each layer metal wiring layer
Even, to realize the line demand of difference in functionality.
Specifically, the nude film 5 can be the nude film (Bumped Die) that front carries conductive bump 6, the nude film leads to
The conductive bump is crossed to be electrically connected with the re-wiring layer.
As an example, will be with convex block nude film (Bumped by engaging (bond-on-trace, abbreviation BOT) method on trace
Die) it is bonded on re-wiring layer.The material of the conductive bump can include but is not limited to copper (Cooper), nickel
(Nickel), Xi Yin (Tin-Silver).
In another embodiment, after re-wiring layer is formed on the perforation silicon intermediary layer 3, further include in described heavy
The step of projection cube structure being formed on new route layer, so that the nude film 5 passes through the projection cube structure and re-wiring layer electricity
Property connection.
As an example, the preparation method of the projection cube structure includes step：A) using galvanoplastic in the re-wiring layer
The metal line layer surface that top is exposed forms copper post；B) using galvanoplastic in the copper post surface formed metal barrier (
Metal barrier can not be made)；C) solder metal is formed in the metal barrier layer surface using galvanoplastic, and is returned using high temperature
Flow technique and form solder bump in the metal barrier layer surface.Further, the metal barrier includes nickel layer, the weldering
The material of material salient point includes one kind in lead, tin and silver or includes the alloy of any one above-mentioned solder metal.
In other embodiments, the projection cube structure can also only include solder bump, for example, the projection cube structure is tin
Ball, is directly made in the metal line layer surface exposed at the top of the re-wiring layer.
As shown in fig. 7, performing step S5, the nude film 5 and the perforation silicon intermediary are covered in being formed on the adhesion layer 2
The plastic packaging layer 7 of layer 3.
Specifically, the plastic packaging layer 7 is used to protect the nude film 5 and the perforation silicon intermediary layer 3 so that encapsulating structure is not
Easily split.As an example, the plastic packaging layer 7 selects one in thermosets, such as silica gel, epoxy resin, polyimides
The common capsulation materials such as kind.The method for forming the plastic packaging layer 7 may be selected from but be not limited to compression molding (compressive
Molding (paste printing), transfer molding (transfer molding), hydraulic seal shaping (liquid), are printed
Encapsulant molding), vacuum pressing-combining (vacuum lamination), spin coating (spin coating) the methods of in
Any one.
For example, transfer molding (transfer molding) is one of manufacturing process of plastics, it is by the gold after closure
Belonging to model heating, the method for being allowed to hardening shaping from tubule cast gate press-in molten resin is high compared with the forming accuracy of compression molding,
And the formed products of extremely complex shape can be generated.And loading resin progress once-through operation can be at the same time in the gold of connection at one
Belong in mould and obtain several formed products.This manufacturing process is mainly used for phenolic resin, urea resin, melamine, epoxy resin with gathering
The shaping of the thermosetting resins such as ester, so the also referred to as injection pressure shaping of thermosetting resin.
As shown in figure 8, perform step S6：The bearing substrate 1 and adhesion layer 2 are removed, obtains including in the perforation silicon
The three-dimensional chip module of interlayer 3, the nude film 5 and the plastic packaging layer 7.
Specifically, separate the adhesion layer 2 is selected from, but not limited to, chemical corruption with perforation silicon intermediary layer 3, the method for plastic packaging layer 7
In erosion, mechanical stripping, mechanical lapping, hot baking, ultraviolet light, laser ablation, chemically mechanical polishing and wet method stripping extremely
Few one kind.If for example, the adhesion layer 2 uses UV adhesive tapes, the UV adhesive tapes viscosity drop can be made using ultraviolet light first
It is low, the bearing substrate 1 and the adhesion layer 2 is departed from the perforation silicon intermediary layer 3 and plastic packaging by way of tearing off
Layer 7, relative to reduction process, such as grinds, for corrosion, this separation method is more simple, easily operated, can drop significantly
Low process costs.
As shown in figure 9, perform step S7：One package substrate 8 is provided, the three-dimensional chip module is had into the perforation silicon
The one side of intermediary layer 3 is installed on the package substrate 8.
Specifically, the package substrate 8 includes but not limited to pcb board, conductive interconnecting structure is provided with, the back side, which is equipped with, draws
Go out the soldered ball 9 of conductive interconnecting structure.
Specifically, after the three-dimensional chip module is installed on the package substrate 8, the three-dimensional chip module with
There is gap between the package substrate 8；In above-mentioned production method, the three-dimensional chip module is installed in the encapsulation base
After on plate 8, the step of protective layer 10 are formed in the gap (as shown in Figure 10) is further included.The protective layer 10 can use
Polymeric material, it surrounds the conductive salient point 303, on the one hand can increase the conductive salient point 303 and the package substrate 8 it
Between bond strength, prevent it from rocking or dropping, on the other hand it can be protected, prevent oxidation and steam etc. to conduction
The influence of salient point 303 and the package substrate of lower section 8.
So far, the making of three-dimensional chip encapsulating structure is completed.Production method described in the present embodiment is first in carrying base
TSI perforation silicon intermediary layers are adhered on plate, then nude film face down is installed on the perforation silicon intermediary layer, and in described viscous
The plastic packaging layer for covering the nude film and the perforation silicon intermediary layer is formed on attached layer, then removes the bearing substrate and adhesion
Layer, obtains the three-dimensional chip module for including the perforation silicon intermediary layer, the nude film and the plastic packaging layer, finally provides an encapsulation
Substrate, the one side that the three-dimensional chip module has the perforation silicon intermediary layer is installed on the package substrate.The making
Method process complexity is relatively low, advantageously reduces production cost and improves encapsulation yield.
In conclusion the three-dimensional chip encapsulating structure of the utility model includes package substrate and is electrically connected at the encapsulation
The three-dimensional chip module of surface, wherein, the three-dimensional chip module includes：Perforation silicon intermediary layer, the perforation silicon intermediary
Layer includes insulated substrate and multiple conductive columns for running through the insulated substrate up and down, and the conductive column and the package substrate are electrical
Connection；At least one nude film, the nude film face down are installed on the perforation silicon intermediary layer；Plastic packaging layer, covering are described naked
Piece and the perforation silicon intermediary layer.The encapsulating structure is using package substrate, perforation silicon intermediary layer, the encapsulation shape of die stack
Formula, and use plastic packaging layer realizes the protection of nude film, wherein, nude film can pass through conductive bump and rewiring with perforation silicon intermediary layer
Layer connection.The encapsulating structure has the advantages that simple in structure, higher I/O density, faster efficiency of transmission, and work in its manufacturing process
Skill complexity is relatively low, advantageously reduces production cost and improves encapsulation yield.So the utility model effectively overcomes existing skill
Various shortcoming in art and have high industrial utilization.
The above embodiments are only illustrative of the principle and efficacy of the utility model, new not for this practicality is limited
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
God and all equivalent modifications completed under technological thought or change, should be covered by the claim of the utility model.
Claims (10)
1. a kind of three-dimensional chip encapsulating structure, including package substrate and the three-dimensional chip that is electrically connected above the package substrate
Module, it is characterised in that the three-dimensional chip module includes：
Perforate silicon intermediary layer, including insulated substrate and it is multiple up and down run through the insulated substrate conductive column, the conductive column with
The package substrate is electrically connected；
At least one nude film, the nude film face down are installed on the perforation silicon intermediary layer；
Plastic packaging layer, covers the nude film and the perforation silicon intermediary layer.
2. three-dimensional chip encapsulating structure according to claim 1, it is characterised in that：The three-dimensional chip module and the envelope
There is gap between dress substrate, matcoveredn is formed in the gap.
3. three-dimensional chip encapsulating structure according to claim 1, it is characterised in that：The nude film and the perforation silicon intermediary
Formed with re-wiring layer between layer, so that the nude film is electrically connected by the re-wiring layer and the perforation silicon intermediary layer
Connect.
4. three-dimensional chip encapsulating structure according to claim 3, it is characterised in that：The re-wiring layer includes at least one
The dielectric layer of layer pattern and at least one layer of patterned metal wiring layer.
5. three-dimensional chip encapsulating structure according to claim 3, it is characterised in that：The front of the nude film carries conductive stud
Block, the nude film are electrically connected by the conductive bump and the re-wiring layer.
6. three-dimensional chip encapsulating structure according to claim 3, it is characterised in that：It is provided with the re-wiring layer convex
Block structure, so that the nude film is electrically connected by the projection cube structure and the re-wiring layer.
7. three-dimensional chip encapsulating structure according to claim 6, it is characterised in that：The projection cube structure include metal column and
The solder bump being connected to above the metal column.
8. three-dimensional chip encapsulating structure according to claim 6, it is characterised in that：It is convex that the projection cube structure only includes solder
Point.
9. three-dimensional chip encapsulating structure according to claim 1, it is characterised in that：The conductive column by conductive salient point with
The package substrate is electrically connected.
10. three-dimensional chip encapsulating structure according to claim 1, it is characterised in that：The package substrate back side is equipped with more
A soldered ball.
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| CN201721271536.2U CN207250493U (en) | 2017-09-29 | 2017-09-29 | A kind of three-dimensional chip encapsulating structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108598046A (en) * | 2018-04-19 | 2018-09-28 | 苏州通富超威半导体有限公司 | The encapsulating structure and its packaging method of chip |
| CN114762103A (en) * | 2019-12-16 | 2022-07-15 | 华为技术有限公司 | Chip stacking structure and manufacturing method thereof |
-
2017
- 2017-09-29 CN CN201721271536.2U patent/CN207250493U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108598046A (en) * | 2018-04-19 | 2018-09-28 | 苏州通富超威半导体有限公司 | The encapsulating structure and its packaging method of chip |
| CN114762103A (en) * | 2019-12-16 | 2022-07-15 | 华为技术有限公司 | Chip stacking structure and manufacturing method thereof |
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Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |