CN205069594U - Fan -out type packaging structure - Google Patents
Fan -out type packaging structure Download PDFInfo
- Publication number
- CN205069594U CN205069594U CN201520869747.0U CN201520869747U CN205069594U CN 205069594 U CN205069594 U CN 205069594U CN 201520869747 U CN201520869747 U CN 201520869747U CN 205069594 U CN205069594 U CN 205069594U
- Authority
- CN
- China
- Prior art keywords
- fan
- projection cube
- layer
- chip
- out package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The utility model provides a fan -out type packaging structure, include: subdividing cloth lead wire layer, the bonded in subdividing cloth lead wire layer upper surface and with at least one first chip that subdividing cloth lead wire layer electricity is connected, with subdividing cloth lead wire layer electricity connects and the top is higher than two at least first lug structures of first chip, cover first chip, and expose the plastic envelope layer of the upper end of first lug structure, and make in the second lug structure of subdividing cloth lead wire layer lower surface. In the carrier roller device, plastic envelope effect, its combination are not only played to the plastic envelope layer first lug structure can replace the TSV structure, realizes the stacked encapsulation, and for the TSV production process of complicacy, the preparation is changeed to this type of TSV structure, is favorable to the simplifying processing flow, reduce cost. Because first lug structure inlay in in the plastic envelope layer and on exposing for the stacked encapsulation realizes more easily.
Description
Technical field
The utility model belongs to field of semiconductor package, relates to a kind of fan-out package structure.
Background technology
Semi-conductor industry continues by lasting reduction minimum feature size the integration density improving various electronic component, and making can integrated more electronic component under given area.At present, state-of-the-art encapsulation solution comprises crystal wafer chip dimension encapsulation (Waferlevelchip-scalepackage), fan-out-type wafer-level packaging (Fan-outwaferlevelpackage) flip-chip (Flipchip) and stack type package (PackageonPackage, POP) etc.
Traditional fan-out-type wafer-level packaging (Fan-outwaferlevelpackaging, FOWLP) generally comprise following several step: first cut single microchip from wafer, and adopt standard to pick up the equipment of putting chip front side is pasted on the adhesive-layer of carrier down; Then form plastic packaging layer, chip is embedded in plastic packaging layer; After the solidification of plastic packaging layer, remove carrier and adhesive-layer, the trace layer technique that then distributes again and plant ball reflux technique, finally carry out cutting and testing.The trace layer that distributes again (RedistributionLayers, RDL) is the connection interface between flip-chip assembly chips and encapsulation.The trace layer that distributes again is an extra metal level, is made up of core metal top trace, for the I/O pad of nude film is outwards tied to other positions such as such as bump pad.Salient point is arranged with comb mesh pattern usually, and each salient point is cast with two pads (at top, in bottom), and they connect distribute trace layer and base plate for packaging respectively again.Traditional fan-out-type wafer-level packaging easily causes offseting between chip and RDL layer, causes yield lower.
Stack type package (PackageonPackage, PoP) the multiple chip of vertical stack in single package body can be made, the logic be longitudinally separated and storage ball grid array are combined, signal transmission is carried out by standard interface between stacked each packaging body, thus realize the multiplication of component density, make single package body realize more function, be widely used in the fields such as mobile phone, personal digital assistant (PDA), digital camera.
In Advanced Packaging, silicon through hole technology (Through-siliconvia, TSV) has significant impact, and it is the vertical electric connection technology penetrating substrate (particularly silicon chip).TSV almost can replace the place of the wire bonding (Wire-Bonding) in all encapsulation, improve the electric property of all kinds chip package, comprise raising integrated level, reduce chip size, particularly at system collection encapsulation (System-in-Packaging, SiP), among wafer level packaging (Wafer-LevelPackaging – WLP) and three-dimensional perpendicular stacked package (3DPackaging) these Advanced Packagings.The manufacture of TSV includes the manufacture of through hole, the deposition of insulating barrier, the filling of through hole and follow-up CMP (CMP) and the techniques such as (RDL) that connects up again.Traditional stack type package is relevant to TSV technique, needs the manufacturing process of series of complex, causes higher production cost and lower yield.
Therefore, how to provide a kind of fan-out package structure, to reduce production cost, improve yield, become the important technological problems that those skilled in the art are urgently to be resolved hurrily.
Utility model content
The shortcoming of prior art in view of the above, the purpose of this utility model is to provide a kind of fan-out package structure, the problem that packaging cost in prior art is higher for solving, yield is lower.
For achieving the above object and other relevant objects, the utility model also provides a kind of fan-out package structure, comprising:
Distribute trace layer again;
Distribute described in being bonded to trace layer upper surface at least one first chip be electrically connected with the described trace layer that distributes again again;
Be electrically connected with the described trace layer that distributes again and top higher than at least two the first projection cube structures of described first chip;
Cover described first chip, and expose the plastic packaging layer of the upper end of described first projection cube structure;
And the second projection cube structure of the trace layer lower surface that distributes again described in being made in.
Alternatively, described fan-out package structure also comprises at least one first packaging body being bonded to the upper end that described first projection cube structure exposes.
Alternatively, described fan-out package structure also comprises the second packaging body be connected with described second projection cube structure.
Alternatively, described second packaging body comprises pcb board.
Alternatively, the described trace layer that distributes again comprises dielectric layer and is formed at least one deck redistribution metal wire road in described dielectric layer.
Alternatively, described first chip surface is manufactured with the 3rd projection cube structure, and described first chip is electrically connected with the described trace layer that distributes again by described 3rd projection cube structure.
Alternatively, described first projection cube structure comprises metal column and is formed at the tinbase metal cap on described metal column top.
Alternatively, described metal column is Cu post or Ni post.
Alternatively, described first projection cube structure is metal soldered ball.
Alternatively, described second projection cube structure is metal soldered ball.
As mentioned above, fan-out package structure of the present utility model has following beneficial effect: in fan-out package structure of the present utility model, described plastic packaging layer not only plays the effect of the first chip described in plastic packaging, and it is in conjunction with described first projection cube structure, can TSV structure be substituted, realize stack type package.Relative to the TSV Making programme of complexity, the class TSV structure that the utility model is made up of plastic packaging layer and described first projection cube structure is more easily prepared, and is conducive to simplification of flowsheet, reduces costs.To be embedded in described plastic packaging layer due to described first projection cube structure and to expose upper end, stack type package is more easily realized.Described stack type package structure further by described second projection cube structure and pcb board or other packaging body bonding, can improve packaging efficiency.
Accompanying drawing explanation
Fig. 1 is shown as the schematic diagram of fan-out package structure of the present utility model.
Fig. 2 is shown as the schematic diagram that fan-out package structure of the present utility model comprises at least one the first packaging body being bonded to the upper end that described first projection cube structure exposes.
Fig. 3 is shown as the schematic diagram that fan-out package structure of the present utility model comprises the second packaging body be connected with described second projection cube structure.
Fig. 4 is shown as the process chart of the manufacture method of fan-out package structure of the present utility model.
The manufacture method that Fig. 5 is shown as fan-out package structure of the present utility model forms adhesive-layer schematic diagram at upper surface of base plate.
The manufacture method that Fig. 6 is shown as fan-out package structure of the present utility model forms the schematic diagram of the trace layer that distributes again at described adhesive-layer upper surface.
Fig. 7 is shown as the schematic diagram of manufacture method at described distribute again at least one first chip of trace layer upper surface bonding making at least two the first projection cube structures of fan-out package structure of the present utility model.
Fig. 8 is shown as the schematic diagram of manufacture method at the described trace layer upper surface formation plastic packaging layer that distributes again of fan-out package structure of the present utility model.
The structural representation of the die module that the manufacture method that Fig. 9 is shown as fan-out package structure of the present utility model uses.
The manufacture method that Figure 10 is shown as fan-out package structure of the present utility model sticks barrier film at the top briquetting lower surface of described die module, described substrate is positioned over briquetting surface, described bottom, and places the schematic diagram of capsulation material on the described trace layer surface that distributes again.
Described substrate is clamped by described top briquetting and described bottom briquetting by the manufacture method that Figure 11 is shown as fan-out package structure of the present utility model, described capsulation material is driven plain, and the upper end of described first projection cube structure embed the schematic diagram in described barrier film.
The manufacture method that Figure 12 is shown as fan-out package structure of the present utility model discharges described top briquetting and described bottom briquetting, and peels off the schematic diagram of described barrier film.
Figure 13 is shown as the complete structural representation obtained of manufacture method pressing mold of fan-out package structure of the present utility model.
The manufacture method that Figure 14 is shown as fan-out package structure of the present utility model removes the schematic diagram of described substrate and adhesive-layer.
Element numbers explanation
1 substrate
2 adhesive-layers
3 distribute trace layer again
31 dielectric layers
32 redistribution metal wire roads
4 first chips
41 the 3rd projection cube structures
5 first projection cube structures
51 metal columns
52 tinbase metal caps
6 plastic packaging layers
7 second projection cube structures
8 first packaging bodies
9 second packaging bodies
10 die module
Briquetting bottom 101
102 top briquettings
11 barrier films
12 capsulation materials
S1 ~ S5 step
Embodiment
Below by way of specific instantiation, execution mode of the present utility model is described, those skilled in the art the content disclosed by this specification can understand other advantages of the present utility model and effect easily.The utility model can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present utility model.
Refer to Fig. 1 to Figure 14.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present utility model in a schematic way, then only the assembly relevant with the utility model is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
Embodiment one
The utility model also provides a kind of fan-out package structure, as shown in Figure 1, is shown as the schematic diagram of this fan-out package structure, comprises:
Distribute trace layer 3 again;
Distribute described in being bonded to trace layer 3 upper surface at least one first chip 4 be electrically connected with the described trace layer 3 that distributes again again;
Be electrically connected with the described trace layer 3 that distributes again and top higher than at least two the first projection cube structures 5 of described first chip 4;
Cover described first chip 4, and expose the plastic packaging layer 6 of the upper end of described first projection cube structure 5;
And the second projection cube structure 7 of trace layer 3 lower surface that distributes again described in being made in.
Concrete, the described trace layer 3 that distributes again comprises dielectric layer 31 and is formed at least one deck redistribution metal wire road 32 in described dielectric layer 31.Exemplarily, the described trace layer 3 that distributes again comprises four floor redistribution metal wire roads 32, and wherein, the redistribution metal wire road 32 of top layer and bottom is exposed to upper surface and the lower surface of described dielectric layer 31 respectively.Be connected by some conductive poles between each floor redistribution metal wire road 32.
Described redistribution metal wire road 32 adopts conducting metal, includes but not limited to the good conductor of the electricity such as copper, aluminium, titanium.The material of described dielectric layer 31 includes but not limited to epoxy resin, silicon rubber, silicones, PI, PBO, BCB, also can adopt low-K dielectric, such as silica, phosphorosilicate glass, fluoride glass etc.
Concrete, described first chip 4 surface is manufactured with the 3rd projection cube structure 41, and described first chip 4 is electrically connected with the described trace layer 3 that distributes again by described 3rd projection cube structure 41.Herein, described electrical connection refers to that described 3rd projection cube structure 41 is connected with the described current-carrying part distributing trace layer 3 again, is namely connected with described redistribution metal wire road 32.Described 3rd projection cube structure 41 includes but not limited to copper, nickel or silver-colored gun-metal soldered ball.Described first chip 4 can comprise substrate or more circuit structure.When multiple first chip 4 of the described trace layer 3 upper surface bonding that distributes again, each first chip 4 can be identical type, also can be dissimilar.
Concrete, the top of described first projection cube structure 5 is higher than the top of described first chip 4.When the height of multiple first chip 4 is inconsistent, the top of described first projection 5 is higher than the top of all described first chips 4.
In the present embodiment, described first projection cube structure 5 comprises metal column 51 and is formed at the tinbase metal cap 52 on described metal column 51 top.Described metal column 51 includes but not limited to Cu post or Ni post.The material of described tinbase metal cap 52 includes but not limited to the conventional solder such as tin, silver-colored tin.
In another embodiment, described first projection cube structure 5 also can not comprise metal column, and is only metal welding ball (solderball).Be only the scheme of metal soldered ball relative to described first projection cube structure 5, described first projection cube structure 5 is more conducive to saving package area in conjunction with the scheme of tinbase metal cap for metal column.
Concrete, described plastic packaging layer 6 adopts thermosets, includes but not limited to one or more in the materials such as polymeric material, resin-based materials, polyimides (PI), epoxy resin.The upper end level of described first projection cube structure 5 that described plastic packaging layer 6 exposes can adjust as required.
Fan-out package structure of the present utility model not only has stack type package ability, also has various packaging body binding ability.As shown in Figure 2, be shown as described fan-out package structure and also comprise at least one first packaging body 8 being bonded to the upper end that described first projection cube structure 5 exposes.Wherein, multiple first packaging body can be identical type, also can be dissimilar, thus meet various application demand.
In addition, as shown in Figure 3, described fan-out package structure also can comprise the second packaging body 9 be connected with described second projection cube structure 7 further.Described second packaging body 9 can be pcb board (flexible circuit board) or other packaging body.
In fan-out package structure of the present utility model, described plastic packaging layer 6 not only plays the effect of the first chip 4 described in plastic packaging, and it, in conjunction with described first projection cube structure 5, can substitute TSV structure, realize stack type package.Relative to the TSV Making programme of complexity, the class TSV structure that the utility model is made up of plastic packaging layer 6 and described first projection cube structure 5 is more easily prepared, and is conducive to simplification of flowsheet, reduces costs.To be embedded in described plastic packaging layer 6 due to described first projection cube structure 5 and to expose upper end, stack type package is more easily realized.Described stack type package structure further by described second projection cube structure 7 and pcb board or other packaging body bonding, can improve packaging efficiency.
Embodiment two
A kind of manufacture method of fan-out package structure of the present utility model is as follows, refers to Fig. 4, is shown as the process chart of the method, comprises the following steps:
S1 a: substrate is provided, surface forms adhesive-layer on the substrate;
S2: form the trace layer that distributes again at described adhesive-layer upper surface;
S3: also make at least two the first projection cube structures at described at least one first chip of trace layer upper surface bonding that distributes again; Described first chip and described first projection cube structure are all electrically connected with the described trace layer that distributes again, and the top of described first projection cube structure is higher than the top of described first chip;
S4: form plastic packaging layer at the described trace layer upper surface that distributes again, described plastic packaging layer covers described first chip, and exposes the upper end of described first projection cube structure;
S5: remove described substrate and adhesive-layer, makes the second projection cube structure at the described trace layer lower surface that distributes again.
First refer to Fig. 5, perform step S1: provide a substrate 1, form adhesive-layer 2 at described substrate 1 upper surface.
Described substrate 1 can provide structure or the matrix of rigidity, at least one in its material selectable from glass, metal, semiconductor (such as Si), polymer or pottery for follow-up making adhesive-layer 2, again distribute trace layer 3, plastic packaging layer 6 etc.Exemplarily, glass selected by described substrate 1.Described substrate 1 can be wafer shape, square (such as 500*500mm) or other any required form.
Described adhesive-layer 2 in subsequent technique as the separating layer distributed again between trace layer 3 and substrate 1, it preferably selects the jointing material with smooth finish surface to make, it must have certain adhesion with the trace layer 3 that distributes again, the situations such as mobile can not be produced in subsequent technique with the trace layer 3 that distributes again described in ensureing, in addition, itself and described substrate 1 also have stronger adhesion, and in general, the adhesion of itself and described substrate 1 needs to be greater than the adhesion with the described trace layer 3 that distributes again.Exemplarily, the material of described adhesive-layer 2 adhesive glue etc. that is selected from the sticking adhesive tape of two-sided equal tool or made by spin coating proceeding.Described adhesive tape preferably adopts UV adhesive tape, and it is easy to be torn off after UV illumination is penetrated.In other embodiments, described adhesive-layer 2 physical vaporous deposition or chemical vapour deposition technique also can be selected to refer to other materials layer, as epoxy resin (Epoxy), silicon rubber (siliconerubber), polyimides (PI), polybenzoxazoles (PBO), benzocyclobutene (BCB) etc.Described in later separation during substrate 1, the method such as wet etching, cmp can be adopted to remove described adhesive-layer 2.
Then refer to Fig. 6, perform step S2: form at described adhesive-layer 2 upper surface the trace layer 3 that distributes again.
Concrete, the described trace layer 3 that distributes again comprises dielectric layer 31 and is formed at least one deck redistribution metal wire road 32 in described dielectric layer 31.Exemplarily, as described in Figure 6, the described trace layer 3 that distributes again comprises four floor redistribution metal wire roads 32, and wherein, the redistribution metal wire road 32 of top layer and bottom is exposed to upper surface and the lower surface of described dielectric layer 31 respectively.Be connected by some conductive poles between each floor redistribution metal wire road 32.
Exemplarily, the described trace layer 3 that distributes again is comprised to the situation on multilayer redistribution metal wire road 32, the mode alternately forming dielectric layer and redistribution metal wire road can be adopted to obtain.Described redistribution metal wire road 32 can select at least one method in physical vaporous deposition (PVD), chemical vapour deposition technique (CVD), sputtering method, plating and chemical plating to be formed.Described dielectric layer 31 can select at least one method in spin coating, physical vapour deposition (PVD) and chemical vapour deposition (CVD) to be formed.
Described redistribution metal wire road 32 adopts conducting metal, includes but not limited to the good conductor of the electricity such as copper, aluminium, titanium.The material of described dielectric layer 31 includes but not limited to epoxy resin, silicon rubber, silicones, PI, PBO, BCB, also can adopt low-K dielectric, such as silica, phosphorosilicate glass, fluoride glass etc.
Then refer to Fig. 7, perform step S3: also make at least two the first projection cube structures 5 at described at least one first chip 4 of trace layer 3 upper surface bonding that distributes again; Described first chip 4 is all electrically connected with the described trace layer 3 that distributes again with described first projection cube structure 5, and the top of described first projection cube structure 5 is higher than the top of described first chip 4.
Concrete, distribute described in being bonded to by described first chip 4 by key mark method (bond-on-trace) trace layer 3 upper surface again.Exemplarily, described first chip 4 surface is manufactured with the 3rd projection cube structure 41, and described first chip 4 is electrically connected with the described trace layer 3 that distributes again by described 3rd projection cube structure 41.Described 3rd projection cube structure 41 includes but not limited to copper, nickel or silver-colored gun-metal soldered ball.
Described first chip 4 can comprise substrate or more circuit structure.When multiple first chip 4 of the described trace layer 3 upper surface bonding that distributes again, each first chip 4 can be identical type, also can be dissimilar.
First the manufacture method of the fan-out package structure of the present embodiment makes the trace layer that distributes again on carrier, and then chip is connected with the trace layer that distributes again, to avoid in traditional plastic packaging process because of the problem that the contraction in capsulation material heat curing process makes chip occur to offset with the trace layer that to distribute again, significantly improve yield.
Concrete, the top of described first projection cube structure 5 is higher than the top of described first chip 4.When the height of multiple first chip 4 is inconsistent, the top of described first projection 5 is higher than the top of all described first chips 4.
In the present embodiment, described first projection cube structure 5 comprises metal column 51 and is formed at the tinbase metal cap 52 on described metal column 51 top.Described metal column 51 includes but not limited to Cu post or Ni post.The technique such as thick photoresistance photoetching, development, metal deposition by routine forms described metal column 51, also forms described metal column 51 by techniques such as micro-embossing, metal depositions.
In another embodiment, described first projection cube structure 5 also can not comprise metal column, and is only metal welding ball (solderball).Be only the scheme of metal soldered ball relative to described first projection cube structure 5, described first projection cube structure 5 is more conducive to saving package area in conjunction with the scheme of tinbase metal cap for metal column.
Refer to Fig. 8 again, perform step S4: form plastic packaging layer 6 at described trace layer 3 upper surface that distributes again, described plastic packaging layer 6 covers described first chip 4, and exposes the upper end of described first projection cube structure 5.
Concrete, described plastic packaging layer 6 adopts thermosets, includes but not limited to one or more in the materials such as polymeric material, resin-based materials, polyimides (PI), epoxy resin.
Concrete, the upper end level of described first projection cube structure 5 exposed can adjust as required.In the present embodiment, adopt compression moulding to form described plastic packaging layer 6, comprise the steps:
As shown in Figure 9, perform step S4-1: provide a die module 10, described die module 10 comprises bottom briquetting 101 and top briquetting 102.
As shown in Figure 10, perform step S4-2: briquetting 102 lower surface sticks barrier film 11 at described top, described substrate 1 is positioned over briquetting 101 surface, described bottom, and place capsulation material 12 on described trace layer 3 surface that distributes again.Described capsulation material 12 can be liquid, and can be also solid granulates, wherein solid granulates can change liquid state under follow-up HTHP.
As shown in figure 11, step S4-3 is performed: clamped by described substrate 1 by described top briquetting 102 and described bottom briquetting 101, described capsulation material is driven plain, and the upper end of described first projection cube structure 5 embeds in described barrier film 11.
As shown in figure 12, step S4-4 is performed: discharge described top briquetting 102 and described bottom briquetting 101, and peel off described barrier film 11.
Concrete, described barrier film 11 is flexible polymeric materials, includes but not limited to polyimides, epoxy resin, polyester (PET) etc.By described barrier film 11, in pressing mold process, because the upper end of described first projection cube structure 5 embeds in described barrier film 11, the upper end of described first projection cube structure 5 is made to protrude from capsulation material surface.
As shown in figure 13, be shown as the complete structural representation obtained of pressing mold, namely as described plastic packaging layer 6 after the capsulation material be wherein driven plain solidification, described plastic packaging layer 6 and expose the upper end of described first projection cube structure 5.It is pointed out that in order to illustrated convenience, the adhesive-layer 2 on described substrate 1, distribute the non-detailed icon of trace layer 3, first chip 4 in Figure 10,11,12 and 13 again.
The present embodiment obtains described plastic packaging layer by die pressing in conjunction with separation membrane, make plastic packaging layer upper surface lower than described first projection cube structure top, avoid the thinning of plastic packaging layer and laser beam drilling process, not only save material, reduce pollution, it also avoid the damage that thinning process causes circuit structure.
Finally refer to Figure 14 and Fig. 1, perform step S5: remove described substrate 1 and adhesive-layer 2, make the second projection cube structure 7 at described trace layer 3 lower surface that distributes again.
Concrete, described second projection cube structure 7 is metal soldered ball.
So far, making obtains fan-out package structure of the present utility model.Wherein, described first projection cube structure 5 is embedded in described plastic packaging layer 6, and exposes upper end.Described plastic packaging layer 6 not only plays the effect of the first chip 4 described in plastic packaging, and it, in conjunction with described first projection cube structure, can substitute TSV structure, realize stack type package.
As shown in Figure 2, the schematic diagram of at least one the first packaging body 8 of upper end bonding exposed at described first projection cube structure 5 is shown as.Wherein, multiple first packaging body can be identical type, also can be dissimilar, to meet different application demands.
Relative to the TSV Making programme of complexity, first the method for the present embodiment makes described first projection cube structure, then carry out mold pressing and form described plastic packaging layer, technological process is more simple, and upper strata packaging body can be bonded directly to the upper end that described first projection cube structure exposes, encapsulation process is also simpler, thus reduces costs.
In addition, as shown in Figure 3, further structure as shown in Figure 2 can be connected to the second packaging body 9 by described second projection cube structure 7.Exemplarily, described second packaging body 9 is pcb board.In other embodiments, described second packaging body 9 also can be other packaging body, should too not limit protection range of the present utility model herein.
In sum, in fan-out package structure of the present utility model, described plastic packaging layer not only plays the effect of the first chip described in plastic packaging, and it, in conjunction with described first projection cube structure, can substitute TSV structure, realize stack type package.Relative to the TSV Making programme of complexity, the class TSV structure that the utility model is made up of plastic packaging layer and described first projection cube structure is more easily prepared, and is conducive to simplification of flowsheet, reduces costs.To be embedded in described plastic packaging layer due to described first projection cube structure and to expose upper end, stack type package is more easily realized.Described stack type package structure further by described second projection cube structure and pcb board or other packaging body bonding, can improve packaging efficiency.So the utility model effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present utility model and effect thereof only, but not for limiting the utility model.Any person skilled in the art scholar all without prejudice under spirit of the present utility model and category, can modify above-described embodiment or changes.Therefore, such as have in art and usually know that the knowledgeable modifies or changes not departing from all equivalences completed under the spirit and technological thought that the utility model discloses, must be contained by claim of the present utility model.
Claims (10)
1. a fan-out package structure, is characterized in that, comprising:
Distribute trace layer again;
Distribute described in being bonded to trace layer upper surface at least one first chip be electrically connected with the described trace layer that distributes again again;
Be electrically connected with the described trace layer that distributes again and top higher than at least two the first projection cube structures of described first chip;
Cover described first chip, and expose the plastic packaging layer of the upper end of described first projection cube structure;
And the second projection cube structure of the trace layer lower surface that distributes again described in being made in.
2. fan-out package structure according to claim 1, is characterized in that: described fan-out package structure also comprises at least one first packaging body being bonded to the upper end that described first projection cube structure exposes.
3. fan-out package structure according to claim 1 and 2, is characterized in that: described fan-out package structure also comprises the second packaging body be connected with described second projection cube structure.
4. fan-out package structure according to claim 3, is characterized in that: described second packaging body comprises pcb board.
5. fan-out package structure according to claim 1, is characterized in that: the described trace layer that distributes again comprises dielectric layer and is formed at least one deck redistribution metal wire road in described dielectric layer.
6. fan-out package structure according to claim 1, is characterized in that: described first chip surface is manufactured with the 3rd projection cube structure, and described first chip is electrically connected with the described trace layer that distributes again by described 3rd projection cube structure.
7. fan-out package structure according to claim 1, is characterized in that: described first projection cube structure comprises metal column and is formed at the tinbase metal cap on described metal column top.
8. fan-out package structure according to claim 7, is characterized in that: described metal column is Cu post or Ni post.
9. fan-out package structure according to claim 1, is characterized in that: described first projection cube structure is metal soldered ball.
10. fan-out package structure according to claim 1, is characterized in that: described second projection cube structure is metal soldered ball.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520869747.0U CN205069594U (en) | 2015-11-03 | 2015-11-03 | Fan -out type packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520869747.0U CN205069594U (en) | 2015-11-03 | 2015-11-03 | Fan -out type packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205069594U true CN205069594U (en) | 2016-03-02 |
Family
ID=55396113
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520869747.0U Active CN205069594U (en) | 2015-11-03 | 2015-11-03 | Fan -out type packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205069594U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105225965A (en) * | 2015-11-03 | 2016-01-06 | 中芯长电半导体（江阴）有限公司 | A kind of fan-out package structure and preparation method thereof |
| CN107799479A (en) * | 2016-09-02 | 2018-03-13 | 矽品精密工业股份有限公司 | Electronic package and manufacturing method thereof |
| CN108346586A (en) * | 2017-01-22 | 2018-07-31 | 欣兴电子股份有限公司 | Encapsulate body device and its manufacturing method |
-
2015
- 2015-11-03 CN CN201520869747.0U patent/CN205069594U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105225965A (en) * | 2015-11-03 | 2016-01-06 | 中芯长电半导体（江阴）有限公司 | A kind of fan-out package structure and preparation method thereof |
| CN107799479A (en) * | 2016-09-02 | 2018-03-13 | 矽品精密工业股份有限公司 | Electronic package and manufacturing method thereof |
| CN108346586A (en) * | 2017-01-22 | 2018-07-31 | 欣兴电子股份有限公司 | Encapsulate body device and its manufacturing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105225965A (en) | A kind of fan-out package structure and preparation method thereof | |
| CN206992089U (en) | Semiconductor device | |
| CN105374693B (en) | Semiconductor package part and forming method thereof | |
| CN105118823A (en) | Stacked type chip packaging structure and packaging method | |
| CN107533985A (en) | Vertical stacking system in package and its manufacture method including first order nude film, the second level nude film of back-to-back stacking and third level nude film and corresponding first redistribution layer, the second redistribution layer and the 3rd redistribution layer | |
| CN105070671A (en) | Chip encapsulation method | |
| WO2017049928A1 (en) | Chip packaging structure and packaging method therefor | |
| CN205039151U (en) | Stacked chip package structure | |
| CN108666214A (en) | Semiconductor devices and the method for being used to form the low embedded wafer scale ball grid array molding laser package of profile | |
| TW201104797A (en) | Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP | |
| CN107706520A (en) | Fan-out-type antenna packages structure and preparation method thereof | |
| CN205069594U (en) | Fan -out type packaging structure | |
| CN110085575A (en) | Semiconductor package and preparation method thereof | |
| CN107195625A (en) | Two-sided system-level laminated packaging structure of plastic packaging fan-out-type and preparation method thereof | |
| CN112713097A (en) | Antenna packaging structure and packaging method | |
| CN112713098A (en) | Antenna packaging structure and packaging method | |
| CN206931602U (en) | The two-sided system-level laminated packaging structure of plastic packaging fan-out-type | |
| CN207852897U (en) | Fan-out-type antenna packages structure | |
| CN107611045A (en) | A kind of three-dimensional chip encapsulating structure and its method for packing | |
| CN205039150U (en) | Chip packaging structure | |
| CN212303700U (en) | System-in-package structure of LED chip | |
| CN210692485U (en) | Antenna packaging structure | |
| CN207250493U (en) | A kind of three-dimensional chip encapsulating structure | |
| CN213366617U (en) | Fan-out type LED packaging structure | |
| CN209929301U (en) | Semiconductor packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |