WO2017049928A1

WO2017049928A1 - Chip packaging structure and packaging method therefor

Info

Publication number: WO2017049928A1
Application number: PCT/CN2016/082782
Authority: WO
Inventors: 仇月东; 林正忠
Original assignee: 中芯长电半导体（江阴）有限公司
Priority date: 2015-09-24
Filing date: 2016-05-20
Publication date: 2017-03-30
Also published as: CN105140213B; CN105140213A

Abstract

A chip packaging method, comprising the following steps: S1: providing a carrier (1), forming an adhesive layer (2) on a surface of the carrier (1); S2: adhering at least two semiconductor chips (3) and at least one interconnection structure (4) on a surface of the adhesive layer (2); the interconnection structure (4) comprising a supporting body (5) and a plurality of conductive columns (6) vertically passing through the supporting body (5); S3: forming a plastic sealing layer (10) on the surface of the adhesive layer (2); S4: removing the carrier (1) and the adhesive layer (2); S5: forming a first dielectric layer (11) on the upper surface of the plastic sealing layer (10), and forming a second dielectric layer (12) on the lower surface of the plastic sealing layer (10); S6: forming redistribution lead layers (14) for the semiconductor chips (3) and the interconnection structure (4) on the basis of the first dielectric layer (11) and the second dielectric layer (12), so as to provide interconnection between the chips. By adding the interconnection structure (4) to the packaging process, the redistribution lead layers (14) are formed on both the front side and the rear side of the chips (3), which can maximize the redistribution area, provide interconnection between the chips (3), and effectively save on production costs.

Description

Chip package structure and packaging method

Technical field

The invention belongs to the field of semiconductor manufacturing, and relates to a chip package structure and a packaging method.

Background technique

The semiconductor industry has experienced rapid growth. Due to the improved integration density of electronic components, people tend to pursue smaller and more innovative semiconductor chip packaging technologies. In the fan-out type structure, the input and output pads of the chip are distributed outside the area where the chip is located, and therefore, the number of input and output pads of the semiconductor device can be increased.

The traditional fan-out wafer level packaging (FOWLP) generally includes the following steps: first, a single microchip is cut from the wafer, and the chip is attached face down to the carrier using a standard pick and place device. The adhesive layer is formed; then the plastic sealing layer is formed, the chip is embedded in the plastic sealing layer; after the plastic sealing layer is cured, the carrier and the adhesive layer are removed, and then the redistribution wiring layer process and the ball reflow process are performed, and finally the cutting and testing are performed.

Redistribution Layers (RDL) are interface interfaces between the chip and the package in a flip chip assembly. The redistribution lead layer is an additional metal layer consisting of core metal top traces that are used to bond the die I/O pads outward to other locations such as bump pads. The bumps are typically arranged in a grid pattern, each bump being cast with two pads (one at the top and one at the bottom) that connect the redistribution layer and the package substrate, respectively.

As the number of input and output pads of a semiconductor chip increases, a larger distribution area is required in order to complete the interconnection between the chip and the chip. More importantly, more than one redistribution layer (RDL) is usually required in the latest devices, which means more distribution area is necessary, which brings a lot of traditional two-dimensional fan-out packaging process. The challenge.

Advanced packaging technologies such as 3D TSV (Through Silicon Via), POP (Package on Package), 3D SiP (System in Package) can reduce package size and achieve between individual package units The interconnection, however, its unit redistribution area still needs to be improved.

Therefore, how to provide a chip package structure and a packaging method to maximize the redistribution area, improve the packaging efficiency, and reduce the production cost has become an important technical problem to be solved by those skilled in the art.

Summary of the invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a chip package structure and a package method for solving the problem that the redistribution area needs to be further improved when the chip package is performed in the prior art.

To achieve the above and other related objects, the present invention provides a chip packaging method including the following steps:

S1: providing a carrier, forming an adhesive layer on the surface of the carrier;

S2: adhering at least two semiconductor chips and at least one interconnect structure on a surface of the adhesive layer; the interconnect structure comprises a support body and a plurality of conductive pillars penetrating the support body up and down;

S3: forming a plastic seal layer on the surface of the adhesive layer, wherein the semiconductor chip and the interconnect structure are embedded in the plastic seal layer and expose the upper surface;

S4: separating the adhesive layer and the plastic sealing layer to remove the carrier and the adhesive layer;

S5: forming a first dielectric layer on the upper surface of the plastic sealing layer, forming a second dielectric layer on the lower surface, and forming a plurality of electrical leads and the conductive pillars in the first dielectric layer and the second dielectric layer Corresponding first through hole;

S6: forming a redistribution wiring layer on the semiconductor chip and the interconnect structure based on the first dielectric layer and the second dielectric layer to implement inter-chip interconnection.

Optionally, in the step S2, at least one semiconductor chip is adhered face down on the surface of the adhesive layer, and at least one semiconductor chip is adhered face up on the surface of the adhesive layer.

Optionally, the cross section of the conductive pillar includes at least one of a polygon, a circle, and an ellipse; the cross section of the support body includes at least one of a polygon, a circle, and an ellipse.

Optionally, in the interconnect structure, each of the conductive pillars is arranged in a lattice.

Optionally, the method for forming the interconnect structure includes the following steps:

(1) forming the support structure;

(2) forming a plurality of second through holes in the support structure;

(3) filling the second via hole with a metal to obtain the conductive pillar.

(1) providing a substrate, forming a plurality of vertically disposed conductive pillars on the surface of the substrate;

(2) forming a molding material covering the conductive pillar;

(3) removing excess molding material on the upper surface of the conductive post and removing the substrate to expose the lower surface of the conductive post, and the remaining molding material constitutes the support.

Optionally, in the step (1), the conductive pillar is formed on the surface of the substrate by an electroplating method or a wire drawing method.

Optionally, the chip packaging method of the present invention further includes a step S7: forming an under bump metal layer on the surface of the redistribution wiring layer, and forming a solder ball bump on the surface of the under bump metal layer.

The invention also provides a chip package structure, comprising:

Plastic seal layer

At least two semiconductor chips embedded in the plastic sealing layer and at least one interconnect structure; the interconnect structure includes a support body and a plurality of conductive pillars penetrating the support body up and down;

a first dielectric layer formed on an upper surface of the plastic seal layer and a second dielectric layer on a lower surface; the first dielectric layer and the second dielectric layer Forming a plurality of first via holes corresponding to the semiconductor chip electrically and the conductive pillars in the dielectric layer;

And a redistribution wiring layer composed of a conductive metal filled in the first via hole and a metal line distributed on the surfaces of the first dielectric layer and the second dielectric layer.

Optionally, in the chip package structure, at least one of the chips is disposed face up, and at least one of the semiconductor chips is disposed face down.

As described above, the chip package structure and the packaging method of the present invention have the following advantageous effects: the present invention can effectively increase the redistribution area by adding an interconnect structure during the packaging process. With the aid of the interconnect structure, the redistribution area is not limited to the front side of the semiconductor chip (the exposed side of the pad), but can also be extended to the back side of the semiconductor chip. More importantly, in the packaging process, not all of the semiconductor chips need to be face up or face down, that is, part of the semiconductor chip faces up and part of the semiconductor chip faces down. Through the chip packaging method of the invention, the redistribution area can be maximized, the interconnection between the chip and the chip can be realized, and the production cost can be effectively saved.

DRAWINGS

FIG. 1 shows a process flow diagram of a chip packaging method of the present invention.

2 is a schematic view showing the formation of an adhesive layer on the surface of a carrier by the chip packaging method of the present invention.

3 is a schematic view showing the method of the present invention for attaching at least two semiconductor chips and at least one interconnect structure to the surface of the adhesive layer.

4 through 7 show several cross-sectional schematic views of the interconnect structure.

8 to 10 are schematic views showing a method of forming the interconnect structure.

11 to 12 are schematic views showing a method of forming the interconnect structure.

Figure 13 is a schematic view showing the formation of a plastic sealing layer on the surface of the adhesive layer by the chip packaging method of the present invention.

FIG. 14 is a schematic view showing the removal of the carrier and the adhesive layer by the chip packaging method of the present invention.

15 shows a chip encapsulation method of the present invention, a first dielectric layer is formed on the upper surface of the plastic encapsulation layer, a second dielectric layer is formed on the lower surface, and a plurality of semiconductor chips are formed in the first dielectric layer and the second dielectric layer. A schematic diagram of electrical extraction and a first via corresponding to the conductive post.

16 shows a schematic diagram of a chip packaging method according to the present invention for forming a redistribution wiring layer on the semiconductor chip and the interconnect structure based on the first dielectric layer and the second dielectric layer to realize inter-chip interconnection.

17 to FIG. 18 are schematic diagrams showing the formation of a bump underlying metal layer on the surface of the redistribution lead layer according to the chip packaging method of the present invention, and forming solder bumps on the surface of the bump under the metal layer.

FIG. 19 is a schematic view showing the chip package method of the present invention cutting out a separate chip package structure.

Component label description

S1~S6 steps

1 carrier

2 adhesive layer

3 semiconductor chip

4 interconnection structure

5 support

6 conductive column

7 second through hole

8 substrate

9 molding materials

10 plastic seal

11 first dielectric layer

12 second dielectric layer

13 first through hole

14 redistributing the lead layer

15 third dielectric layer

16 third through hole

17 under bump metal layer

18 solder bumps

detailed description

The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention.

Please refer to Figure 1 to Figure 19. It should be noted that the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention in a schematic manner, and only the components related to the present invention are shown in the drawings, instead of the number and shape of components in actual implementation. Dimensional drawing, the actual type of implementation of each component's type, number and proportion can be a random change, and its component layout can be more complicated.

Embodiment 1

The present invention provides a chip packaging method. Referring to FIG. 1, a process flow diagram of the method is shown, including the following steps:

Referring first to FIG. 2, step S1 is performed: a carrier 1 is provided, and an adhesive layer 2 is formed on the surface of the carrier 1.

Specifically, the carrier 1 may be a structure or a substrate for providing a bonding layer 2 and a bonding semiconductor chip 3 and an interconnection structure 4, and the material thereof may be selected from a metal, a semiconductor (for example, Si), a polymer or a glass. At least one of them. As an example, the carrier 1 is made of glass.

The adhesive layer 2 serves as a separation layer between the semiconductor chip 3, the interconnect structure 4 and the carrier 1 in a subsequent process, which is preferably made of a bonding material having a smooth surface, which must be combined with the semiconductor chip 3 and The connecting structure 4 has a certain bonding force to ensure that the semiconductor chip 3 and the interconnect structure 4 do not move in a subsequent process, and in addition, it has a strong bonding force with the carrier 1, and generally, The bonding force of the carrier 1 needs to be greater than the bonding force with the semiconductor chip 3 and the interconnection structure 4. As an example, the material of the adhesive layer 2 is selected from a tape which is adhesive on both sides or an adhesive which is produced by a spin coating process or the like. The tape is preferably a UV tape which is easily peeled off after UV light irradiation.

Referring to FIG. 3, step S2 is performed to adhere at least two semiconductor chips 3 and at least one interconnect structure 4 on the surface of the adhesive layer 2; the interconnect structure 4 includes a support body and vertically penetrates the support body Several conductive columns.

Specifically, the semiconductor chip 3 includes, but is not limited to, a memory device, a display device, an input component, a discrete component, a power supply, a voltage regulator, and the like. The number of the semiconductor chips 3 may be two or more up to the number of semiconductor chips 3 that one wafer can carry.

Specifically, all of the semiconductor chips 3 may be adhered face-up to the surface of the adhesive layer 2, or all of the semiconductor chips 3 may be adhered face down on the surface of the adhesive layer 2. Here, the front surface of the semiconductor chip 3 refers to the side on which the semiconductor chip 3 is formed with the device and the electrode is taken out.

In particular, in the present invention, not all of the semiconductor chips need to be face up or face down, that is, at least one semiconductor chip may be adhered face down on the surface of the adhesive layer, and at least one semiconductor chip front side Adhered upward to the surface of the adhesive layer.

As an example, FIG. 3 shows a case where the surface of the adhesive layer 2 is adhered with four semiconductor chips 3, which are divided into two groups, each of which has one semiconductor chip facing up and the other semiconductor chip facing down. Two chips in each group need to be interconnected in the subsequent packaging process. It should be noted that, here is only an example, in the actual packaging process, the number and arrangement of chips in each group of package structures may be more complicated, and the scope of protection of the present invention should not be unduly limited herein.

Specifically, the height of the interconnect structure 4 is preferably the same as or substantially the same as the semiconductor chip. The cross section of the conductive pillar includes at least one of a polygon, a circle, and an ellipse; the cross section of the support includes at least one of a polygon, a circle, and an ellipse.

As an example, FIGS. 4-7 show several cross-sectional schematic views of the interconnect structure, wherein FIG. 4 shows a schematic view of the support body 5 and the conductive post 6 having a square cross section. 5 is a schematic view showing that the cross section of the support body 5 is square, the cross section of the conductive pillar 6 is circular, and FIG. 6 shows that the cross section of the support body 5 is circular, and the conductive pillar 6 The cross section of the cross section is a square diagram, and FIG. 7 shows a schematic view in which the cross section of the support body 5 and the conductive post 6 are both circular.

As an example, in the interconnect structure, each of the conductive pillars 6 is arranged in a lattice. It should be noted that the lattice arrangement described herein means that the arrangement of the conductive pillars has a periodicity in the cross section of the interconnect structure. 4 to 7 are only examples. In other embodiments, the support body 5 and the conductive pillars 6 may have other shapes and arrangements, as long as the conductive pillars 6 are vertically penetrated through the support body 5 Yes, the scope of protection of the present invention should not be unduly limited herein.

As an example, the method of forming the interconnect structure includes the following steps:

As shown in FIG. 8, step (1) is performed: the support structure 5 is formed.

The material of the support structure 5 includes, but is not limited to, glass, polymer, silicon oxide, silicon nitride, etc., preferably using low K (dielectric constant K ≤ 3.9) or ultra low K (dielectric constant K < 3 or K < 2.5) Dielectric material. The support structure may be formed by an injection molding process, spin coating, chemical vapor deposition, plasma vapor deposition or the like depending on the material.

The support structure 5 can also adopt photosensitive materials such as photosensitive polyimide, photosensitive benzocyclobutene, photosensitive polybenzoxazole, etc., which also have the characteristics of low K, and can be used as a dielectric material at the same time The photoresist layer can be directly obtained through the steps of exposure, development, and the like.

As shown in FIG. 9, step (2) is performed to form a plurality of second through holes 7 in the support structure 5. Methods of forming the second through holes 7 include, but are not limited to, laser drilling, mechanical drilling, deep reactive ion etching, exposure development, and the like.

As shown in FIG. 10, the second via hole 7 is filled with metal to obtain the conductive pillar 6. The material of the conductive pillar 6 is selected from at least one of Al, Cu, Sn, Ni, Au, and Ag. A method of filling metal in the second through hole 7 includes However, it is not limited to electroplating, electroless plating, physical vapor deposition, chemical vapor deposition, and the like.

In another embodiment, the interconnect structure can also be formed by the following steps:

As shown in FIG. 11, step (1) is performed: a substrate 8 is provided, and a plurality of vertically disposed conductive pillars 6 are formed on the surface of the substrate 8.

Specifically, the conductive pillars 6 may be formed on the surface of the substrate by an electroplating method or a wire drawing method.

As shown in FIG. 12, step (2) is performed: forming a molding material 9 covering the conductive pillars 6. The molding material employs a thermosetting material including, but not limited to, an epoxy resin, a polyimide, a silica gel, or the like. This process can be carried out by compression molding or injection molding.

Then performing step (3), removing excess molding material on the upper surface of the conductive pillar 6 and removing the substrate 8 to expose the lower surface of the conductive pillar 6, and the remaining molding material constitutes the support member 5, Thereby an interconnection structure as shown in FIG. 10 is obtained.

It should be noted that the above two methods can simultaneously form a plurality of the interconnect structures, and finally obtain a single of the interconnect structures by cutting.

Referring to FIG. 13, step S3 is performed to form a molding layer 10 on the surface of the adhesive layer 2, wherein the semiconductor chip 3 and the interconnect structure 4 are embedded in the molding layer 10 and expose the upper surface. .

It should be noted that the heights of the plurality of semiconductor chips 3 adhered to the surface of the adhesive layer 2 and the interconnect structure 4 may be inconsistent, in order to expose all of the semiconductor chips 3 and the For the upper surface of the interconnect structure 4, a process such as grinding, partial laser opening, or the like may be applied to the plastic sealing layer. The height of each of the semiconductor chips 3 and the interconnect structure 4 can be reasonably adjusted according to actual needs.

Specifically, the plastic sealing layer 10 is made of a thermosetting material, such as a common molding material such as silica gel or epoxy resin. The method of forming the plastic seal layer 10 may be selected from, but not limited to, compressive molding, paste printing, transfer molding, liquid encapsulant molding, vacuum lamination. Any one of methods such as spin coating.

For example, transfer molding is one of plastic molding methods, which is a method in which a closed metal mold is heated and pressed into a molten resin from a fine tube gate to be hardened and formed, and the forming precision is higher than that of compression molding. And can produce molded parts of very complicated shapes. Further, it is possible to simultaneously obtain a plurality of molded articles in a connected metal mold by performing one operation of charging the resin at one place. This molding method is mainly used for forming a thermosetting resin such as a phenol resin, a urea resin, a melamine, an epoxy resin, and a polyester, and is therefore also referred to as a press molding of a thermosetting resin.

Next, referring to FIG. 14, step S4 is performed: separating the adhesive layer 2 and the molding layer 10 to remove the carrier 1 and the adhesive layer 2.

Specifically, the method for separating the adhesive layer 2 and the plastic sealing layer 10 is selected from, but not limited to, chemical etching, mechanical peeling, and mechanical At least one of grinding, hot baking, ultraviolet light irradiation, laser ablation, chemical mechanical polishing, and wet peeling. For example, if the adhesive layer 2 is made of UV tape, the UV tape may be firstly reduced in viscosity by ultraviolet light irradiation, and then the carrier 1 and the adhesive layer 2 are detached from the plastic seal by tearing off. The layer 10, the chip 3 and the interconnect structure 4 are simpler and easier to operate than the thinning process, such as grinding, etching, etc., and the process cost can be greatly reduced.

Referring to FIG. 15 again, step S5 is performed: forming a first dielectric layer 11 on the upper surface of the plastic sealing layer 10, forming a second dielectric layer 12 on the lower surface, and forming the second dielectric layer 12 on the upper dielectric layer 11 and the second dielectric layer 12 A plurality of first via holes 13 corresponding to the semiconductor chip 3 and the conductive pillars 6 are formed.

Specifically, the first dielectric layer 11 and the second dielectric layer 12 may be the same or different materials, preferably low-k or ultra-low-K materials, including but not limited to silicon oxide, phosphosilicate glass, silicon oxycarbon compound, Polyimide, benzocyclobutene, polybenzoxazole, and the like. The first dielectric layer 11 and the second dielectric layer 12 may be formed by spin coating, thermal chemical vapor deposition, plasma enhanced chemical vapor deposition, or the like, depending on the material. Methods of forming the first vias 13 include, but are not limited to, laser drilling, mechanical drilling, deep reactive ion etching. If the first dielectric layer 11 and the second dielectric layer 12 are made of a photosensitive material, the first through holes 13 can be directly obtained by exposure and development, thereby simplifying the process steps.

Finally, referring to FIG. 16, step S6 is performed to form a redistribution wiring layer 14 on the semiconductor chip and the interconnect structure 4 based on the first dielectric layer 11 and the second dielectric layer 123 to realize inter-chip interconnection.

Specifically, the method for forming the redistribution wiring layer 14 includes, but is not limited to, at least one of physical vapor deposition, chemical vapor deposition, electroplating, and electroless plating; the redistribution wiring layer 14 may be a single layer or more The layer, the material of which is selected from, but not limited to, at least one of Al, Cu, Sn, Ni, Au, and Ag.

As shown in FIG. 16, the redistribution wiring layer 14 includes a conductive plug filled in the first through hole 13 and a metal line formed on the surfaces of the first dielectric layer 11 and the second dielectric layer 12. The conductive plugs may be formed separately from the metal lines or may be formed together. As an example, the first via hole 13 is first filled with a metal conductor by a process such as deposition, plating, or the like to form the conductive plug; and then formed by sputtering and electroplating on the first dielectric layer by photolithography. Metal circuit pattern.

Since the redistribution wiring layer 14 is distributed on the front and back sides of the semiconductor chip 3, the redistribution wiring layers of the front surface and the back surface of the same semiconductor chip or different semiconductor chips are connected through the interconnection structure, thereby maximizing the redistribution area, and Easily complete inter-chip interconnects without increasing chip size, which not only improves package performance, but also reduces package cost.

Further, the chip packaging method of the present invention further includes a step S7: forming a lower under bump metal layer 17 on the surface of the redistribution wiring layer 14 and a metal layer 17 under the bump as shown in FIGS. 17 and 18. Solder ball bumps 18 are formed on the surface.

Specifically, the step S7 includes:

Step S7-1: forming a third dielectric layer 15 covering the redistribution wiring layer 14 on the surface of the first dielectric layer 11 and the second dielectric layer 12, and in the third dielectric layer, as shown in FIG. Forming a plurality of third through holes 16 in 15;

Step S7-2: The under bump metal layer 17 and the solder ball bumps 18 are formed based on the third dielectric layer 15 and the third via holes 16 as shown in FIG.

The under bump metal layer 17 can prevent diffusion between the solder bumps 18 and the integrated circuit and achieve lower contact resistance. Generally, the under bump metal layer 17 may be a single layer or a plurality of layers of metal. As an example, the under bump metal layer 17 is a Ti/Cu composite layer. The material of the solder bumps 18 includes, but is not limited to, conductive metals such as Ag, Cu, and the like.

As shown in FIG. 19, each set of semiconductor chip interconnection package structures can be finally separated by a dicing process.

Embodiment 2

The present invention also provides a chip package structure, as shown in FIG. 19, the chip package structure includes:

Plastic sealing layer 10;

At least two semiconductor chips 3 embedded in the plastic sealing layer 10 and at least one interconnect structure 4; the interconnect structure 4 includes a support body and a plurality of conductive pillars penetrating the support body up and down;

a first dielectric layer 11 formed on an upper surface of the plastic sealing layer 10 and a second dielectric layer 12 on a lower surface; a plurality of electrically formed semiconductor chips 3 are electrically formed in the first dielectric layer 11 and the second dielectric layer 12 a first through hole corresponding to the conductive column;

A redistribution wiring layer 14 is formed of a conductive metal filled in the first via hole and a metal line distributed on the surfaces of the first dielectric layer 12 and the second dielectric layer 13.

Specifically, the surface of the redistribution lead layer 14 may further be formed with an under bump metal layer 17, and the solder bump bumps 18 are formed on the surface of the under bump metal layer 17. The third dielectric layer 15 covering the redistribution wiring layer 14 is formed on the surface of the first dielectric layer 11 and the second dielectric layer 12, and the third dielectric layer 15 is formed to accommodate the under bump metal. The third through hole of layer 17.

In particular, in the chip package structure of the present invention, not all of the semiconductor chips need to face up or face down, that is, at least one of the semiconductor chips may be disposed face down, and at least one of the semiconductor chips may be disposed face down.

As an example, FIG. 19 shows a case where two semiconductor chips are included in the chip package structure, in which one semiconductor chip faces upward and the other semiconductor chip faces downward, and redistribution leads are formed on the front and back sides of each semiconductor chip. Layer 14, thereby greatly expanding the redistribution area under the same device dimensions, and interconnection between the two semiconductor chips is easily achieved by the interconnection structure.

Specifically, the height of the interconnect structure 4 is preferably the same as or substantially the same as the semiconductor chip. The cross section of the conductive pillar includes at least one of a polygon, a circle, and an ellipse; the cross section of the support includes a polygon, a circle, and At least one of the elliptical shapes.

In the interconnect structure, the support 5 is preferably made of a low-k material (dielectric constant K ≤ 3.9), including but not limited to glass, polymer, silicon oxide, silicon nitride, and the like. The material of the conductive pillar 6 is selected from at least one of Al, Cu, Sn, Ni, Au, and Ag. The first dielectric layer 11 and the second dielectric layer 12 may be made of the same or different materials, preferably low-k or ultra-low-K materials, including but not limited to silicon oxide, phosphosilicate glass, silicon oxycarbon, polyacryl Any of an amine, a benzocyclobutene, and a polybenzoxazole.

The chip package structure of the present invention can greatly expand the redistribution area and improve the package performance without increasing the size of the device.

In summary, the present invention can effectively increase the redistribution area by adding an interconnect structure during the packaging process. With the aid of the interconnect structure, the redistribution area is not limited to the front side of the semiconductor chip (the exposed side of the pad), but can also be extended to the back side of the semiconductor chip. More importantly, in the packaging process, not all of the semiconductor chips need to be face up or face down, that is, part of the semiconductor chip faces up and part of the semiconductor chip faces down. Through the chip packaging method of the invention, the redistribution area can be maximized, the interconnection between the chip and the chip can be realized, and the production cost can be effectively saved. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications or variations of the above-described embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and scope of the invention will be covered by the appended claims.

Claims

A chip packaging method, comprising the steps of:

S1: providing a carrier, forming an adhesive layer on the surface of the carrier;

S2: adhering at least two semiconductor chips and at least one interconnect structure on a surface of the adhesive layer; the interconnect structure comprises a support body and a plurality of conductive pillars penetrating the support body up and down;

S3: forming a plastic seal layer on the surface of the adhesive layer, wherein the semiconductor chip and the interconnect structure are embedded in the plastic seal layer and expose the upper surface;

S4: separating the adhesive layer and the plastic sealing layer to remove the carrier and the adhesive layer;

S5: forming a first dielectric layer on the upper surface of the plastic sealing layer, forming a second dielectric layer on the lower surface, and forming a plurality of electrical leads and the conductive pillars in the first dielectric layer and the second dielectric layer Corresponding first through hole;

S6: forming a redistribution wiring layer on the semiconductor chip and the interconnect structure based on the first dielectric layer and the second dielectric layer to implement inter-chip interconnection.
The chip packaging method according to claim 1, wherein in the step S2, at least one of the semiconductor chips is adhered face down on the surface of the adhesive layer, and at least one of the semiconductor chips is bonded to the front side. Attached to the surface of the adhesive layer.
The chip packaging method according to claim 1, wherein the cross section of the conductive pillar comprises at least one of a polygon, a circle and an ellipse; the cross section of the support body comprises a polygon, a circle and an ellipse; At least one of the shapes.
The chip packaging method according to claim 1, wherein in the interconnect structure, each of the conductive pillars is arranged in a lattice.
The chip packaging method according to claim 1, wherein the forming method of the interconnect structure comprises the following steps:

(1) forming the support structure;

(2) forming a plurality of second through holes in the support structure;

(3) filling the second via hole with a metal to obtain the conductive pillar.
The chip packaging method according to claim 1, wherein the forming method of the interconnect structure comprises the following steps:

(1) providing a substrate, forming a plurality of vertically disposed conductive pillars on the surface of the substrate;

(2) forming a molding material covering the conductive pillar;

(3) removing excess molding material on the upper surface of the conductive post and removing the substrate to expose the lower surface of the conductive post, and the remaining molding material constitutes the support.
The chip packaging method according to claim 6, wherein in the step (1), the conductive pillar is formed on the surface of the substrate by a plating method or a wire drawing method.
The chip packaging method according to claim 1, further comprising a step S7 of: forming an under bump metal layer on the surface of the redistribution wiring layer, and forming a solder bump on the surface of the bump under the metal layer .
A chip package structure, comprising:

Plastic seal layer

At least two semiconductor chips embedded in the plastic sealing layer and at least one interconnect structure; the interconnect structure includes a support body and a plurality of conductive pillars penetrating the support body up and down;

a first dielectric layer formed on the upper surface of the plastic sealing layer and a second dielectric layer on the lower surface; wherein the first dielectric layer and the second dielectric layer are formed with a plurality of semiconductor chips electrically connected to the conductive pillars First through hole;

And a redistribution wiring layer composed of a conductive metal filled in the first via hole and a metal line distributed on the surfaces of the first dielectric layer and the second dielectric layer.
The chip package structure according to claim 9, wherein at least one of the chip package structures is disposed face up, and at least one of the semiconductor chips is disposed face down.