CN110957284A - Three-dimensional packaging structure of chip and packaging method thereof - Google Patents

Three-dimensional packaging structure of chip and packaging method thereof Download PDF

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Publication number
CN110957284A
CN110957284A CN201911229312.9A CN201911229312A CN110957284A CN 110957284 A CN110957284 A CN 110957284A CN 201911229312 A CN201911229312 A CN 201911229312A CN 110957284 A CN110957284 A CN 110957284A
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Prior art keywords
layer
packaging
metal
chips
chip
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CN201911229312.9A
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Inventor
陈彦亨
林正忠
吴政达
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SJ Semiconductor Jiangyin Corp
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SJ Semiconductor Jiangyin Corp
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Priority to CN201911229312.9A priority Critical patent/CN110957284A/en
Publication of CN110957284A publication Critical patent/CN110957284A/en
Priority to US17/112,835 priority patent/US11735564B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/24147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect not connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted, e.g. the upper semiconductor or solid-state body being mounted in a cavity or on a protrusion of the lower semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a three-dimensional packaging structure of a chip and a packaging method thereof, wherein the structure comprises the following components: more than two chips with welding pads are stacked in a step structure, and the welding pads are arranged in a step table top of the step structure; a metal connection post formed on the pad; the packaging layer covers the metal connecting column and the chip; a rewiring layer formed on the encapsulation layer; and the metal bump is formed on the rewiring layer. The plurality of chips are combined in a stacked manner in a stepped structure, and meanwhile, the welding pads arranged in the stepped table top of the stepped structure are electrically connected with the metal connecting columns to lead out a chip circuit, so that the whole packaging structure does not need a TSV (through silicon via) punching process, and the packaging cost of the packaging structure is effectively reduced; in addition, compared with the TSV process, the wire bonding process is mature and simple, and the yield of the packaging structure can be greatly improved; and finally, the packaging structure does not need substrate support, so that the packaging thickness of the packaging structure can be reduced.

Description

Three-dimensional packaging structure of chip and packaging method thereof
Technical Field
The invention belongs to the field of semiconductor packaging, and particularly relates to a three-dimensional packaging structure of a chip and a packaging method thereof.
Background
With the rapid development of the integrated circuit manufacturing industry, the front-end process of the integrated circuit has reached the back-end of moore's law, the process has reached the physical limit of exposure, and the investment cost is too high, so that people developing in the future will develop the development direction of advanced packaging in the back-end.
The existing semiconductor packaging technology comprises Ball Grid Array (BGA), Chip Size Package (CSP), Wafer Level Package (WLP), three-dimensional package (3D), System In Package (SiP) and the like, wherein the Wafer Level Package (WLP) is gradually adopted by most semiconductor manufacturers due to the excellent advantages, all or most of the process steps are finished on a silicon wafer which is subjected to the previous process, and finally the wafer is directly cut into separated independent devices.
In the existing three-dimensional packaging technology, the Through Silicon Via (TSV) technology is used for realizing three-dimensional stacking of chips, but the TSV has complex manufacturing process, high difficulty and high price, and the cost of three-dimensional packaging of the chips is directly increased.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a three-dimensional chip package structure and a package method thereof, which are used to solve the problems of complex three-dimensional chip package process, high package cost, and the like in the prior art.
To achieve the above and other related objects, the present invention provides a three-dimensional package structure of a chip, the three-dimensional package structure at least comprising:
the chip comprises more than two chips with welding pads, wherein the more than two chips are stacked in a stepped structure, and the welding pads are arranged in a stepped table top of the stepped structure;
the metal connecting column is formed on the welding pad and is electrically connected with the welding pad;
the packaging layer covers the metal connecting column and the chip, and the top surface of the packaging layer is exposed out of the metal connecting column;
a rewiring layer formed on the packaging layer, the metal connecting column being electrically connected with the rewiring layer;
and the metal bump is formed on the rewiring layer.
Optionally, the chip comprises a memory chip.
Optionally, the material of the pad comprises metallic aluminum.
Optionally, the material of the metal connection pillar includes at least one of gold, silver, aluminum, and copper, and the material of the encapsulation layer includes one of polyimide, silicone, and epoxy resin.
Optionally, the rewiring layer comprises a dielectric layer and a metal wiring layer, and the dielectric layer is made of one or a combination of more than two of the group consisting of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass; the material of the metal wiring layer includes one or a combination of two or more of the group consisting of copper, aluminum, nickel, gold, silver, and titanium.
Optionally, the metal bump includes one of a gold-tin solder ball, a silver-tin solder ball, and a copper-tin solder ball, or the metal bump includes a metal pillar and a solder ball formed on the metal pillar.
Optionally, the material of the metal pillar comprises copper or nickel.
The invention also provides a three-dimensional packaging method of the chip, which at least comprises the following steps:
providing a support substrate, and forming a separation layer on the support substrate, wherein the separation layer comprises a first surface which is in contact with the support substrate and a second surface which is opposite to the first surface;
providing more than two chips with welding pads, laminating and bonding the chips on the second surface of the separation layer, bonding two chips which are adjacent up and down, wherein the chips which are laminated and bonded are in a stepped structure, and the welding pads are arranged in the stepped mesa of the stepped structure;
forming a metal connecting column on the welding pad, wherein the metal connecting column is electrically connected with the welding pad;
packaging the metal connecting column and the chip by adopting a packaging layer, and exposing the metal connecting column on the top surface of the packaging layer;
forming a rewiring layer on the packaging layer, wherein the metal connecting column is electrically connected with the rewiring layer;
forming a metal bump on the rewiring layer;
and removing the separation layer and the support substrate.
Optionally, the support substrate comprises one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate; the separation layer comprises a polymer layer or an adhesive glue layer, the polymer layer or the adhesive glue layer is firstly coated on the surface of the support substrate by adopting a spin coating process, and then is cured and molded by adopting an ultraviolet curing or heat curing process.
Optionally, the chip is bonded on the second side of the separation layer by stacking using a surface mount process.
Optionally, the rewiring layer comprises a dielectric layer and a metal wiring layer, and the dielectric layer is made of one or a combination of more than two of the group consisting of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass; the material of the metal wiring layer includes one or a combination of two or more of the group consisting of copper, aluminum, nickel, gold, silver, and titanium.
Optionally, the step of forming the rewiring layer includes:
forming a dielectric layer on the surface of the packaging layer by adopting a chemical vapor deposition process or a physical vapor deposition process, and etching the dielectric layer to form a graphical dielectric layer;
and forming a metal wiring layer on the surface of the patterned dielectric layer by adopting a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, an electroplating process or a chemical plating process, etching the metal wiring layer to form a patterned metal wiring layer, wherein the metal connecting column is electrically connected with the patterned metal wiring layer.
As described above, according to the three-dimensional chip packaging structure and the packaging method thereof, the plurality of chips are combined in a stacked manner in the stepped structure, and meanwhile, the chip circuit is led out by electrically connecting the welding pad arranged in the stepped table top of the stepped structure with the metal connecting column, so that the chip circuit can be led out without a TSV (through silicon via) punching process in the whole packaging structure, and the packaging cost of the packaging structure is effectively reduced; in addition, compared with the TSV electric connection process, the routing process is mature and simple, and the yield of the packaging structure can be greatly improved; and finally, the packaging structure does not need substrate support, so that the packaging thickness of the packaging structure can be reduced.
Drawings
Fig. 1 is a flow chart illustrating a method for packaging a three-dimensional chip package structure according to the present invention.
Fig. 2 to 9 are schematic structural diagrams of steps of the method for packaging a three-dimensional package structure of a chip according to the present invention, wherein fig. 9 is a schematic structural diagram of the three-dimensional package structure of the chip according to the present invention.
Description of the element reference numerals
10 support substrate
11 separating layer
12 chips
121 pad
122 step table
13 metal connecting column
14 encapsulation layer
15 rewiring layer
151 dielectric layer
152 metal wiring layer
16 metal bump
S1-S7
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 9. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
As shown in fig. 9, the present embodiment provides a three-dimensional package structure of a chip, where the three-dimensional package structure includes:
more than two chips 12 with welding pads 121, wherein the more than two chips 12 are stacked in a step structure, and the welding pads 121 are arranged in a step table top of the step structure;
a metal connection stud 13 formed on the pad 121 and electrically connected to the pad 121;
an encapsulation layer 14 covering the metal connection posts 13 and the chip 12, and the top surface of the encapsulation layer 14 exposes the metal connection posts 13;
a rewiring layer 15 formed on the encapsulation layer 14, the metal connection posts 13 being electrically connected to the rewiring layer 15;
and a metal bump 16 formed on the rewiring layer 15.
According to the three-dimensional packaging structure of the chip, the chips are combined in a stacked manner in the stepped structure, meanwhile, the chip circuit is led out through the welding pad arranged in the stepped table top of the stepped structure and the metal connecting column (namely routing), the whole packaging structure does not need to lead out the chip circuit through the TSV hole, and the packaging cost of the packaging structure is effectively reduced; in addition, compared with the TSV electric connection process, the routing process is mature and simple, and the yield of the packaging structure can be greatly improved; and finally, the packaging structure does not need substrate support, so that the packaging thickness of the packaging structure can be reduced.
The chip 12 may be any existing semiconductor chip suitable for three-dimensional packaging, may be an independent functional chip, such as a memory chip, a circuit chip, etc., or may be an integrated functional chip, such as an APU chip, a GPU chip, etc., without limitation, and preferably, the packaging structure of the embodiment is more suitable for packaging of a memory chip.
As an example, the material of the pad 121 in the chip 12 includes metal aluminum, which is an aluminum pad. When the bonding pad 121 is prepared, in order to improve the electrical property of the bonding pad and the adhesion property with the chip 12, an adhesion layer may be further formed under the bonding pad 121, and an anti-reflection layer may be formed on the bonding pad 121.
As an example, the material of the metal connection post 13 includes at least one of gold, silver, aluminum, and copper.
By way of example, the material of the encapsulation layer 14 includes one of polyimide, silicone, and epoxy. The top surface of the encapsulation layer 14 is a flat surface that is ground or polished to improve the quality of the redistribution layer 15.
As an example, the redistribution layer 15 includes a dielectric layer 151 and a metal wiring layer 152, the material of the dielectric layer 151 includes one or a combination of two or more of the group consisting of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass; the material of the metal wiring layer 152 includes one or a combination of two or more of the group consisting of copper, aluminum, nickel, gold, silver, and titanium. It should be noted that the materials, the number of layers, and the distribution morphology of the dielectric layer 151 and the metal wiring layer 152 may be set according to the specific situation of the chip, and are not limited herein.
As an example, the metal bump 16 includes one of a gold-tin solder ball, a silver-tin solder ball, and a copper-tin solder ball, or the metal bump 16 includes a metal pillar and a solder ball formed on the metal pillar, and preferably, the metal pillar is a copper pillar or a nickel pillar. In this embodiment, the metal bump 16 is a gold-tin solder ball, and the manufacturing steps thereof include: firstly, forming a gold-tin layer on the surface of the rewiring layer 15, then refluxing the gold-tin layer into a spherical shape by adopting a high-temperature refluxing process, and cooling to form a gold-tin solder ball; or forming a gold-tin solder ball by adopting a ball planting process.
Example two
As shown in fig. 1 to 9, the present embodiment provides a three-dimensional packaging method for a chip, and the three-dimensional packaging structure of the chip according to the first embodiment may be prepared by the packaging method, but is not limited to the packaging method of the present embodiment.
Specifically, fig. 2 to 9 illustrate schematic structural diagrams presented in each step of the three-dimensional packaging method in this embodiment.
As shown in fig. 1 and fig. 2, step S1 is performed to provide a support substrate 10, and form a separation layer 11 on the support substrate 10, where the separation layer 11 includes a first surface contacting the support substrate 10 and an opposite second surface.
The support substrate 10 includes, as an example, one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate. In this embodiment, the support substrate 10 is a glass substrate, which has a low cost, is easy to form the separation layer 11 on the surface thereof, and can reduce the difficulty of the subsequent stripping process.
As an example, the separation layer 11 includes a polymer layer or an adhesive glue layer, which is first coated on the surface of the support substrate 10 by a spin coating process and then cured by a uv curing or thermal curing process.
In the present embodiment, the polymer layer includes a LTHC light-to-heat conversion layer, which may be subsequently heated based on laser light when the supporting substrate 10 is peeled off, so that the chip 12 and the supporting substrate 10 are separated from each other.
As shown in fig. 1 and 3, step S2 is performed to provide two or more chips 12 having bonding pads 121, and the chips 12 are stacked and bonded on the second surface of the separation layer 11, two chips 12 adjacent to each other in the upper and lower directions are bonded, and the stacked and bonded chips 12 have a stepped structure, and the bonding pads 121 are disposed in the stepped mesa 122 having the stepped structure.
The chip 12 may be any existing semiconductor chip suitable for three-dimensional packaging, may be an independent functional chip, such as a memory chip, a circuit chip, etc., or may be an integrated functional chip, such as an APU chip, a GPU chip, etc., without limitation, and preferably, the packaging structure of the embodiment is more suitable for packaging of a memory chip.
As an example, the chips 12 are laminated and bonded on the second surface of the separation layer 11 by using a surface mount process.
As an example, the material of the pad 121 in the chip 12 includes metal aluminum, which is an aluminum pad. When the bonding pad 121 is prepared, in order to improve the electrical property of the bonding pad and the adhesion property with the chip 12, an adhesion layer may be further formed under the bonding pad 121, and an anti-reflection layer may be formed on the bonding pad 121.
It should be noted that, in the chip stacking structure with the ladder-type structure, the functions of each layer of chips may be the same or different, the sizes of the step mesas of each layer of chips may be the same or different, and the above parameters may be set according to the specific packaging requirements of the packaging structure, which is not limited herein.
As shown in fig. 1 and 4, step S3 is performed to form a metal connection stud 13 on the pad 121, wherein the metal connection stud 13 is electrically connected to the pad 121.
As an example, the metal connection post 13 is manufactured by a wire bonding process, which includes one of a thermocompression bonding process, an ultrasonic bonding process, and a thermocompression ultrasonic bonding process; the material of the metal connecting column 13 comprises at least one of gold, silver, aluminum and copper.
As an example, the metal connection post 13 is manufactured by electroplating or chemical plating; the material of the metal connecting column 13 comprises at least one of gold, silver, aluminum and copper.
Of course, the metal connection post 13 may also be formed by other conventional wire bonding processes to implement circuit lead-out of the chip, which is not limited herein.
As shown in fig. 1, fig. 5 and fig. 6, step S4 is performed to encapsulate the metal connection studs 13 and the chip 12 with an encapsulation layer 14, and expose the metal connection studs 13 from the top surface of the encapsulation layer 14.
As an example, the method of encapsulating the metal connection posts 13 and the chip 12 with the encapsulation layer 14 includes one of compression molding, transfer molding, liquid sealing, vacuum lamination, and spin coating. The material of the encapsulation layer 14 includes one of polyimide, silicone, and epoxy resin.
Specifically, as shown in fig. 5 and 6, after the encapsulation layer 14 is formed, a grinding or polishing method may be used to act on the upper surface of the encapsulation layer 14, so as to provide the first encapsulation layer 14 with a flat surface, thereby improving the product quality.
As shown in fig. 1 and 7, step S5 is performed to form a redistribution layer 15 on the package layer 14, and the metal connection stud 13 is electrically connected to the redistribution layer 15.
As shown in fig. 6, the redistribution layer 15 includes a dielectric layer 151 and a metal wiring layer 152, as an example; the dielectric layer 151 is made of one or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass; the material of the metal wiring layer 152 includes one or a combination of two or more of the group consisting of copper, aluminum, nickel, gold, silver, and titanium.
As an example, forming the re-wiring layer includes the steps of: firstly, forming a dielectric layer 151 on the surface of the packaging layer 14 by adopting a chemical vapor deposition process or a physical vapor deposition process, and etching the dielectric layer 151 to form a patterned dielectric layer 151; and then, forming a metal wiring layer 152 on the surface of the patterned dielectric layer 151 by adopting a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, an electroplating process or a chemical plating process, etching the metal wiring layer 152 to form a patterned metal wiring layer 152, wherein the metal connecting column 13 is electrically connected with the patterned metal wiring layer 152. It should be noted that the materials, the number of layers, and the distribution morphology of the dielectric layer 151 and the metal wiring layer 152 may be set according to the specific situation of the chip, and are not limited herein.
As shown in fig. 1 and 8, step S6 is performed to form metal bumps 16 on the redistribution layer 15.
As an example, the metal bump 16 includes one of a gold-tin solder ball, a silver-tin solder ball, and a copper-tin solder ball, or the metal bump 16 includes a metal pillar and a solder ball formed on the metal pillar, and preferably, the metal pillar is a copper pillar or a nickel pillar. In this embodiment, the metal bump 16 is a gold-tin solder ball, and the manufacturing steps thereof include: firstly, forming a gold-tin layer on the surface of the rewiring layer 15, then refluxing the gold-tin layer into a spherical shape by adopting a high-temperature refluxing process, and cooling to form a gold-tin solder ball; or forming a gold-tin solder ball by adopting a ball planting process.
As shown in fig. 1 and 9, step S7 is finally performed to remove the separation layer 11 and the support substrate 10.
When the separation layer 11 includes an adhesive layer, the adhesive layer may be rendered less tacky by exposure to effect separation from the chip 12; when the separation layer 11 includes the LTHC light-to-heat conversion layer, the LTHC light-to-heat conversion layer is heated based on laser light to separate the chip 12 and the support substrate 10 from each other.
In summary, according to the three-dimensional packaging structure of the chip and the packaging method thereof, the plurality of chips are combined in a stacked manner in the stepped structure, and meanwhile, the lead-out of the chip circuit is realized by electrically connecting the welding pad arranged in the stepped table top of the stepped structure with the metal connecting column, so that the lead-out of the chip circuit can be realized without the TSV punching process in the whole packaging structure, and the packaging cost of the packaging structure is effectively reduced; in addition, compared with the TSV electric connection process, the routing process is mature and simple, and the yield of the packaging structure can be greatly improved; and finally, the packaging structure does not need substrate support, so that the packaging thickness of the packaging structure can be reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (12)

1. A three-dimensional packaging structure of a chip, the three-dimensional packaging structure at least comprising:
the chip comprises more than two chips with welding pads, wherein the more than two chips are stacked in a stepped structure, and the welding pads are arranged in a stepped table top of the stepped structure;
the metal connecting column is formed on the welding pad and is electrically connected with the welding pad;
the packaging layer covers the metal connecting column and the chip, and the top surface of the packaging layer is exposed out of the metal connecting column;
a rewiring layer formed on the packaging layer, the metal connecting column being electrically connected with the rewiring layer;
and the metal bump is formed on the rewiring layer.
2. The three-dimensional package structure of chips of claim 1, wherein: the chip includes a memory chip.
3. The three-dimensional package structure of chips of claim 1, wherein: the material of the welding pad comprises metal aluminum.
4. The three-dimensional package structure of chips of claim 1, wherein: the material of the metal connecting column comprises at least one of gold, silver, aluminum and copper, and the material of the packaging layer comprises one of polyimide, silica gel and epoxy resin.
5. The three-dimensional package structure of chips of claim 1, wherein: the rewiring layer comprises a dielectric layer and a metal wiring layer, and the dielectric layer is made of one or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass; the material of the metal wiring layer includes one or a combination of two or more of the group consisting of copper, aluminum, nickel, gold, silver, and titanium.
6. The three-dimensional package structure of chips of claim 1, wherein: the metal bump comprises one of a gold-tin solder ball, a silver-tin solder ball and a copper-tin solder ball, or the metal bump comprises a metal column and a solder ball formed on the metal column.
7. The three-dimensional package structure of chips of claim 6, wherein: the material of the metal pillar comprises copper or nickel.
8. A three-dimensional packaging method for a chip is characterized by at least comprising the following steps:
providing a support substrate, and forming a separation layer on the support substrate, wherein the separation layer comprises a first surface which is in contact with the support substrate and a second surface which is opposite to the first surface;
providing more than two chips with welding pads, laminating and bonding the chips on the second surface of the separation layer, bonding two chips which are adjacent up and down, wherein the chips which are laminated and bonded are in a stepped structure, and the welding pads are arranged in the stepped mesa of the stepped structure;
forming a metal connecting column on the welding pad, wherein the metal connecting column is electrically connected with the welding pad;
packaging the metal connecting column and the chip by adopting a packaging layer, and exposing the metal connecting column on the top surface of the packaging layer;
forming a rewiring layer on the packaging layer, wherein the metal connecting column is electrically connected with the rewiring layer;
forming a metal bump on the rewiring layer;
and removing the separation layer and the support substrate.
9. The three-dimensional packaging method of chips according to claim 8, characterized in that: the support substrate comprises one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate; the separation layer comprises a polymer layer or an adhesive glue layer, the polymer layer or the adhesive glue layer is firstly coated on the surface of the support substrate by adopting a spin coating process, and then is cured and molded by adopting an ultraviolet curing or heat curing process.
10. The three-dimensional packaging method of chips according to claim 8, characterized in that: and laminating and combining the chip on the second surface of the separation layer by adopting a surface mounting process.
11. The three-dimensional packaging method of chips according to claim 8, characterized in that: the rewiring layer comprises a dielectric layer and a metal wiring layer, and the dielectric layer is made of one or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass; the material of the metal wiring layer includes one or a combination of two or more of the group consisting of copper, aluminum, nickel, gold, silver, and titanium.
12. The three-dimensional packaging method of chips according to claim 11, wherein the step of forming the rewiring layer includes:
forming a dielectric layer on the surface of the packaging layer by adopting a chemical vapor deposition process or a physical vapor deposition process, and etching the dielectric layer to form a graphical dielectric layer;
and forming a metal wiring layer on the surface of the patterned dielectric layer by adopting a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, an electroplating process or a chemical plating process, etching the metal wiring layer to form a patterned metal wiring layer, wherein the metal connecting column is electrically connected with the patterned metal wiring layer.
CN201911229312.9A 2019-12-04 2019-12-04 Three-dimensional packaging structure of chip and packaging method thereof Pending CN110957284A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022165749A1 (en) * 2021-02-05 2022-08-11 Yangtze Memory Technologies Co., Ltd. Flip-chip stacking structures and methods for forming the same
CN114975416A (en) * 2022-04-29 2022-08-30 盛合晶微半导体(江阴)有限公司 Three-dimensional fan-out type memory packaging structure and packaging method thereof
CN114975242A (en) * 2022-04-25 2022-08-30 盛合晶微半导体(江阴)有限公司 Preparation method of 2.5D packaging structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022165749A1 (en) * 2021-02-05 2022-08-11 Yangtze Memory Technologies Co., Ltd. Flip-chip stacking structures and methods for forming the same
CN114975242A (en) * 2022-04-25 2022-08-30 盛合晶微半导体(江阴)有限公司 Preparation method of 2.5D packaging structure
CN114975242B (en) * 2022-04-25 2023-06-27 盛合晶微半导体(江阴)有限公司 Preparation method of 2.5D packaging structure
CN114975416A (en) * 2022-04-29 2022-08-30 盛合晶微半导体(江阴)有限公司 Three-dimensional fan-out type memory packaging structure and packaging method thereof

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