CN112289742A - Wafer system level three-dimensional fan-out type packaging structure and manufacturing method thereof - Google Patents

Wafer system level three-dimensional fan-out type packaging structure and manufacturing method thereof Download PDF

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Publication number
CN112289742A
CN112289742A CN202011310588.2A CN202011310588A CN112289742A CN 112289742 A CN112289742 A CN 112289742A CN 202011310588 A CN202011310588 A CN 202011310588A CN 112289742 A CN112289742 A CN 112289742A
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China
Prior art keywords
layer
rewiring
rewiring layer
packaging
plastic packaging
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CN202011310588.2A
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Chinese (zh)
Inventor
陈彦亨
林正忠
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SJ Semiconductor Jiangyin Corp
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SJ Semiconductor Jiangyin Corp
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Priority to CN202011310588.2A priority Critical patent/CN112289742A/en
Publication of CN112289742A publication Critical patent/CN112289742A/en
Priority to US17/531,631 priority patent/US20220165654A1/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention provides a wafer system level three-dimensional fan-out type packaging structure and a manufacturing method thereof, wherein the method comprises the following steps: forming a rewiring layer including a first face and a second face which are oppositely arranged; forming a conductive connection column on the second surface of the rewiring layer; bonding the patch element to the second face of the rewiring layer; forming a plastic packaging layer on the second surface of the rewiring layer; thinning the plastic packaging layer; forming a plurality of solder bumps on one side of the plastic packaging layer, which is far away from the rewiring layer; cutting the rewiring layer and the plastic packaging layer to obtain a plurality of first packaging bodies; the second package is bonded to the first surface of the rewiring layer of the first package. According to the invention, the wafer-level packaging is adopted to plastically package the patch element on one surface of the rewiring layer, the first packaging bodies are obtained by cutting, and then the second packaging bodies are jointed on the other surface of the rewiring layer, so that the double-surface plastic-packaged system-level packaging structure is obtained, the function integration of the fan-out type packaging structure can be increased, the function and efficiency of a single chip are improved, and the volume is optimized.

Description

Wafer system level three-dimensional fan-out type packaging structure and manufacturing method thereof
Technical Field
The invention belongs to the field of semiconductor packaging, and relates to a wafer system level three-dimensional fan-out type packaging structure and a manufacturing method thereof.
Background
With the advent of the 5G communication and Artificial Intelligence (AI) era, the amount of data to be transmitted and processed interactively at high speed is enormous for chips applied in such related fields, which usually have huge number of pad pins (hundreds or even thousands), ultra-fine pin sizes and pitches (several microns or even smaller). On the other hand, the demands on the mobile internet and the internet of things are more and more strong, and the miniaturization and the multi-functionalization of electronic terminal products become a great trend of industrial development. How to integrate and package a plurality of different high-density chips together to form a system or subsystem with powerful function and smaller volume and power consumption becomes a great challenge in the field of advanced packaging of semiconductor chips.
At present, for multi-chip integrated packaging of such high-density chips, the industry generally adopts Through Silicon Vias (TSVs), silicon interposer (Si interposer) and other manners, so as to lead out and effectively interconnect ultra-fine pins of the chips to form a functional module or system, but the technology has higher cost, thereby greatly limiting the application range thereof.
With the continuing demand for higher functionality, better performance and higher energy efficiency, lower manufacturing costs and smaller dimensions, fan-out wafer level packaging (FOWLP) technology has become one of the most promising technologies to meet the demands of electronic devices for mobile and network applications. The fan-out packaging technology provides a good platform for realizing integrated packaging of multiple chips by adopting a mode of reconstructing wafers and rewiring RDL (remote desktop language), but the existing fan-out packaging technology has the problems of large area, high thickness and the like of a packaging body due to limited wiring precision, and various working procedures and low reliability.
In order to adapt to the development trend of multiple functions, miniaturization, portability, high speed, low power consumption and high reliability of the microelectronic packaging technology, a system-In-package (SIP) technology is used as a new heterogeneous integration technology and becomes a packaging form of more and more chips, and the system-In-package integrates various functional chips and components In one package, so that a complete function is realized. The system-in-package is a novel packaging technology and has the advantages of short development period, more functions, lower power consumption, better performance, lower cost price, smaller volume, light weight and the like.
However, with the increasing demands for package components and functions, the conventional system-in-package occupies an increasing area and thickness, which is not favorable for increasing the integration level.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a wafer level three-dimensional fan-out package structure and a method for fabricating the same, which are used to solve the problem that the volume of the system level package is difficult to be reduced in the prior art.
To achieve the above and other related objects, the present invention provides a method for fabricating a wafer level three-dimensional fan-out package structure, comprising the steps of:
forming a rewiring layer, wherein the rewiring layer comprises a first surface and a second surface which are oppositely arranged, and the rewiring layer comprises at least one dielectric layer and at least one metal wiring layer which are stacked in the vertical direction;
forming a conductive connection post on a second side of the rewiring layer, the conductive connection post being electrically connected to the rewiring layer;
providing a patch element, bonding the patch element on the second surface of the rewiring layer, wherein the patch element is electrically connected with the rewiring layer;
forming a plastic packaging layer on the second surface of the rewiring layer, wherein the plastic packaging layer covers the conductive connecting column and the patch element;
thinning the plastic packaging layer to expose the conductive connecting column;
forming a plurality of solder bumps on one side of the plastic packaging layer, which is far away from the rewiring layer, wherein at least one solder bump is electrically connected with the conductive connecting column;
cutting the rewiring layer and the plastic packaging layer to obtain a plurality of first packaging bodies;
and providing a second packaging body, and bonding the second packaging body to the first surface of the rewiring layer of the first packaging body, wherein the second packaging body is electrically connected with the rewiring layer.
Optionally, the method further comprises the following steps: and providing a carrier, and forming a release layer on the carrier, wherein the rewiring layer is formed on the release layer, and the first surface of the rewiring layer is connected with the release layer.
Optionally, before dicing, the carrier and the release layer are removed to expose the first side of the rewiring layer.
Optionally, the method further comprises the following steps: and forming a through hole, wherein the through hole is opened from the first surface of the rewiring layer and extends towards the direction of the second surface of the rewiring layer so as to expose the metal wiring layer.
Optionally, the through holes are formed using a laser drilling method.
Optionally, a conductive bump is disposed on one side of the second package body, and the conductive bump extends into the through hole to be electrically connected to the metal wiring layer.
Optionally, the method further includes the step of forming an insulating layer on a surface of the plastic package layer away from the rewiring layer, and forming an under-bump metal layer on the surface of the insulating layer, where the solder bump is formed on the surface of the under-bump metal layer away from the plastic package layer.
Optionally, the patch element comprises a passive element.
The invention also provides a wafer system level three-dimensional fan-out package structure, comprising:
the rewiring layer comprises a first surface and a second surface which are oppositely arranged, and the rewiring layer comprises at least one dielectric layer and at least one metal wiring layer which are stacked in the vertical direction;
a patch element bonded to the second surface of the rewiring layer and electrically connected to the rewiring layer;
the plastic packaging layer is positioned on the second surface of the rewiring layer and covers the patch element;
the conductive connecting column penetrates through the plastic packaging layer in the vertical direction and is electrically connected with the rewiring layer;
the solder bumps are distributed on one side, away from the rewiring layer, of the plastic packaging layer, and at least one solder bump is electrically connected with the conductive connecting column;
and the packaging body is jointed with the first surface of the rewiring layer and is electrically connected with the rewiring layer.
Optionally, a through hole is formed in the redistribution layer, the through hole is opened from a first surface of the redistribution layer and extends toward a second surface of the redistribution layer to expose the metal routing layer, and a conductive bump is arranged on one surface of the package body and extends into the through hole to be electrically connected with the metal routing layer.
Optionally, the solder bump package structure further comprises an insulating layer and an under bump metal layer, wherein the insulating layer is located on one surface of the plastic package layer, which is away from the rewiring layer, and the under bump metal layer is located on one surface of the solder bump, which faces the plastic package layer, and is in contact with the insulating layer.
Optionally, the patch element comprises a passive element.
As described above, according to the wafer-level three-dimensional fan-out package structure and the manufacturing method thereof of the present invention, the chip component is first subjected to plastic package by using the wafer-level package on one side of the redistribution layer, and is cut to obtain the plurality of first package bodies, and then the second package body is bonded to the other side of the redistribution layer, so as to obtain the double-sided plastic package-level package structure. The invention can increase the functional integration of the fan-out type packaging structure, improve the function and efficiency of a single chip and optimize the volume.
Drawings
Fig. 1 is a process flow diagram of a method for fabricating a wafer-level three-dimensional fan-out package structure according to the present invention.
Fig. 2 is a schematic diagram illustrating a carrier provided for a method of fabricating a wafer-level three-dimensional fan-out package structure according to the present invention.
Fig. 3 is a schematic diagram illustrating a release layer formed on the carrier according to the method for fabricating the wafer-level three-dimensional fan-out package structure of the present invention.
Fig. 4 is a schematic diagram illustrating a redistribution layer formed on the release layer according to the method for fabricating the wafer system level three-dimensional fan-out package structure of the present invention.
Fig. 5 is a schematic diagram illustrating the method for fabricating a wafer-level three-dimensional fan-out package structure according to the present invention, wherein conductive connection studs are formed on the second surface of the redistribution layer.
Fig. 6 is a schematic diagram showing a method for manufacturing a wafer system level three-dimensional fan-out package structure according to the present invention, in which a patch element is provided and the patch element is bonded to the second surface of the redistribution layer.
Fig. 7 is a schematic view illustrating a molding layer formed on the second surface of the redistribution layer according to the method for fabricating the wafer system level three-dimensional fan-out package structure of the present invention.
Fig. 8 is a schematic diagram illustrating the method for manufacturing a wafer-level three-dimensional fan-out package structure according to the present invention, in which the molding layer is thinned to expose the conductive connection stud.
Fig. 9 is a schematic diagram illustrating a method for manufacturing a wafer system level three-dimensional fan-out package structure according to the present invention, in which a plurality of solder bumps are formed on a side of the molding layer away from the redistribution layer.
Fig. 10 is a schematic diagram illustrating the method for fabricating a wafer-level three-dimensional fan-out package structure further removing the carrier and the release layer to expose the first surface of the redistribution layer according to the present invention.
Fig. 11 is a schematic diagram illustrating a method for manufacturing a wafer system level three-dimensional fan-out package structure according to the present invention, in which a through hole is formed in a dielectric layer in the redistribution layer.
Fig. 12 shows that the redistribution layer and the molding layer are cut to obtain a plurality of first package bodies according to the method for manufacturing the wafer system level three-dimensional fan-out package structure of the present invention.
Fig. 13 is a schematic view illustrating a second package provided by the method for manufacturing a wafer-level three-dimensional fan-out package structure of the present invention and the second package is bonded to a first surface of the redistribution layer of the first package.
Description of the element reference numerals
S1-S8
1 vector
2 Release layer
3 rewiring layer
301 dielectric layer
302 metal wiring layer
4 conductive connecting column
5 Patch element
6 Plastic packaging layer
7 solder bump
8 insulating layer
9 bump under metal layer
10 blue film
11 Metal frame
12 second package
13 conductive bump
14 through hole
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 13. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The present embodiment provides a method for manufacturing a wafer level three-dimensional fan-out package structure, please refer to fig. 1, which shows a process flow diagram of the method, including the following steps:
s1: forming a rewiring layer, wherein the rewiring layer comprises a first surface and a second surface which are oppositely arranged, and the rewiring layer comprises at least one dielectric layer and at least one metal wiring layer which are stacked in the vertical direction;
s2: forming a conductive connection post on a second side of the rewiring layer, the conductive connection post being electrically connected to the rewiring layer;
s3: providing a patch element, bonding the patch element on the second surface of the rewiring layer, wherein the patch element is electrically connected with the rewiring layer;
s4: forming a plastic packaging layer on the second surface of the rewiring layer, wherein the plastic packaging layer covers the conductive connecting column and the patch element;
s5: thinning the plastic packaging layer to expose the conductive connecting column;
s6: forming a plurality of solder bumps on one side of the plastic packaging layer, which is far away from the rewiring layer, wherein at least one solder bump is electrically connected with the conductive connecting column;
s7: cutting the rewiring layer and the plastic packaging layer to obtain a plurality of first packaging bodies;
s8: and providing a second packaging body, and bonding the second packaging body to the first surface of the rewiring layer of the first packaging body, wherein the second packaging body is electrically connected with the rewiring layer.
Referring to fig. 2 to 4, step S1 is executed: and forming a rewiring layer, wherein the rewiring layer comprises a first surface and a second surface which are oppositely arranged, and the rewiring layer comprises at least one dielectric layer and at least one metal wiring layer which are stacked in the vertical direction.
Specifically, as shown in fig. 2, a carrier 1 is provided. The carrier 1 is used for preventing the layer structure from cracking, warping, breaking, etc. during the packaging process, and the shape of the carrier 1 may be wafer-shaped, panel-shaped, or any other desired shape, including but not limited to any one of glass, metal, semiconductor, polymer, and ceramic. In this embodiment, the carrier 1 is made of glass, which is low in cost, and is easy to form a release layer on the surface thereof, and can reduce the difficulty of the subsequent stripping process.
As shown in fig. 3, a release layer 2 is formed on the carrier 1. The release layer 2 may be made of adhesive tape or polymer, and may be uv-cured or thermally cured.
As shown in fig. 4, a rewiring layer 3 is formed on the release layer 2, and a first surface of the rewiring layer 3 is connected to the release layer 2.
As an example, the redistribution layer 3 includes at least one dielectric layer 301 and at least one metal wiring layer 302 stacked in a vertical direction.
As an example, the fabrication of the rewiring layer 3 comprises the following steps:
(1) and forming a first dielectric layer on the surface of the release layer by adopting a chemical vapor deposition process, a physical vapor deposition process or other suitable processes, wherein the material of the first dielectric layer comprises but is not limited to one or the combination of more than two of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass. In this embodiment, the first dielectric layer is made of PI (polyimide), so as to further reduce the process difficulty and the process cost.
(2) And forming a first metal layer on the surface of the first medium layer by adopting sputtering, electroplating, chemical plating or other suitable processes, and etching the first metal layer to form a patterned first metal wiring layer. The material of the first metal wiring layer comprises one or the combination of more than two of copper, aluminum, nickel, gold, silver and titanium.
(3) And forming a second dielectric layer on the surface of the patterned first metal wiring layer by adopting a chemical vapor deposition process, a physical vapor deposition process or other suitable processes, and etching the second dielectric layer to form the second dielectric layer with the patterned through hole. The material of the second dielectric layer includes but is not limited to one or a combination of more than two of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass. In this embodiment, the second dielectric layer is made of PI (polyimide), so as to further reduce the process difficulty and the process cost.
In this embodiment, it is shown that the redistribution layer 3 includes two dielectric layers and one metal routing layer, and a through hole exposing the metal routing layer is formed in the dielectric layer located on the upper layer. In other embodiments, the absorption step may also continue to be performed:
(4) and filling the conductive plugs in the patterned through holes by adopting sputtering, electroplating, chemical plating or other suitable processes, forming a second metal layer on the surface of the second dielectric layer by adopting sputtering, electroplating, chemical plating or other suitable processes, and etching the metal layer to form a patterned second metal wiring layer. The second metal wiring layer is made of one or a combination of more than two of copper, aluminum, nickel, gold, silver and titanium.
And (3) repeating the steps (3) to (4) one or more times as required to form a rewiring layer with a multi-layer stacked structure to realize different wiring functions, and finally, a through hole for exposing the metal wiring layer at the top layer is formed in the dielectric layer at the top layer.
Referring to fig. 5, step S2 is executed: a wire bonding process, a deposition process, or other suitable process is used to form a conductive via 4 on the second side of the redistribution layer 3, and the conductive via 4 is electrically connected to the redistribution layer 3.
Referring to fig. 6, step S3 is executed: a patch element 5 is provided, and the patch element 5 is bonded to the second surface of the redistribution layer 3, and the patch element 5 is electrically connected to the redistribution layer 3.
As an example, the patch element 5 includes a passive element, such as a resistor, an inductor, a capacitor, etc., and the patch element 5 may be bonded to the second surface of the redistribution layer 3 by a surface mount process to achieve electrical connection with the redistribution layer 3.
Referring to fig. 7, step S4 is executed: a molding layer 6 is formed on the second side of the redistribution layer 3, the molding layer 6 covering the conductive connection posts 4 and the patch element 5.
By way of example, the molding layer 6 may be formed by any one of compression molding, transfer molding, liquid sealing, vacuum lamination, and spin coating, and the material of the molding layer 6 may be a curable material, such as a polymer-based material, a resin-based material, a polyamide, an epoxy resin, and any combination thereof.
Referring to fig. 8, step S5 is executed: and thinning the plastic packaging layer 6 to expose the conductive connecting column 4.
Referring to fig. 9, step S6 is executed: and forming a plurality of solder bumps 7 on one side of the plastic packaging layer 6, which is far away from the rewiring layer 3, wherein at least one solder bump 7 is electrically connected with the conductive connecting column 4.
As an example, an insulating layer 8 is formed on a surface of the plastic package layer 6 away from the redistribution layer 3, an under bump metal layer 9 is formed on a surface of the insulating layer 8, and then the solder bump 7 is formed on a surface of the under bump metal layer 9 away from the plastic package layer 6. The material of the insulating layer 8 includes but is not limited to silicon oxide, the material of the under bump metal layer 9 includes but is not limited to copper, nickel, tin silver, etc., and the solder bump 7 may be composed of a metal pillar, a solder joint, or only a solder ball.
Referring to fig. 10, the carrier 1 and the release layer 2 are further removed to expose the first surface of the redistribution layer 3.
Specifically, the viscosity of the release layer 2 is reduced by a corresponding method according to the type of the release layer 2, and the carrier 1 and the release layer 2 are peeled off. For example, when the release layer 2 employs a photothermal conversion material, the photothermal conversion layer may be irradiated with laser light to separate the photothermal conversion layer from the rewiring layer 3 and the support 1.
Referring to fig. 11, a via 14 is formed in the dielectric layer in the redistribution layer 3 by a laser drilling method or other suitable methods, and the via 14 is opened from the first surface of the redistribution layer 3 and extends toward the second surface of the redistribution layer 3 to expose the metal routing layer.
Referring to fig. 12, step S7 is executed: and cutting the rewiring layer 3 and the plastic packaging layer 6 to obtain a plurality of first packaging bodies. For example, the side of the structure having the solder bumps 7 obtained as described above may be covered with a blue film 10, fixed to a metal frame 11, and then cut with a blade.
Referring to fig. 13, step S8 is executed: providing a second package body 12, and bonding the second package body 12 to the first surface of the redistribution layer 3 of the first package body, wherein the second package body 12 is electrically connected with the redistribution layer 3.
By way of example, the second package 12 may have at least one functional chip disposed therein, including but not limited to a system-on-chip, a power management chip, a memory chip, and the like. The three-dimensional stacked package structure composed of the first package body and the second package body 12 integrates various functional chips and patch elements into one package structure, so that various different system function requirements can be realized, and the performance of a package system is improved.
As an example, one surface of the second package body 12 is provided with a conductive bump 13, and the conductive bump 13 extends into the through hole 14 to be electrically connected to the metal wiring layer 302.
Thus, a wafer system level three-dimensional fan-out package structure is manufactured, as shown in fig. 13, the wafer system level three-dimensional fan-out package structure includes a first package body and a second package body 12, the first package body includes a redistribution layer 3, a chip component 5, a plastic package layer 6, a conductive connection column 4 and a plurality of solder bumps 7, wherein the redistribution layer 3 includes a first surface and a second surface which are oppositely arranged, and includes at least one dielectric layer 301 and at least one metal wiring layer 302 which are stacked in a vertical direction; the patch element 5 is bonded to the second surface of the rewiring layer 3 and electrically connected to the rewiring 3 layer; the plastic packaging layer 6 is positioned on the second side of the rewiring layer 3 and covers the patch element 5; the conductive connecting column 4 penetrates through the plastic packaging layer 6 in the vertical direction and is electrically connected with the rewiring layer 3, the solder bumps 7 are distributed on one side, away from the rewiring layer 3, of the plastic packaging layer 6, and at least one solder bump 7 is electrically connected with the conductive connecting column 4; the second package 12 is bonded to the first surface of the redistribution layer 3 of the first package, and is electrically connected to the redistribution layer 3.
As an example, a through hole 14 is formed in the redistribution layer 3, the through hole 14 is opened from a first side of the redistribution layer 3 and extends toward a second side of the redistribution layer 3 to expose the metal wiring layer 302, a conductive bump 13 is formed on one side of the second package, and the conductive bump 13 extends into the through hole 14 to be electrically connected to the metal wiring layer 302.
As an example, the wafer system level three-dimensional fan-out package structure further includes an insulating layer 8 and an under bump metal layer 9, where the insulating layer 8 is located on a surface of the plastic package layer 6 away from the redistribution layer 3, and the under bump metal layer 9 is located on a surface of the solder bump 7 facing the plastic package layer 6 and is in contact with the insulating layer 8.
The patch element 5 comprises, as an example, passive elements such as resistors, inductors, capacitors, etc.
In summary, in the wafer-level three-dimensional fan-out package structure and the manufacturing method thereof of the present invention, the chip component is first plastic-packaged on one side of the redistribution layer by the wafer-level package, and is cut to obtain a plurality of first package bodies, and then the second package body is bonded to the other side of the redistribution layer to obtain the double-sided plastic-packaged system-level package structure. The invention can increase the functional integration of the fan-out type packaging structure, improve the function and efficiency of a single chip and optimize the volume. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (12)

1. A manufacturing method of a wafer system level three-dimensional fan-out type packaging structure is characterized by comprising the following steps:
forming a rewiring layer, wherein the rewiring layer comprises a first surface and a second surface which are oppositely arranged, and the rewiring layer comprises at least one dielectric layer and at least one metal wiring layer which are stacked in the vertical direction;
forming a conductive connection post on a second side of the rewiring layer, the conductive connection post being electrically connected to the rewiring layer;
providing a patch element, bonding the patch element on the second surface of the rewiring layer, wherein the patch element is electrically connected with the rewiring layer;
forming a plastic packaging layer on the second surface of the rewiring layer, wherein the plastic packaging layer covers the conductive connecting column and the patch element;
thinning the plastic packaging layer to expose the conductive connecting column;
forming a plurality of solder bumps on one side of the plastic packaging layer, which is far away from the rewiring layer, wherein at least one solder bump is electrically connected with the conductive connecting column;
cutting the rewiring layer and the plastic packaging layer to obtain a plurality of first packaging bodies;
and providing a second packaging body, and bonding the second packaging body to the first surface of the rewiring layer of the first packaging body, wherein the second packaging body is electrically connected with the rewiring layer.
2. The method of fabricating the wafer system level three-dimensional fan-out package structure of claim 1, further comprising the steps of: and providing a carrier, and forming a release layer on the carrier, wherein the rewiring layer is formed on the release layer, and the first surface of the rewiring layer is connected with the release layer.
3. The method of claim 2, wherein the carrier and the release layer are removed to expose the first side of the redistribution layer before dicing.
4. The method of fabricating the wafer system level three-dimensional fan-out package structure of claim 1, further comprising the steps of: and forming a through hole, wherein the through hole is opened from the first surface of the rewiring layer and extends towards the direction of the second surface of the rewiring layer so as to expose the metal wiring layer.
5. The method of manufacturing the wafer system level three-dimensional fan-out package structure of claim 4, wherein: and forming the through hole by adopting a laser drilling method.
6. The method of manufacturing the wafer system level three-dimensional fan-out package structure of claim 4, wherein: and one surface of the second packaging body is provided with a conductive bump, and the conductive bump extends into the through hole to be electrically connected with the metal wiring layer.
7. The method of manufacturing a wafer system level three-dimensional fan-out package structure of claim 1, wherein: the method further comprises the steps of forming an insulating layer on one surface, away from the rewiring layer, of the plastic packaging layer and forming an under-bump metal layer on the surface of the insulating layer, wherein the solder bumps are formed on one surface, away from the plastic packaging layer, of the under-bump metal layer.
8. The method of manufacturing a wafer system level three-dimensional fan-out package structure of claim 1, wherein: the patch element includes a passive element.
9. A wafer level three-dimensional fan-out package structure, comprising:
the rewiring layer comprises a first surface and a second surface which are oppositely arranged, and the rewiring layer comprises at least one dielectric layer and at least one metal wiring layer which are stacked in the vertical direction;
a patch element bonded to the second surface of the rewiring layer and electrically connected to the rewiring layer;
the plastic packaging layer is positioned on the second surface of the rewiring layer and covers the patch element;
the conductive connecting column penetrates through the plastic packaging layer in the vertical direction and is electrically connected with the rewiring layer;
the solder bumps are distributed on one side, away from the rewiring layer, of the plastic packaging layer, and at least one solder bump is electrically connected with the conductive connecting column;
and the packaging body is jointed with the first surface of the rewiring layer and is electrically connected with the rewiring layer.
10. The wafer system-level three-dimensional fan-out package structure of claim 9, wherein: the redistribution layer is provided with a through hole, the through hole extends from the first surface opening of the redistribution layer to the second surface direction of the redistribution layer to expose the metal wiring layer, and one surface of the packaging body is provided with a conductive bump which extends into the through hole to be electrically connected with the metal wiring layer.
11. The wafer system-level three-dimensional fan-out package structure of claim 9, wherein: the plastic packaging layer is arranged on the substrate, the insulating layer is arranged on one surface of the plastic packaging layer, which deviates from the rewiring layer, of the plastic packaging layer, and the under-bump metal layer is arranged on one surface of the solder bump, which faces the plastic packaging layer, and is in contact with the insulating layer.
12. The wafer system-level three-dimensional fan-out package structure of claim 9, wherein: the patch element includes a passive element.
CN202011310588.2A 2020-11-20 2020-11-20 Wafer system level three-dimensional fan-out type packaging structure and manufacturing method thereof Pending CN112289742A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114023663A (en) * 2021-11-05 2022-02-08 华天科技（昆山）电子有限公司 Three-dimensional board-level fan-out type packaging structure and manufacturing method thereof
CN114975139A (en) * 2022-04-15 2022-08-30 盛合晶微半导体(江阴)有限公司 Passive component substrate packaging structure and chip packaging method thereof
CN114975136A (en) * 2021-10-22 2022-08-30 盛合晶微半导体(江阴)有限公司 System wafer level chip packaging method and structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114975136A (en) * 2021-10-22 2022-08-30 盛合晶微半导体(江阴)有限公司 System wafer level chip packaging method and structure
CN114023663A (en) * 2021-11-05 2022-02-08 华天科技（昆山）电子有限公司 Three-dimensional board-level fan-out type packaging structure and manufacturing method thereof
CN114975139A (en) * 2022-04-15 2022-08-30 盛合晶微半导体(江阴)有限公司 Passive component substrate packaging structure and chip packaging method thereof

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