CN213242550U

CN213242550U - Wafer system level fan-out type packaging structure

Info

Publication number: CN213242550U
Application number: CN202022718472.4U
Authority: CN
Inventors: 陈彦亨; 林正忠
Original assignee: SJ Semiconductor Jiangyin Corp
Current assignee: SJ Semiconductor Jiangyin Corp
Priority date: 2020-11-20
Filing date: 2020-11-20
Publication date: 2021-05-18
Anticipated expiration: 2030-11-20

Abstract

The utility model provides a wafer system level fan-out type packaging structure, this wafer system level fan-out type packaging structure includes: a rewiring layer including a first face and a second face disposed opposite to each other; at least one patch element bonded to the second side of the redistribution layer; at least one bare chip with bumps on the front surface, wherein the front surface of the bare chip is jointed on the second surface of the redistribution layer; a molding layer on a second side of the redistribution layer, the molding layer covering the patch element and the die. The utility model discloses a wafer system level fan-out type packaging structure is with bare chip and the same encapsulation of paster component in the plastic envelope layer to realize bare chip and paster component's interconnection and draw forth through wiring layer again, can increase fan-out function integration nature, promote single chip function and efficiency, and optimize the volume.

Description

Wafer system level fan-out type packaging structure

Technical Field

The utility model belongs to the semiconductor package field relates to a wafer system level fan-out type packaging structure.

Background

With the advent of the 5G communication and Artificial Intelligence (AI) era, the amount of data to be transmitted and processed interactively at high speed is enormous for chips applied in such related fields, which usually have huge number of pad pins (hundreds or even thousands), ultra-fine pin sizes and pitches (several microns or even smaller). On the other hand, the demands on the mobile internet and the internet of things are more and more strong, and the miniaturization and the multi-functionalization of electronic terminal products become a great trend of industrial development. How to integrate and package a plurality of different high-density chips together to form a system or subsystem with powerful function and smaller volume and power consumption becomes a great challenge in the field of advanced packaging of semiconductor chips.

At present, for multi-chip integrated packaging of such high-density chips, the industry generally adopts Through Silicon Vias (TSVs), silicon interposer (Si interposer) and other manners, so as to lead out and effectively interconnect ultra-fine pins of the chips to form a functional module or system, but the technology has higher cost, thereby greatly limiting the application range thereof.

With the continuing demand for higher functionality, better performance and higher energy efficiency, lower manufacturing costs and smaller dimensions, fan-out wafer level packaging (FOWLP) technology has become one of the most promising technologies to meet the demands of electronic devices for mobile and network applications. The fan-out packaging technology provides a good platform for realizing integrated packaging of multiple chips by adopting a mode of reconstructing wafers and rewiring RDL (remote desktop language), but the existing fan-out packaging technology has the problems of large area, high thickness and the like of a packaging body due to limited wiring precision, and various working procedures and low reliability.

In order to adapt to the development trend of multiple functions, miniaturization, portability, high speed, low power consumption and high reliability of the microelectronic packaging technology, a system-In-package (SIP) technology is used as a new heterogeneous integration technology and becomes a packaging form of more and more chips, and the system-In-package integrates various functional chips and components In one package, so that a complete function is realized. The system-in-package is a novel packaging technology and has the advantages of short development period, more functions, lower power consumption, better performance, lower cost price, smaller volume, light weight and the like.

However, with the increasing demands for package components and functions, the conventional system-in-package occupies an increasing area and thickness, which is not favorable for increasing the integration level.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a wafer level fan-out package structure for solving the problem that the volume of the system level package in the prior art is difficult to be reduced.

To achieve the above and other related objects, the present invention provides a wafer system level fan-out package structure, including:

a rewiring layer including a first face and a second face disposed opposite to each other;

at least one patch element bonded to the second side of the redistribution layer;

at least one bare chip with bumps on the front surface, wherein the front surface of the bare chip is jointed on the second surface of the redistribution layer;

a molding layer on a second side of the redistribution layer, the molding layer covering the patch element and the die.

Optionally, the redistribution layer further includes an under bump metal layer and a solder bump, the under bump metal layer is located on the first surface of the redistribution layer, and the solder bump is bonded to the under bump metal layer.

Optionally, an underfill layer is further included, the underfill layer being located in a gap between the die and the re-routing layer.

Optionally, the redistribution layer includes at least one dielectric layer and at least one metal wiring layer stacked in a vertical direction.

Optionally, the patch element comprises a passive element.

As described above, the utility model discloses a wafer system level fan-out type packaging structure is with bare chip and the same encapsulation of paster component in the plastic envelope layer to realize bare chip and paster component's interconnection and draw forth through rewiring layer, can increase fan-out function integration nature, promote single chip function and efficiency, and optimize the volume.

Drawings

Fig. 1 is a process flow diagram of a method for fabricating a wafer level fan-out package.

Fig. 2 shows a schematic view of providing a first carrier.

Fig. 3 is a schematic diagram illustrating the formation of a release layer on the first carrier.

Fig. 4 is a schematic view showing a re-wiring layer formed on the release layer.

Fig. 5 shows a schematic diagram of bonding at least one patch element to the second side of the redistribution layer.

Fig. 6 shows a schematic view of providing a die with bumps on at least one front side, and bonding the die front side to the second side of the redistribution layer 3.

FIG. 7 shows a schematic view of forming an underfill layer in the gap between the die and the re-routing layer.

Fig. 8 is a schematic diagram illustrating the formation of a molding layer on the second surface of the redistribution layer.

Fig. 9 shows a schematic view of bonding a second carrier to the molding layer in order to provide the second carrier.

Fig. 10 is a schematic diagram showing the removal of the first carrier and the release layer to expose the first side of the re-wiring layer.

Fig. 11 is a schematic diagram illustrating the formation of an under bump metallurgy layer on the first side of the re-routing layer.

Fig. 12 is a schematic diagram illustrating the formation of a solder bump on the under bump metallurgy layer.

Fig. 13 shows a schematic view of the removal of the second carrier and the adhesion layer in substantially the same way as the removal of the first carrier and the release layer.

Fig. 14 is a schematic diagram showing a plurality of chips obtained by cutting the redistribution layer and the molding layer.

Description of the element reference numerals

S1-S4

1 first carrier

2 Release layer

3 rewiring layer

301 dielectric layer

302 metal wiring layer

4 paster element

5 bare chip

6 underfill layer

7 Plastic packaging layer

8 second Carrier

9 adhesive layer

10 bump under metal layer

11 solder bump

12 blue film

13 Metal frame

14 blade

Detailed Description

The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to fig. 1 to 14. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the invention in a schematic manner, and only the components related to the invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.

The present embodiment provides a method for manufacturing a fan-out package structure of a wafer level, referring to fig. 1, which is a process flow diagram of the method, and includes the following steps:

s1: forming a rewiring layer including a first face and a second face disposed oppositely;

s2: providing at least one patch element, and bonding the patch element on the second surface of the rewiring layer;

s3: providing a bare chip with bumps on at least one front surface, and bonding the front surface of the bare chip to the second surface of the redistribution layer;

s4: forming a molding layer on a second side of the redistribution layer, the molding layer covering the patch element and the die.

Referring to fig. 2 to 4, step S1 is executed: and forming a rewiring layer which comprises a first surface and a second surface which are oppositely arranged.

Specifically, as shown in fig. 2, a first carrier 1 is provided. The first carrier 1 is used for preventing the layer structure from cracking, warping, breaking, etc. during the packaging process, and the shape of the first carrier 1 may be wafer-shaped, panel-shaped, and any other desired shape, including but not limited to any one of glass, metal, semiconductor, polymer, and ceramic. In this embodiment, the first carrier 1 is made of glass, which is low in cost, and is easy to form a release layer on the surface thereof, and can reduce the difficulty of the subsequent stripping process.

As shown in fig. 3, a release layer 2 is formed on the first carrier. The release layer can be made of materials such as adhesive tapes or polymers, and can be cured by ultraviolet light or heat.

As shown in fig. 4, a rewiring layer 3 is formed on the release layer, and a first surface of the rewiring layer 3 is connected to the release layer 2.

As an example, the redistribution layer 3 includes at least one dielectric layer 301 and at least one metal wiring layer 302 stacked in a vertical direction.

As an example, the fabrication of the rewiring layer 3 comprises the following steps:

(1) and forming a first dielectric layer on the surface of the release layer by adopting a chemical vapor deposition process, a physical vapor deposition process or other suitable processes, wherein the material of the first dielectric layer comprises but is not limited to one or the combination of more than two of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass. In this embodiment, the first dielectric layer is Polyimide (PI), so as to further reduce the process difficulty and the process cost.

(2) And forming a first metal layer on the surface of the first medium layer by adopting sputtering, electroplating, chemical plating or other suitable processes, and etching the first metal layer to form a patterned first metal wiring layer. The material of the first metal wiring layer comprises one or the combination of more than two of copper, aluminum, nickel, gold, silver and titanium.

(3) And forming a second dielectric layer on the surface of the patterned first metal wiring layer by adopting a chemical vapor deposition process, a physical vapor deposition process or other suitable processes, and etching the second dielectric layer to form the second dielectric layer with the patterned through hole. The material of the second dielectric layer includes but is not limited to one or a combination of more than two of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass. In this embodiment, the second dielectric layer is made of PI (polyimide), so as to further reduce the process difficulty and the process cost.

(4) And filling the conductive plugs in the patterned through holes by adopting sputtering, electroplating, chemical plating or other suitable processes, forming a second metal layer on the surface of the second dielectric layer by adopting sputtering, electroplating, chemical plating or other suitable processes, and etching the metal layer to form a patterned second metal wiring layer. The second metal wiring layer is made of one or a combination of more than two of copper, aluminum, nickel, gold, silver and titanium.

Next, the above steps (3) - (4) may be repeated one or more times as required to form a redistribution layer with a multi-layer stacked structure, so as to implement different routing functions, for example, in this embodiment, the redistribution layer 3 further includes a patterned third dielectric layer and a patterned third metal routing layer.

Referring to fig. 5, step S2 is executed: at least one patch element 4 is provided, and the patch element 4 is bonded to the second surface of the redistribution layer 3.

As an example, the patch element 4 includes a passive element, such as a resistor, an inductor, a capacitor, etc., and the patch element may be bonded to the second surface of the redistribution layer 3 by a surface mount process to achieve electrical connection with the redistribution layer 3.

Referring to fig. 6, step S3 is executed: providing a bare chip 5 with bumps on at least one front surface, and bonding the bare chip 5 on the second surface of the redistribution layer 3 on the front surface.

By way of example, a Bumped die (Bumped die) may be bonded to the second side of the redistribution layer 3 by a bond-on-trace method, the die 5 may have a substrate or more circuits therein, the type and number of the dies may be adjusted as desired, and the bumps of the dies may be made of copper, nickel, tin, silver, or the like.

As an example, as shown in fig. 7, an underfill layer 6 may be further formed in the gap between the die 5 and the redistribution layer 3 by a dispensing process or other suitable processes, and the underfill layer 6 may provide protection for the connection between the die 5 and the redistribution layer 3 to prevent corrosion or connection damage, and may improve the adhesion between the die 5 and the redistribution layer 3 to improve the mechanical strength.

Referring to fig. 8, step S4 is executed: a molding layer 7 is formed on the second side of the redistribution layer, the molding layer 7 covering the patch element 4 and the die 5.

By way of example, the molding layer 7 may be formed by any one of compression molding, transfer molding, liquid sealing, vacuum lamination, and spin coating, and the material of the molding layer 7 may be a curable material, such as a polymer-based material, a resin-based material, a polyamide, an epoxy resin, and any combination thereof.

As an example, as shown in fig. 9, a second carrier 8 is further provided, and the second carrier 8 is bonded to the molding layer 7.

As an example, the second carrier 8 may be joined to the molding layer 7 by an adhesive layer or other suitable adhesive layer 9. The material of the second carrier 8 includes, but is not limited to, any one of glass, metal, semiconductor, polymer and ceramic.

As an example, as shown in fig. 10, the first carrier 1 and the release layer 2 are further removed to expose the first side of the rewiring layer 3.

Specifically, the viscosity of the release layer 2 is reduced by a corresponding method according to the type of the release layer 2, and the first carrier 1 and the release layer 2 are peeled off. For example, when the release layer 2 employs a photothermal conversion material, the photothermal conversion layer may be irradiated with laser light to separate the photothermal conversion layer from the rewiring layer 3 and the first support 1.

As an example, as shown in fig. 11, an under bump metallurgy layer 10 is further formed on the first surface of the rewiring layer 3.

In this embodiment, a window may be formed in the first dielectric layer by using laser, the window exposes the first metal wiring layer, and then the under bump metal layer 10 is formed in and near the window, where the material of the under bump metal layer 10 includes, but is not limited to, copper, nickel, tin and silver, and the like.

As an example, as shown in fig. 12, a solder bump 11 is further formed on the under bump metal layer 10. The solder bump 11 may be composed of a metal pillar, a solder bump, or may be a solder ball.

As an example, as shown in fig. 13, the second carrier 8 and the adhesive layer 9 are removed in substantially the same way as the first carrier 1 and the release layer 2 are removed.

As an example, as shown in fig. 14, the redistribution layer 3 and the molding layer 7 are further diced to obtain a plurality of chips. For example, a blue film 12 may be attached to the back of the molding layer 7, fixed to a metal frame 13, and then cut by a blade 14.

To this end, a wafer system fan-out package structure is manufactured, as shown in fig. 14, the wafer system fan-out package structure includes a redistribution layer 3, at least one patch element 4, at least one bare chip 5 having a bump on a front surface thereof, and a molding layer 7, the redistribution layer 3 includes a first surface and a second surface that are arranged opposite to each other, the patch element 4 is bonded to the second surface of the redistribution layer 3, the bare chip 5 is bonded to the second surface of the redistribution layer 3 on the front surface thereof, and the molding layer 7 is located on the second surface of the redistribution layer 3 and covers the patch element 4 and the bare chip 5. In this embodiment, the package structure further includes an under bump metal layer 10 and a solder bump 11, where the under bump metal layer 10 is located on the first surface of the redistribution layer 3, and the solder bump 11 is bonded to the under bump metal layer 10. The package structure further includes an underfill layer 6, the underfill layer 6 being located in a gap between the die 5 and the redistribution layer 3. The rewiring layer 3 includes at least one dielectric layer 301 and at least one metal wiring layer 302 stacked in a vertical direction. The package structure the patch element 4 comprises passive components such as resistors, inductors, capacitors, etc.

To sum up, the utility model discloses a wafer system level fan-out type packaging structure is with bare chip and the same encapsulation of paster component in the plastic envelope layer to realize bare chip and paster component's interconnection and draw forth through rewiring layer, can increase fan-out function integration nature, promote single chip function and efficiency, and optimize the volume. Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A wafer level fan-out package structure, comprising:

2. The wafer system level fan-out package structure of claim 1, wherein: the rewiring layer is arranged on the first surface of the rewiring layer, and the lower bump metal layer is connected to the lower bump metal layer through the solder bump.

3. The wafer system level fan-out package structure of claim 1, wherein: also included is an underfill layer located in a gap between the die and the re-routing layer.

4. The wafer system level fan-out package structure of claim 1, wherein: the rewiring layer includes at least one dielectric layer and at least one metal wiring layer stacked in a vertical direction.

5. The wafer system level fan-out package structure of claim 1, wherein: the patch element includes a passive element.