CN212392240U - Fan-out type packaging structure - Google Patents
Fan-out type packaging structure Download PDFInfo
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- CN212392240U CN212392240U CN202022013581.6U CN202022013581U CN212392240U CN 212392240 U CN212392240 U CN 212392240U CN 202022013581 U CN202022013581 U CN 202022013581U CN 212392240 U CN212392240 U CN 212392240U
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- redistribution
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The utility model provides a fan-out type packaging structure, fan-out type packaging structure include first rewiring layer, second rewiring layer, metal connecting post, semiconductor chip, first filling layer, first encapsulated layer, pile up the chip packaging body, passive component, second filling layer, second encapsulated layer and metal convex block. The utility model can integrate a plurality of chips with different functions into one packaging structure, thereby improving the integration of the fan-out type packaging structure; through the first rewiring layer, the second rewiring layer and the metal connecting column, three-dimensional vertical stacking packaging is achieved, the integration level of a packaging structure can be effectively improved, the conducting path can be effectively shortened, power consumption is reduced, the transmission speed is improved, and data processing capacity is increased.
Description
Technical Field
The utility model relates to a semiconductor package technical field especially relates to a fan-out type packaging structure.
Background
Lower cost, more reliable, faster, and higher density circuits are sought after goals for integrated circuit packaging. With the arrival of the 5G communication and artificial intelligence era, the data volume to be transmitted and processed by high-speed interaction of chips applied to the related fields is large, the requirements on the mobile internet and the internet of things are more and more strong, and the miniaturization and the multi-functionalization of electronic terminal products become a great trend of industrial development. How to integrate and package different kinds of high-density chips together to form a system with powerful functions and small volume power consumption has become a great challenge in the field of advanced packaging of semiconductor chips.
Among them, the fan-out wafer level package (FOWLP) has become one of the more advanced fan-out packaging methods due to its more input/output ports (I/O) and better integration flexibility. However, in the conventional fan-out package technology, the area of the package is large and the thickness of the package is high due to limited wiring precision, and the problems of multiple processes, low reliability and the like exist.
Therefore, it is necessary to provide a new fan-out package structure.
SUMMERY OF THE UTILITY MODEL
In view of the above shortcomings in the prior art, an object of the present invention is to provide a fan-out package structure for solving the problems in the prior art that the package size is difficult to shrink and the package integration level is low.
To achieve the above and other related objects, the present invention provides a fan-out package structure, comprising:
a first redistribution layer including opposing first and second faces;
a second rewiring layer including a first surface and a second surface opposite to each other;
a metal connection stud located between the second surface of the first redistribution layer and the first surface of the second redistribution layer and electrically connected to the first redistribution layer and the second redistribution layer;
a semiconductor chip located between the second surface of the first re-wiring layer and the first surface of the second re-wiring layer, wherein the front surface of the semiconductor chip is electrically connected with the first re-wiring layer through a chip pad, and the back surface of the semiconductor chip is far away from the first re-wiring layer;
a first filling layer located between the semiconductor chip and the first re-wiring layer and filling a gap between the semiconductor chip and the first re-wiring layer;
the first packaging layer is positioned between the second surface of the first rewiring layer and the first surface of the second rewiring layer and covers the first rewiring layer, the metal connecting column and the semiconductor chip;
the stacked chip packaging body and the passive element are positioned on the second surface of the second rewiring layer and are electrically connected with the second rewiring layer;
a second filling layer located between the stacked chip package and the second redistribution layer and filling a gap between the stacked chip package and the second redistribution layer;
the second packaging layer covers the second rewiring layer, the stacked chip packaging body and the passive element;
and the metal bump is positioned on the first surface of the first redistribution layer and is electrically connected with the first redistribution layer.
Optionally, the stacked chip package includes an ePoP memory.
Optionally, the passive element includes one or a combination of a resistor, a capacitor, and an inductor.
Optionally, a thickness of the first re-wiring layer is greater than a thickness of the second re-wiring layer.
Optionally, the first encapsulation layer includes one of an epoxy layer, a polyimide layer, and a silicone layer; the second packaging layer comprises one of an epoxy resin layer, a polyimide layer and a silica gel layer.
Optionally, the first filling layer includes one of an epoxy layer, a polyimide layer, and a silicone layer; the second filling layer comprises one of an epoxy resin layer, a polyimide layer and a silica gel layer.
Optionally, the metal bump includes one of a copper metal bump, a nickel metal bump, a tin metal bump, and a silver metal bump.
As described above, the fan-out package structure of the present invention can integrate a plurality of chips with different functions into one package structure, thereby improving the integration of the fan-out package structure; through the first rewiring layer, the second rewiring layer and the metal connecting column, three-dimensional vertical stacking packaging is achieved, the integration level of a packaging structure can be effectively improved, the conducting path can be effectively shortened, power consumption is reduced, the transmission speed is improved, and data processing capacity is increased.
Drawings
Fig. 1 shows a flow chart of a manufacturing process of the fan-out package structure of the present invention.
Fig. 2 to fig. 21 show the schematic structural diagrams of the steps in the manufacturing process of the middle fan-out package structure of the present invention, wherein fig. 21 shows the schematic structural diagram of the middle fan-out package structure of the present invention.
Description of the element reference numerals
100 support substrate
200 separating layer
300 first rewiring layer
301 dielectric layer
302 metal wiring layer
400 UBM layer
500 metal connecting column
600 semiconductor chip
700 first fill layer
800 first encapsulation layer
900 second rewiring layer
110 temporary substrate
120 metal bump
130 carrier body
140 stacked chip package
150 passive element
160 second filling layer
170 second encapsulation layer
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structure are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, amount and ratio of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.
As shown in fig. 1, the present embodiment provides a fan-out package method, which can integrate a plurality of chips with different functions into one package structure, thereby improving the integrity of the fan-out package structure; through the first rewiring layer, the second rewiring layer and the metal connecting column, three-dimensional vertical stacking packaging is achieved, the integration level of a packaging structure can be effectively improved, the conducting path can be effectively shortened, power consumption is reduced, the transmission speed is improved, and data processing capacity is increased.
First, referring to fig. 2, a supporting substrate 100 is provided, and a separation layer 200 is formed on the supporting substrate 100.
Specifically, the support substrate 100 may include one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate. In the present embodiment, the supporting substrate 100 is preferably a glass substrate which has low cost, is easy to form the separation layer 200 on the surface thereof, and can reduce the difficulty of the subsequent peeling process, but is not limited thereto. The separation layer 200 may include one of an adhesive tape and a polymer layer, and when the polymer layer is used, a polymer may be applied to the surface of the support substrate 100 by a spin coating process and then cured by a uv curing or thermal curing process. In this embodiment, the separation layer 200 is an LTHC light-to-heat conversion layer, so that the LTHC light-to-heat conversion layer may be heated based on laser and other methods in the subsequent steps, so that the supporting substrate 100 is separated from the LTHC light-to-heat conversion layer, thereby reducing the difficulty of the stripping process and reducing the damage.
Next, referring to fig. 3 to 4, a first redistribution layer 300 is formed on the separation layer 200, where the first redistribution layer 300 includes a first surface contacting the separation layer 200 and an opposite second surface.
Specifically, in this embodiment, a dielectric layer 301 is formed on the surface of the separation layer 200, and then a patterned metal wiring layer 302 is formed, and the steps of forming the dielectric layer 301 and the metal wiring layer 302 may be repeated according to the process requirements, so as to increase the conductive paths and reduce the thickness of the first redistribution layer 300, and the specific number of layers of the first redistribution layer 300 may be selected according to the requirements. The material of the dielectric layer 301 may include one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass; the material of the metal wiring layer 302 may include one of copper, aluminum, nickel, gold, silver, and titanium.
As an example, after the first re-wiring layer 300 is formed, a step of forming a UBM layer 400 on the second side of the first re-wiring layer 300 is further included.
Specifically, the bonding of the subsequent semiconductor chip 600 to the first re-wiring layer 300 may be enhanced by the UBM layer 400, and the material, the preparation method, and the like of the UBM layer 400 are not limited herein.
Next, referring to fig. 5, a metal connection post 500 is formed on a second surface of the first redistribution layer 300, and the metal connection post 500 is electrically connected to the first redistribution layer 300.
Specifically, the metal connection column 500 may be formed by a wire bonding process, wherein the wire bonding process may include one of a thermocompression bonding process, an ultrasonic bonding process, and a thermocompression ultrasonic bonding process; the material of the metal connection pillar 500 may include one or a combination of Au, Ag, Cu, and Al, and the selection of the forming method and the material of the metal connection pillar 500 is not limited herein.
Next, referring to fig. 6, a semiconductor chip 600 is provided, the semiconductor chip 600 is located on the second surface of the first re-wiring layer 300, the front surface of the semiconductor chip 600 is electrically connected to the first re-wiring layer 300 through a chip pad, and the back surface of the semiconductor chip 600 is away from the second surface of the first re-wiring layer 300.
As an example, the height of the metal connection stud 500 is greater than the height of the semiconductor chip 600.
Specifically, when the height of the metal connection pillar 500 is greater than the height of the semiconductor chip 600, the damage to the semiconductor chip 600 can be reduced in the subsequent thinning process. The height of the metal connection posts 500 and the semiconductor chip 600 can be selected according to the type of the semiconductor chip 600, and is not limited herein.
Next, referring to fig. 7, a gap between the semiconductor chip 600 and the first re-wiring layer 300 is filled with a first filling layer 700.
Specifically, the first filling layer 700 may include one of an epoxy layer, a polyimide layer, and a silicone layer, so as to fill the gap with the first filling layer 700 having insulation properties, so as to enhance the bonding effect between the semiconductor chip 600 and the first redistribution layer 300, and form a protective layer, thereby preventing moisture, oxygen, and the like from acting on the semiconductor chip 600 and the first redistribution layer 300. The material of the first filling layer 700 is not limited herein.
Next, referring to fig. 8 to 9, the first redistribution layer 300, the metal connection pillar 500 and the semiconductor chip 600 are packaged by a first packaging layer 800, and the metal connection pillar 500 is exposed by the first packaging layer 800.
Specifically, the method for forming the first encapsulation layer 800 may include one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, and spin coating, and the material of the first encapsulation layer 800 may include one of polyimide, silicone, and epoxy. After the first encapsulation layer 800 is formed, a grinding or polishing method may be further included to act on the top surface of the first encapsulation layer 800 to provide a flat top surface of the first encapsulation layer 800.
Next, referring to fig. 10, a second redistribution layer 900 is formed on the first encapsulation layer 800, the second redistribution layer 900 includes a first surface contacting the first encapsulation layer 800 and an opposite second surface, and the second redistribution layer 900 is electrically connected to the metal connection pillar 500.
As an example, the thickness of the first re-wiring layer 300 is greater than the thickness of the second re-wiring layer 900.
Specifically, the material, structure and preparation of the second redistribution layer 900 may refer to the first redistribution layer 300, and details are not repeated here, in this embodiment, since the first redistribution layer 300 has more conductive channels, the thickness of the first redistribution layer 300 is greater than that of the second redistribution layer 900, and specific dimensions of the first redistribution layer 300 and the second redistribution layer 900 are not limited here.
Next, referring to fig. 11, a temporary base 110 is provided, and the temporary base 110 is bonded to the second surface of the second redistribution layer 900 to provide a temporary support function through the temporary base 110, so as to strip the supporting substrate 100 for subsequent processes. The material, bonding method, etc. of the temporary substrate 110 can be referred to the support substrate 100, and are not limited herein.
Next, referring to fig. 12, the supporting substrate 100 is peeled based on the separation layer 200 to expose the first face of the first re-wiring layer 300.
Specifically, in this embodiment, since the separation layer 200 is the LTHC photothermal conversion layer, the supporting substrates 100 may be separated from each other by heating with laser, but the method of separating the supporting substrates 100 is not limited thereto, and may be selected according to the materials of the supporting substrates 100 and the separation layer 200.
Next, referring to fig. 13, the first re-wiring layer 300 is laser etched to expose the metal wiring layer 302 in the first re-wiring layer 300.
Next, referring to fig. 14, a metal bump 120 is formed, and the metal bump 120 is electrically connected to the metal wiring layer 302 exposed in the first redistribution layer 300, wherein the metal bump 120 may include one of a copper metal bump, a nickel metal bump, a tin metal bump, and a silver metal bump, and the specific kind may be selected as required.
Next, referring to fig. 15 to 16, the carrier 130 is provided, and the temporary substrate 110 is removed to expose the second side of the second redistribution layer 900.
Next, referring to fig. 17 to 18, a stacked chip package 140 and a passive device 150 are provided, the stacked chip package 140 and the passive device 150 are located on a second surface of the second redistribution layer 900, and both the stacked chip package 140 and the passive device 150 are electrically connected to the second redistribution layer 900.
As an example, the stacked chip package 140 includes an ePoP memory.
As an example, the passive element 150 includes one or a combination of a resistor, a capacitor, and an inductor.
Specifically, in the present embodiment, the stacked chip package 140 is an ePoP memory, but is not limited thereto, and other packages may be adopted according to the need, and similarly, the passive component 150 may also be disposed according to the need, and is not limited herein.
Next, referring to fig. 19, a second filling layer 160 is used to fill a gap between the stacked chip package 140 and the second re-wiring layer 900.
Specifically, the second filling layer 160 may include one of an epoxy layer, a polyimide layer, and a silicone layer, and the specific function of the second filling layer 160 may refer to the first filling layer 700, which is not described herein again.
Next, referring to fig. 20, the second redistribution layer 900, the stacked chip package 140 and the passive component 150 are packaged by using a second packaging layer 170.
Specifically, the second encapsulation layer 170 includes one of an epoxy layer, a polyimide layer, and a silicone layer, and the specific preparation method can refer to the first encapsulation layer 800, which is not described herein again.
Finally, referring to fig. 21, a dicing process is performed to form a fan-out package structure.
Referring to fig. 21, the present embodiment further provides a fan-out package structure, which can be prepared by the above-mentioned preparation method, but is not limited thereto. In this embodiment, the fan-out package structure is prepared by the above preparation method, and therefore, details regarding the selection of the preparation method, the material, and the like of the fan-out package structure are not described herein.
Specifically, the fan-out package structure includes a first redistribution layer 300, a second redistribution layer 900, a metal connection pillar 500, a semiconductor chip 600, a first filling layer 700, a first packaging layer 800, a stacked chip package body 140, a passive component 150, a second filling layer 160, a second packaging layer 170, and a metal bump 120. Wherein the first redistribution layer 300 includes a first side and a second side opposite to each other; the second redistribution layer 900 includes a first side and a second side opposite to each other; the metal connection stud 500 is located between the second side of the first redistribution layer 300 and the first side of the second redistribution layer 900, and is electrically connected to the first redistribution layer 300 and the second redistribution layer 900; the semiconductor chip 600 is located between the second surface of the first redistribution layer 300 and the first surface of the second redistribution layer 900, the front surface of the semiconductor chip 600 is electrically connected to the first redistribution layer 300 through a chip pad, and the back surface of the semiconductor chip 600 is far away from the first redistribution layer 300; the first filling layer 700 is located between the semiconductor chip 600 and the first re-wiring layer 300, and fills a gap between the semiconductor chip 600 and the first re-wiring layer 300; the first encapsulation layer 800 is located between the second side of the first redistribution layer 300 and the first side of the second redistribution layer 900, and covers the first redistribution layer 300, the metal connection stud 500 and the semiconductor chip 600; the stacked chip package 140 and the passive component 150 are located on a second surface of the second redistribution layer 900 and electrically connected to the second redistribution layer 900; the second filling layer 160 is located between the stacked chip package 140 and the second redistribution layer 900, and fills a gap between the stacked chip package 140 and the second redistribution layer 900; the second encapsulant layer 170 covers the second redistribution layer 900, the stacked chip package 140 and the passive component 150; the metal bump 120 is located on a first side of the first re-wiring layer 300 and electrically connected to the first re-wiring layer 300.
As an example, the stacked chip package 140 includes an ePoP memory.
As an example, the passive element 150 includes one or a combination of a resistor, a capacitor, and an inductor.
As an example, the thickness of the first re-wiring layer 300 is greater than the thickness of the second re-wiring layer 900.
As an example, the first encapsulation layer 800 includes one of an epoxy layer, a polyimide layer, and a silicone layer; the second encapsulation layer 170 includes one of an epoxy layer, a polyimide layer, and a silicone layer; the first filling layer 700 includes one of an epoxy layer, a polyimide layer, and a silicone layer; the second filling layer 160 includes one of an epoxy layer, a polyimide layer, and a silicone layer.
As an example, the metal bump 120 includes one of a copper metal bump, a nickel metal bump, a tin metal bump, and a silver metal bump.
In summary, the fan-out package structure of the present invention can integrate a plurality of chips with different functions into one package structure, thereby improving the integration of the fan-out package structure; through the first rewiring layer, the second rewiring layer and the metal connecting column, three-dimensional vertical stacking packaging is achieved, the integration level of a packaging structure can be effectively improved, the conducting path can be effectively shortened, power consumption is reduced, the transmission speed is improved, and data processing capacity is increased.
The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (7)
1. A fan-out package structure, comprising:
a first redistribution layer including opposing first and second faces;
a second rewiring layer including a first surface and a second surface opposite to each other;
a metal connection stud located between the second surface of the first redistribution layer and the first surface of the second redistribution layer and electrically connected to the first redistribution layer and the second redistribution layer;
a semiconductor chip located between the second surface of the first re-wiring layer and the first surface of the second re-wiring layer, wherein the front surface of the semiconductor chip is electrically connected with the first re-wiring layer through a chip pad, and the back surface of the semiconductor chip is far away from the first re-wiring layer;
a first filling layer located between the semiconductor chip and the first re-wiring layer and filling a gap between the semiconductor chip and the first re-wiring layer;
the first packaging layer is positioned between the second surface of the first rewiring layer and the first surface of the second rewiring layer and covers the first rewiring layer, the metal connecting column and the semiconductor chip;
the stacked chip packaging body and the passive element are positioned on the second surface of the second rewiring layer and are electrically connected with the second rewiring layer;
a second filling layer located between the stacked chip package and the second redistribution layer and filling a gap between the stacked chip package and the second redistribution layer;
the second packaging layer covers the second rewiring layer, the stacked chip packaging body and the passive element;
and the metal bump is positioned on the first surface of the first redistribution layer and is electrically connected with the first redistribution layer.
2. The fan-out package structure of claim 1, wherein: the stacked chip package includes an ePoP memory.
3. The fan-out package structure of claim 1, wherein: the passive element comprises one or a combination of a resistor, a capacitor and an inductor.
4. The fan-out package structure of claim 1, wherein: the thickness of the first re-wiring layer is greater than the thickness of the second re-wiring layer.
5. The fan-out package structure of claim 1, wherein: the first packaging layer comprises one of an epoxy resin layer, a polyimide layer and a silica gel layer; the second packaging layer comprises one of an epoxy resin layer, a polyimide layer and a silica gel layer.
6. The fan-out package structure of claim 1, wherein: the first filling layer comprises one of an epoxy resin layer, a polyimide layer and a silica gel layer; the second filling layer comprises one of an epoxy resin layer, a polyimide layer and a silica gel layer.
7. The fan-out package structure of claim 1, wherein: the metal bump comprises one of a copper metal bump, a nickel metal bump, a tin metal bump and a silver metal bump.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022013581.6U CN212392240U (en) | 2020-09-15 | 2020-09-15 | Fan-out type packaging structure |
| US17/476,340 US11756871B2 (en) | 2020-09-15 | 2021-09-15 | Fan-out packaging structure and method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022013581.6U CN212392240U (en) | 2020-09-15 | 2020-09-15 | Fan-out type packaging structure |
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| CN212392240U true CN212392240U (en) | 2021-01-22 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114093772A (en) * | 2021-11-04 | 2022-02-25 | 盛合晶微半导体(江阴)有限公司 | Fan-out type packaging structure and packaging method |
| CN116960108A (en) * | 2023-09-21 | 2023-10-27 | 江苏展芯半导体技术有限公司 | Chip packaging structure and method |
-
2020
- 2020-09-15 CN CN202022013581.6U patent/CN212392240U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114093772A (en) * | 2021-11-04 | 2022-02-25 | 盛合晶微半导体(江阴)有限公司 | Fan-out type packaging structure and packaging method |
| CN116960108A (en) * | 2023-09-21 | 2023-10-27 | 江苏展芯半导体技术有限公司 | Chip packaging structure and method |
| CN116960108B (en) * | 2023-09-21 | 2023-12-08 | 江苏展芯半导体技术有限公司 | Chip packaging structure and method |
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