CN209843707U - Packaging structure of fan-out type fingerprint identification chip - Google Patents
Packaging structure of fan-out type fingerprint identification chip Download PDFInfo
- Publication number
- CN209843707U CN209843707U CN201920869199.XU CN201920869199U CN209843707U CN 209843707 U CN209843707 U CN 209843707U CN 201920869199 U CN201920869199 U CN 201920869199U CN 209843707 U CN209843707 U CN 209843707U
- Authority
- CN
- China
- Prior art keywords
- chip
- fingerprint
- layer
- fan
- packaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Wire Bonding (AREA)
Abstract
The utility model provides a packaging structure of fan-out type fingerprint identification chip, the structure includes: rewiring layers; the fingerprint acquisition chip is connected to the first surface of the rewiring layer, and an electrode of the fingerprint acquisition chip is connected with the rewiring layer; the packaging layer coats the side face of the fingerprint acquisition chip, and the top face of the fingerprint acquisition chip is exposed out of the packaging layer; the fingerprint processing chip is connected to the second surface of the rewiring layer and is connected with the fingerprint acquisition chip through the rewiring layer; and the metal bump is formed on the second surface of the rewiring layer so as to realize the electrical leading-out of the fingerprint processing chip through the rewiring layer. The utility model discloses a fan-out type encapsulation fingerprint identification chip can handle chip integration in same packaging structure with fingerprint collection chip and fingerprint, and fingerprint collection chip and fingerprint handle the chip and set up for perpendicular, compares in the encapsulation of other fingerprint identification chips that have now, has with low costs, thickness is little, the advantage that the yield is high.
Description
Technical Field
The utility model belongs to the semiconductor package field especially relates to a packaging structure and packaging method of fan-out type fingerprint identification chip.
Background
With the increasing functionality, performance and integration level of integrated circuits, and the emergence of new types of integrated circuits, packaging technology plays an increasingly important role in integrated circuit products, and accounts for an increasing proportion of the value of the entire electronic system. Meanwhile, as the feature size of the integrated circuit reaches the nanometer level, the transistor is developed to a higher density and a higher clock frequency, and the package is also developed to a higher density.
Because the fan-out wafer level package (fowlp) technology has the advantages of miniaturization, low cost, high integration, better performance, and higher energy efficiency, the fan-out wafer level package (fowlp) technology has become an important packaging method for high-demand electronic devices such as mobile/wireless networks, and is one of the most promising packaging technologies currently.
Fingerprint identification technology is the most mature and cheap biometric identification technology at present. At present, the technology of fingerprint identification is most widely applied, the figure of the fingerprint identification technology can be seen in an access control and attendance system, and more fingerprint identification applications are available in the market: such as notebook computer, mobile phone, automobile, bank payment can all apply the technology of fingerprint identification.
The prior art packaging method of fingerprint identification chip is shown in fig. 1a to 1 c:
first, as shown in fig. 1a, a deep groove is formed in a fingerprint identification chip 101, the deep groove is bonded to an FPC board 102, and then a metal wire 103 is formed through a wire bonding process to electrically connect the fingerprint identification chip 101 and the FP C board 102, wherein the FPC is a Flexible Printed Circuit (hereinafter referred to as a "Flexible Printed Circuit") for short, and has the characteristics of high wiring density, light weight, and thin thickness.
Second, as shown in fig. 1b, a frame 104 is manufactured;
and thirdly, as shown in fig. 1c, covering a sapphire cover plate 105 on the fingerprint identification chip to finish packaging.
This method has the following disadvantages: the packaging structure comprises a three-layer structure of the FPC board, the fingerprint identification chip and the sapphire cover plate, the packaging thickness is thick, the metal connecting wires are easy to break due to pulling of the FPC board and the like, and the overall yield is low.
Another method for packaging a fingerprint identification chip is shown in fig. 2a to 2 c:
first, as shown in fig. 2a, a through-hole electrode 106 is formed in the fingerprint recognition chip 101 by a through-silicon via TSV technique;
secondly, as shown in fig. 2b, the sapphire cover plate 105, the fingerprint identification chip 101 and the FPC board 102 are laminated together, and a metal connecting wire 103 is manufactured through a wire bonding process to connect the fingerprint identification chip 101 and the FPC board 102;
third, as shown in FIG. 2c, the frame 104 is fabricated.
This method has the following disadvantages: the fingerprint identification chip is packaged by a sapphire cover plate, the thickness is thick, the cost of a silicon perforation process is high, metal connecting wires are easy to break due to pulling of an FPC (flexible printed circuit) soft board and the like, the thickness of the fingerprint identification chip is thin, the cracking phenomenon is easy to occur, and the overall yield is low.
Based on the above, it is necessary to provide a fingerprint identification chip package structure and a fingerprint identification chip package method with low cost, low thickness and high package yield.
SUMMERY OF THE UTILITY MODEL
In view of the above disadvantages of the prior art, an object of the present invention is to provide a package structure and a package method for a fan-out type fingerprint identification chip, which are used to solve the problems of the prior art that the thickness of the fingerprint identification package is large and the cost of the package is high.
To achieve the above and other related objects, the present invention provides a package structure of fan-out fingerprint identification chip, the package structure includes: a rewiring layer including a first side and an opposing second side; the fingerprint acquisition chip is jointed with the first surface of the rewiring layer, and an electrode of the fingerprint acquisition chip is connected with the rewiring layer; the packaging layer coats the side face of the fingerprint acquisition chip, and the top face of the fingerprint acquisition chip is exposed out of the packaging layer; the fingerprint processing chip is jointed with the second surface of the rewiring layer and is connected with the fingerprint acquisition chip through the rewiring layer; and the metal bump is formed on the second surface of the rewiring layer so as to realize the electrical leading-out of the fingerprint processing chip through the rewiring layer.
Optionally, the fingerprint acquisition chip and the fingerprint processing chip are arranged in a manner of overlapping in the vertical direction.
Optionally, a gap is formed between the fingerprint processing chip and the rewiring layer, and a protective layer is formed in the gap and completely fills the gap.
Optionally, the protective layer is selected from epoxy resin.
Optionally, the encapsulation layer includes one of polyimide, silicone, and epoxy.
Optionally, the metal bump comprises one of a tin solder, a silver solder, and a gold-tin alloy solder.
The utility model also provides a packaging method of fan-out type fingerprint identification chip, including the step: 1) providing a supporting substrate, and forming a separation layer on the supporting substrate; 2) providing a fingerprint acquisition chip, fixing the fingerprint acquisition chip on the separation layer, wherein an electrode of the fingerprint acquisition chip faces the separation layer; 3) packaging the fingerprint acquisition chip by using a packaging layer, wherein the top surface of the fingerprint acquisition chip is exposed out of the packaging layer; 4) peeling the fingerprint acquisition chip and the supporting substrate based on the separation layer, and exposing the packaging layer and the electrodes of the fingerprint acquisition chip; 5) manufacturing a rewiring layer on the packaging layer and the fingerprint acquisition chip, wherein the first surface of the rewiring layer is connected with an electrode of the fingerprint acquisition chip; 6) providing a fingerprint processing chip, connecting the fingerprint processing chip to the second surface of the rewiring layer, and connecting the fingerprint processing chip with the fingerprint acquisition chip through the rewiring layer; 7) and forming a metal bump on the second surface of the rewiring layer so as to realize the electrical leading-out of the fingerprint processing chip through the rewiring layer.
Optionally, the fingerprint acquisition chip and the fingerprint processing chip are arranged in a manner of overlapping in the vertical direction.
Optionally, the support base comprises one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate.
Optionally, the separation layer includes a light-to-heat conversion layer, and step 4) irradiates the light-to-heat conversion layer with laser light to separate the light-to-heat conversion layer from the encapsulation layer and the supporting substrate, thereby peeling the encapsulation layer and the supporting substrate.
Optionally, in step 6), after the fingerprint processing chip is mounted on the rewiring layer through the metal solder joint, a gap is formed between the fingerprint processing chip and the rewiring layer, and step 6) further includes a step of forming a protective layer in the gap, where the protective layer completely fills the gap.
Optionally, the protective layer is made of epoxy resin, and is formed in a gap between the fingerprint processing chip and the rewiring layer in a dispensing or molding manner.
Optionally, the method for packaging the fingerprint processing chip with the packaging layer includes one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination and spin coating, and the packaging layer includes one of polyimide, silicone and epoxy resin.
Optionally, the metal bump comprises one of a tin solder, a silver solder, and a gold-tin alloy solder.
As described above, the utility model discloses a packaging structure and packaging method of fan-out type fingerprint identification chip has following beneficial effect:
1) the utility model discloses a Fan-out type encapsulation (Fan out) fingerprint identification chip can be with fingerprint collection chip and fingerprint processing chip integration in same packaging structure, and fingerprint collection chip and fingerprint processing chip are perpendicular setting, compare in the encapsulation of current other fingerprint identification chips, have with low costs, thickness is little, the advantage that the yield is high.
2) The utility model discloses do not need the routing technology simultaneously, also need not costly silicon perforation Technology (TSV), and can realize the encapsulation of fingerprint identification chip, greatly reduced the technology degree of difficulty and cost.
3) The utility model discloses a Fan-out encapsulation (Fan out) technology, the electricity of chip is drawn forth and is not needed traditional FPC board, can reduce the thickness of encapsulation and the stability of structure is drawn forth to the electrical property, improves the encapsulation yield.
Drawings
Fig. 1a to fig. 1c are schematic structural diagrams showing steps of a packaging method for a fingerprint identification chip in the prior art.
Fig. 2a to 2c are schematic structural diagrams showing steps of another fingerprint identification chip packaging method in the prior art.
Fig. 3 to fig. 10 show the structural schematic diagram presented in each step of the packaging method of the fan-out fingerprint identification chip of the present invention, wherein fig. 10 shows the structural schematic diagram of the packaging structure of the fan-out fingerprint identification chip of the present invention.
Description of the element reference numerals
201 supporting a substrate
202 separating layers
203 fingerprint acquisition chip
204 encapsulation layer
205 rewiring layer
206 fingerprint processing chip
207 protective layer
208 metal bump
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structure are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, amount and ratio of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.
As shown in fig. 3 to 10, the present embodiment provides a packaging method of a fan-out fingerprint identification chip, where the packaging method includes the steps of:
as shown in fig. 3, step 1) is performed to provide a supporting substrate 201, and a separation layer 202 is formed on the supporting substrate 201.
The support base 201 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate, as an example. In this embodiment, the support substrate 201 is a glass substrate, which has a low cost, is easy to form the separation layer 202 on the surface thereof, and can reduce the difficulty of the subsequent stripping process.
As an example, the separation layer 202 includes a light-to-heat conversion Layer (LTHC), and is formed on the support substrate 201 by a spin coating process and then cured by a curing process. The light-heat conversion Layer (LTHC) has stable performance and smooth surface, is beneficial to obtaining flatness subsequently, and has lower stripping difficulty in the subsequent stripping process.
As shown in fig. 4, step 2) is then performed, providing a fingerprint acquisition chip 203, and fixing the fingerprint acquisition chip 203 on the separation layer 202, wherein the electrodes of the fingerprint acquisition chip 203 face the separation layer 202.
The fingerprint acquisition chip 203 is used for adopting human fingerprints and transmitting acquired signals to the fingerprint processing chip 206 for processing.
As shown in fig. 5, step 3) is performed, the fingerprint acquisition chip 203 is packaged by a packaging layer 204, and a top surface of the fingerprint acquisition chip 203 is exposed to the packaging layer 204.
As an example, the method for encapsulating the fingerprint acquisition chip 203 with the encapsulation layer 204 includes one of compression molding, transfer molding, liquid encapsulation, vacuum lamination and spin coating, and the material of the encapsulation layer 204 includes one of polyimide, silicone and epoxy.
Then, the method further comprises the step of thinning the packaging layer 204 and exposing the fingerprint acquisition chip 203 to the packaging layer 204, so as to improve the acquisition precision of the fingerprint acquisition chip 203.
As shown in fig. 6, step 4) is then performed to peel off the fingerprint acquisition chip 203 and the supporting substrate 201 based on the separation layer 202, and expose the encapsulation layer 204 and the electrodes of the fingerprint acquisition chip 203.
Specifically, the separation layer 202 is a photothermal conversion layer, and laser is adopted to irradiate the photothermal conversion layer, so that the photothermal conversion layer is separated from the packaging layer 204, the fingerprint acquisition chip 203 and the supporting substrate 201, and then the fingerprint acquisition chip 203 and the supporting substrate 201 are peeled off, and an electrode of the fingerprint acquisition chip 203 is exposed on the peeling surface, so as to facilitate the subsequent manufacturing of the rewiring layer 205.
As shown in fig. 7, step 5) is performed to fabricate a redistribution layer 205 on the package layer 204 and the fingerprint acquisition chip 203, and a first surface of the redistribution layer 205 is connected to the electrode of the fingerprint acquisition chip 203.
The redistribution layer 205 may include a plurality of dielectric layers and a plurality of metal wiring layers arranged according to a pattern requirement, and two adjacent metal wiring layers are connected by a conductive plug. The dielectric layer can be made of one or a combination of more than two of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass. In this embodiment, the dielectric layer may be made of PI (polyimide), so as to further reduce the process difficulty and the process cost. The material of the metal wiring layer comprises one or the combination of more than two of copper, aluminum, nickel, gold, silver and titanium. In this embodiment, the metal wiring layer is made of copper.
As shown in fig. 8 to 9, step 6) is then performed to provide a fingerprint processing chip 206, and the fingerprint processing chip 206 is bonded to the second surface of the redistribution layer 205, where the fingerprint processing chip 206 is connected to the fingerprint acquisition chip 203 through the redistribution layer 205. The fingerprint processing chip 206 is configured to perform feature extraction and feature ratio peer-to-peer processing on the fingerprint signal acquired by the fingerprint acquisition chip 203, so as to implement a fingerprint identification function.
In this embodiment, after the fingerprint processing chip 206 is mounted on the redistribution layer 205 through the metal pad, a gap is formed between the fingerprint processing chip 206 and the redistribution layer 205, and the embodiment further includes a step of forming a protection layer 207 in the gap, where the protection layer 207 completely fills the gap. For example, the protection layer 207 is selected as epoxy resin, and may be formed in a gap between the fingerprint processing chip 206 and the redistribution layer 205 by using a dispensing or molding method. The protective layer 207 can effectively increase the bonding strength and the compression strength between the fingerprint processing chip 206 and the redistribution layer 205.
Preferably, after the fingerprint processing chip 206 is bonded to the second surface of the redistribution layer 205, the fingerprint acquisition chip 203 and the fingerprint processing chip 206 are overlapped in the vertical direction, which can greatly reduce the overall volume of the package structure.
As shown in fig. 10, step 7) is finally performed to form a metal bump 208 on the second surface of the redistribution layer 205, so as to achieve electrical leading-out of the fingerprint processing chip 206 through the redistribution layer 205.
In the present embodiment, the metal bump 208 includes one of a tin solder, a silver solder, and a gold-tin alloy solder.
As shown in fig. 10, this embodiment further provides a package structure of a fan-out fingerprint identification chip, where the package structure includes: a re-routing layer 205, the re-routing layer 205 comprising a first side and an opposing second side; a fingerprint acquisition chip 203 bonded to a first surface of the rewiring layer 205, an electrode of the fingerprint acquisition chip 203 being connected to the rewiring layer 205; the packaging layer 204 coats the side surface of the fingerprint acquisition chip 203, and the top surface of the fingerprint acquisition chip 203 is exposed out of the packaging layer 204; a fingerprint processing chip 206 bonded to the second surface of the rewiring layer 205, the fingerprint processing chip 206 being connected to the fingerprint acquisition chip 203 through the rewiring layer 205; and a metal bump 208 formed on the second surface of the redistribution layer 205 to electrically extract the fingerprint processing chip 206 through the redistribution layer 205.
In this embodiment, the fingerprint acquisition chip 203 and the fingerprint processing chip 206 are disposed in a vertically overlapped manner, which can greatly reduce the overall size of the package structure.
A gap is formed between the fingerprint processing chip 206 and the rewiring layer 205, a protective layer 207 is formed in the gap, and the protective layer 207 completely fills the gap. For example, the protective layer 207 is selected to be epoxy. The protective layer 207 can effectively increase the bonding strength and the compression strength between the fingerprint processing chip 206 and the redistribution layer 205.
The encapsulation layer 204 may be one of polyimide, silicone, and epoxy. The metal bump 208 may be one of a tin solder, a silver solder, and a gold-tin alloy solder.
As described above, the utility model discloses a packaging structure and packaging method of fan-out type fingerprint identification chip has following beneficial effect:
1) the utility model discloses a Fan-out type encapsulation (Fan out) fingerprint identification chip can be integrated in same packaging structure with fingerprint collection chip 203 and fingerprint processing chip 206, and fingerprint collection chip 203 and fingerprint processing chip 206 are perpendicular settings, compare in current other fingerprint identification chip encapsulation, have with low costs, thickness is little, the advantage that the yield is high.
2) The utility model discloses do not need the routing technology simultaneously, also need not costly silicon perforation Technology (TSV), and can realize the encapsulation of fingerprint identification chip, greatly reduced the technology degree of difficulty and cost.
3) The utility model discloses a Fan-out encapsulation (Fan out) technology, the electricity of chip is drawn forth and is not needed traditional FPC board, can reduce the thickness of encapsulation and the stability of structure is drawn forth to the electrical property, improves the encapsulation yield.
Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (6)
1. A packaging structure of fan-out fingerprint identification chip, characterized in that, packaging structure includes:
a rewiring layer including a first side and an opposing second side;
the fingerprint acquisition chip is jointed with the first surface of the rewiring layer, and an electrode of the fingerprint acquisition chip is connected with the rewiring layer;
the packaging layer coats the side face of the fingerprint acquisition chip, and the top face of the fingerprint acquisition chip is exposed out of the packaging layer;
the fingerprint processing chip is jointed with the second surface of the rewiring layer and is connected with the fingerprint acquisition chip through the rewiring layer;
and the metal bump is formed on the second surface of the rewiring layer so as to realize the electrical leading-out of the fingerprint processing chip through the rewiring layer.
2. The package structure of the fan-out fingerprint identification chip of claim 1, wherein: the fingerprint acquisition chip and the fingerprint processing chip are arranged in a superposition mode in the vertical direction.
3. The package structure of the fan-out fingerprint identification chip of claim 1, wherein: a gap is formed between the fingerprint processing chip and the rewiring layer, a protective layer is formed in the gap, and the protective layer completely fills the gap.
4. The package structure of the fan-out fingerprint identification chip of claim 3, wherein: the protective layer is made of epoxy resin.
5. The package structure of the fan-out fingerprint identification chip of claim 1, wherein: the encapsulation layer includes one of polyimide, silicone, and epoxy.
6. The package structure of the fan-out fingerprint identification chip of claim 1, wherein: the metal bump comprises one of tin solder, silver solder and gold-tin alloy solder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920869199.XU CN209843707U (en) | 2019-06-11 | 2019-06-11 | Packaging structure of fan-out type fingerprint identification chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920869199.XU CN209843707U (en) | 2019-06-11 | 2019-06-11 | Packaging structure of fan-out type fingerprint identification chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209843707U true CN209843707U (en) | 2019-12-24 |
Family
ID=68898300
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920869199.XU Active CN209843707U (en) | 2019-06-11 | 2019-06-11 | Packaging structure of fan-out type fingerprint identification chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209843707U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110164859A (en) * | 2019-06-11 | 2019-08-23 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure and packaging method of fan-out-type fingerprint recognition chip |
-
2019
- 2019-06-11 CN CN201920869199.XU patent/CN209843707U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110164859A (en) * | 2019-06-11 | 2019-08-23 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure and packaging method of fan-out-type fingerprint recognition chip |
| CN110164859B (en) * | 2019-06-11 | 2024-09-06 | 盛合晶微半导体(江阴)有限公司 | Packaging structure and packaging method of fan-out fingerprint identification chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110277356B (en) | Packaging structure and packaging method of antenna feeder | |
| CN107146779B (en) | Packaging structure and packaging method of fingerprint identification chip | |
| CN111370385A (en) | Fan-out type system-in-package structure and manufacturing method thereof | |
| CN111370387A (en) | Fan-out type system-in-package structure and manufacturing method thereof | |
| US11756871B2 (en) | Fan-out packaging structure and method | |
| CN211480019U (en) | Fan-out type system-in-package structure | |
| CN111370386A (en) | Fan-out type system-in-package structure and manufacturing method thereof | |
| CN110854093A (en) | Three-dimensional laminated packaging structure and manufacturing method thereof | |
| CN212392240U (en) | Fan-out type packaging structure | |
| CN107170721B (en) | Packaging structure and packaging method of fingerprint identification chip | |
| CN212084995U (en) | Wafer level package structure | |
| CN209843707U (en) | Packaging structure of fan-out type fingerprint identification chip | |
| CN210467768U (en) | Wafer level chip packaging structure | |
| CN114188227A (en) | Fan-out type packaging structure and packaging method | |
| CN114188226A (en) | Fan-out type packaging structure and packaging method | |
| CN110164859B (en) | Packaging structure and packaging method of fan-out fingerprint identification chip | |
| CN209880614U (en) | Packaging structure of fan-out type fingerprint identification chip | |
| CN112582287A (en) | Wafer-level chip packaging structure and packaging method | |
| CN112289766A (en) | Packaged antenna module and preparation method thereof | |
| CN212303700U (en) | System-in-package structure of LED chip | |
| CN210692529U (en) | Antenna packaging structure | |
| CN210040521U (en) | Packaged antenna module | |
| CN112151394A (en) | Packaging structure and packaging method of three-dimensional fan-out type fingerprint identification chip | |
| CN112151395A (en) | Packaging structure and packaging method of three-dimensional fan-out type fingerprint identification chip | |
| CN210692485U (en) | Antenna packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |