CN114975136A - System wafer level chip packaging method and structure - Google Patents

System wafer level chip packaging method and structure Download PDF

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Publication number
CN114975136A
CN114975136A CN202111235109.XA CN202111235109A CN114975136A CN 114975136 A CN114975136 A CN 114975136A CN 202111235109 A CN202111235109 A CN 202111235109A CN 114975136 A CN114975136 A CN 114975136A
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China
Prior art keywords
layer
metal bump
wiring layer
chip
forming
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CN202111235109.XA
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Chinese (zh)
Inventor
黄晗
陈彦亨
林正忠
李俊德
伍信桦
薛兴涛
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SJ Semiconductor Jiangyin Corp
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Shenghejing Micro Semiconductor Jiangyin Co Ltd
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Priority to CN202111235109.XA priority Critical patent/CN114975136A/en
Publication of CN114975136A publication Critical patent/CN114975136A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/111—Manufacture and pre-treatment of the bump connector preform
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

The invention provides a system wafer level chip packaging method and a structure. The method comprises the following steps: providing a carrier, and forming a first wiring layer; forming a first solder ball, electrically connecting with the first metal bump, and mounting the SMT element on the first metal bump; forming a first plastic packaging layer; forming a second wiring layer, wherein the second metal bump is electrically connected with the first solder ball; mounting the chip on the second wiring layer and electrically connecting the chip with the second metal bump; forming a second plastic packaging layer; removing the carrier, and transferring the structure obtained after the carrier is removed to a temporary substrate in a mode that the chip faces downwards to expose the first wiring layer; forming a second solder ball to be electrically connected with the first metal bump; the temporary substrate is removed. The MUF process is adopted to replace the traditional Underfill to be applied to the wafer-level advanced integrated packaging, so that the plastic packaging requirements of different components can be met, the manufacturing procedures can be reduced, the manufacturing cost can be reduced, the bonding surfaces of different materials in a chip can be reduced, the risk of component failure is reduced, and the reliability of the component is improved.

Description

System wafer level chip packaging method and structure
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to the field of back-end packaging, and specifically relates to a packaging method and a structure of a system wafer-level chip.
Background
With the rapid development of integrated circuit technology, the integration degree of devices is increasing and the line width is shrinking, which brings more and more challenges to chip packaging. In the existing wafer-level chip packaging technology, after an electrical lead-out structure is prepared on a wafer-level chip, an external chip is electrically connected to the wafer-level chip, and then the external chip is coated by a capillary Underfill technology (underfil). The preparation process is complex, the packaging cost is increased, and the size of the packaged device is large and the heat dissipation performance of the device is poor due to the existence of the underfill layer.
Disclosure of Invention
In view of the above disadvantages of the prior art, an object of the present invention is to provide a method and structure for packaging a wafer-level chip, which are used to solve the problems of complicated preparation process, increased packaging cost, large size of packaged devices due to the presence of an Underfill layer, poor heat dissipation performance of the packaged devices, and the like in the conventional wafer-level chip packaging technology, in which an electrical lead-out structure is first prepared on a wafer-level chip, an external chip is then electrically connected to the wafer-level chip, and the external chip is then encapsulated by a capillary Underfill technology (underfil).
To achieve the above and other related objects, the present invention provides a method for packaging a wafer level chip, comprising:
providing a carrier, and forming a first wiring layer on the carrier, wherein the first wiring layer comprises a first dielectric layer and a first metal bump, and the first metal bump is exposed on the surface of the first dielectric layer;
forming a first solder ball by ball-planting on the first wiring layer, wherein the first solder ball is electrically connected with the first metal bump, and the SMT component is mounted on the first metal bump;
forming a first plastic package layer, wherein the first solder balls and the SMT element are positioned in the first plastic package layer, and the first solder balls are exposed on the surface of the first plastic package layer;
forming a second wiring layer on the first plastic packaging layer, wherein the second wiring layer comprises a second dielectric layer and a second metal bump, the second metal bump is exposed on the surface of the second dielectric layer, and the second metal bump is electrically connected with the first solder ball;
mounting a chip on the second wiring layer, the chip being electrically connected to the second metal bump;
forming a second plastic package layer, wherein the chip is positioned in the second plastic package layer and is exposed on the surface of the second plastic package layer;
removing the carrier, and transferring the structure obtained after the carrier is removed to a temporary substrate in a mode that a chip faces downwards to expose the first wiring layer;
planting balls on the surface of the first wiring layer, which is far away from the first solder balls, so as to form second solder balls, wherein the second solder balls are electrically connected with the first metal bumps;
and removing the temporary substrate.
Optionally, after the carrier is provided, a step of forming a separation layer on the carrier is further included, the first wiring layer is formed on the separation layer, and after the second molding layer is formed, the carrier is separated from the separation layer.
Optionally, the first solder ball is formed first, and then the SMT component is mounted on the first metal bump.
Optionally, a step of performing surface planarization is further included after the first molding layer and the second molding layer are formed to expose the first solder balls and the chip, respectively.
Optionally, before forming the second solder ball, a step of forming an opening in the first wiring layer by laser etching to expose the first metal bump is further included, and the second solder ball is located in the opening.
Optionally, the chip is electrically connected to the second metal bump by ball bonding.
Optionally, the system wafer level chip packaging method further includes a step of cutting the obtained structure to separate into a plurality of independent devices after removing the temporary substrate.
The invention also provides a system wafer level chip packaging structure, which comprises a first wiring layer, a second wiring layer, a first solder ball, a second solder ball, an SMT element, a chip, a first plastic package layer and a second plastic package layer; the first wiring layer comprises a first dielectric layer and a first metal bump, the first metal bump is exposed on the surface of the first dielectric layer, the second wiring layer comprises a second dielectric layer and a second metal bump, and the second metal bump is exposed on the surface of the second dielectric layer; the first plastic package layer is located between the first wiring layer and the second wiring layer, the second plastic package layer is located on the surface, away from the first plastic package layer, of the second wiring layer, the SMT element and the first solder balls are located in the first plastic package layer, two ends of each first solder ball are electrically connected with the first metal bump and the second metal bump respectively, and the SMT element is electrically connected with the first metal bumps; the chip is positioned in the second plastic package layer and is electrically connected with the second metal bump, and the surface of the chip is exposed on the surface of the second plastic package layer, which is far away from the second wiring layer; the second solder balls are located on the surface, away from the first plastic packaging layer, of the first wiring layer and electrically connected with the first metal bumps.
Optionally, the number of the first solder balls is greater than that of the second solder balls.
Optionally, the SMT component is located between a plurality of first solder balls.
As described above, the system wafer level chip packaging method and structure of the invention have the following beneficial effects: the invention adopts plastic package technology (molding) to wrap the external chip and the SMT element in the packaging structure, and the MUF (molded Underfill) technology replaces the traditional Underfill technology to be applied to wafer level (wafer level) advanced integrated packaging, thereby not only meeting the plastic package requirements of different components, but also reducing the manufacturing procedures and the manufacturing cost, reducing the bonding surfaces of different materials in the chip, reducing the risk of component failure and improving the reliability of the component, and effectively reducing the size of the packaging structure through a multilayer bonding structure, improving the heat dissipation performance of the component and reducing the power consumption of the component. In addition, the invention adopts a metal bump (bump) process to interconnect the wafer level chips, thereby ensuring good conduction of the upper layer and the lower layer. The structure packaged by the method has better electric heating performance and high-efficiency transmission performance.
Drawings
Fig. 1-16 are schematic cross-sectional views of exemplary steps of a system wafer level chip packaging method according to the present invention.
Description of the element reference numerals
11 vector
12 separating layer
13 first dielectric layer
14 first metal bump
15 first solder ball
16 SMT component
17 first plastic packaging layer
18 second dielectric layer
19 second metal bump
20 chip
21 second plastic packaging layer
22 temporary substrate
23 second solder ball
24 open pores
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated. In order to keep the drawings as concise as possible, not all features of a single figure may be labeled in their entirety.
As shown in fig. 1-16, the present invention provides a system wafer level chip packaging method, comprising the steps of:
providing a carrier 11, and forming a first wiring layer on the carrier 11, where the first wiring layer includes a first dielectric layer 13 and a first metal bump 14(bump), and the first metal bump 14 is exposed on a surface of the first dielectric layer 13; the carrier 11 may be a single-layer or multi-layer structure, and specifically refer to fig. 1, in order to facilitate peeling of a subsequent structure, as an example, after the carrier 11 is provided, a separation layer 12 may be formed on the surface of the carrier 11 by a process including, but not limited to, coating, and the resulting structure is shown in fig. 2; then, forming the first wiring layer on the separation layer 12, and obtaining a structure as shown in fig. 3;
forming a first solder ball 15 on the first wiring layer by ball mounting (ball mount), wherein the first solder ball 15 is electrically connected to the first metal bump 14, and the SMT component 16 is mounted on the first metal bump 14; in this process, it is preferable that the first solder balls 15 are formed first, the obtained structure is shown in fig. 4, and then the SMT component 16 is mounted on the first metal bumps 14, and the obtained structure is shown in fig. 5, which helps to avoid adverse effects on the SMT component 16 during the process of forming the first solder balls 15; the SMT elements 16 can be active or passive devices, including but not limited to one of resistors, capacitors, inductors and the like, and the number of the SMT elements 16 can be single or more than 2; the number of the first solder balls 15 is preferably plural to ensure the electrical connection of the upper and lower layers, the SMT component 16 is preferably located in the middle of the plural first solder balls 15, and the material of the first solder balls 15 includes but is not limited to tin, gold, copper or an alloy of tin and copper;
forming a first plastic packaging layer 17, wherein the first solder balls 15 and the SMT components 16 are located in the first plastic packaging layer 17, and the first solder balls 15 are exposed on the surface of the first plastic packaging layer 17; since the height of the molding process is difficult to be precisely controlled, and meanwhile, in order to ensure the molding quality, the first molding layer 17 with a height greater than that of the first solder balls 15 is usually formed first to completely cover the first solder balls 15 and the SMT components 16, and the resulting structure is shown in fig. 6, and then a surface planarization process, such as Chemical Mechanical Polishing (CMP), is performed to perform a surface planarization process on the first molding layer 17 until the upper surfaces of the first solder balls 15 are exposed, and the resulting structure is shown in fig. 7; through surface planarization treatment, the quality of the first plastic packaging layer 17 can be further improved, and collapse is avoided;
forming a second wiring layer on the first plastic package layer 17, where the second wiring layer includes a second dielectric layer 18 and a second metal bump, the second metal bump is exposed on the surface of the second dielectric layer 18, and the second metal bump is electrically connected to the first solder ball 15, and the structure obtained in this step is as shown in fig. 8;
mounting and typically flip-chip mounting a chip 20 onto the second wiring layer, the chip 20 being electrically connected to the second metal bumps, the resulting structure being shown in fig. 9; if the chip 20 is formed with solder balls in advance, the solder balls of the chip 20 are directly soldered to the second metal bumps, and if the chip 20 is not formed with solder balls in advance, the second metal bumps are implanted with solder balls to form solder balls, and then the chip 20 is soldered;
forming a second molding layer 21, wherein the chip 20 is located in the second molding layer 21 and exposed on the surface of the second molding layer 21; also, since the height of the molding process is difficult to be precisely controlled, in this step, in order to ensure the molding quality, the second molding layer 21 with a height greater than that of the chip 20 is usually formed to completely cover the chip 20, and the resulting structure is shown in fig. 10, and then a surface planarization process, such as a Chemical Mechanical Polishing (CMP) process, is performed on the second molding layer 21 to expose the upper surface of the chip 20, and the resulting structure is shown in fig. 11; through surface planarization treatment, the quality of the second plastic package layer 21 can be further improved, and collapse is avoided;
removing the carrier 11, and transferring the structure obtained after removing the carrier 11 onto a temporary substrate 22 in a manner that the chip 20 faces downwards to expose the first wiring layer, wherein the structure obtained in the step is shown in fig. 12; for example, in the case where the separation layer 12 of the UV resin material is formed in advance, laser irradiation may be performed from the back surface (surface on which other structures are not formed) of the carrier 11 to peel off the carrier 11;
planting balls on the surface of the first wiring layer, which is away from the first solder balls, to form second solder balls 23, wherein the second solder balls 23 are electrically connected with the first metal bumps 14; as the first metal bump 14 in the previously formed first wiring layer is covered by the first dielectric layer 13, and in order to improve the stability of the second solder ball 23 and ensure the sufficient electrical connection between the second solder ball 23 and the first metal bump 14, as an example, in this step, an opening 24 may be formed in the first dielectric layer 13 by using a process including, but not limited to, laser etching to expose the first metal bump 14, so as to obtain the structure shown in fig. 13, and then the second solder ball 23 is formed by ball-planting in the opening 24, so as to obtain the structure shown in fig. 14; the number of the second solder balls 23 is preferably 2 or more to ensure sufficient electrical connection with an external structure;
the temporary substrate 22 is removed and the resulting structure is shown in fig. 15.
The invention adopts plastic package technology (molding) to wrap the external chip and the SMT element in the packaging structure, and the MUF (molded Underfill) technology replaces the traditional Underfill technology to be applied to wafer level (wafer level) advanced integrated packaging, thereby not only meeting the plastic package requirements of different components, but also reducing the manufacturing procedures and the manufacturing cost, reducing the bonding surfaces of different materials in the chip, reducing the risk of component failure and improving the reliability of the component, and effectively reducing the size of the packaging structure through a multilayer bonding structure, improving the heat dissipation performance of the component and reducing the power consumption of the component. In addition, the invention adopts the metal bump process to interconnect the wafer level chips, thereby ensuring good conduction of the upper layer and the lower layer. The structure packaged by the method of the invention has better electric heating performance and high-efficiency transmission performance.
As an example, the first wiring layer is formed by first forming a first dielectric layer 13 on the carrier 11 by using a vapor deposition process, and then forming a first metal material layer on the surface of the first dielectric layer 13 by using one or more methods, including but not limited to a sputtering method, an electroplating method, an electroless plating method, and the like, and then performing photolithography etching on the first metal material layer to form a plurality of independent first metal bumps 14. The material of the first dielectric layer 13 includes but is not limited to one or a combination of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, fluorine-containing glass, and may also be other high-K dielectric materials; the material of the first metal bump 14 includes, but is not limited to, a combination (preferably a copper layer) of one or more of gold, silver, copper, aluminum, and the like. The first dielectric layer 13 and the first metal bump 14 may be of a single-layer or multi-layer structure, but it is necessary to ensure that the first metal bumps 14 of different layers are electrically connected to each other. The material and the manufacturing process of the second wiring layer may be the same as those of the first wiring layer, and a detailed description thereof is omitted.
The carrier 11 mainly plays a supporting role, and avoids the defects of bending deformation and the like in the device preparation process. By way of example, the carrier 11 includes, but is not limited to, a glass, a silicon substrate, a sapphire substrate, a ceramic substrate, a metal substrate, and the like, which have a certain hardness and are not easily bent. In this embodiment, a transparent substrate such as a glass substrate is preferable, which facilitates that UV light irradiation can be performed from the back surface of the carrier 11 to peel the carrier 11 from the separation layer 12 later when peeling the separation layer 12. Before the separation layer 12 is prepared, the carrier 11 may be washed and dried.
The separation layer 12 may be a single-layer or multi-layer structure, and may include, for example, a release layer and a protective layer on the surface of the release layer. Specifically, the release layer includes, but is not limited to, a combination of one or more of a carbon material layer, a resin material layer, and an organic material layer, and the protective layer includes, but is not limited to, a polyimide layer. For example, the carrier 11 is a transparent substrate such as glass, and the separation layer 12 is a UV resin layer, and the separation layer 12 may be peeled off by irradiating the separation layer 12 from the back surface of the carrier 11 at the time of subsequent peeling. The separation layer 12 may also be an LTHC light-to-heat conversion layer, and the subsequent step may be heating the LTHC light-to-heat conversion layer based on a method such as laser, so as to separate the carrier 11 from the LTHC light-to-heat conversion layer, thereby reducing the difficulty of the stripping process and preventing the device from being damaged. The method for forming the separation layer 12 may be determined according to the material thereof, and may be one or more selected from spin coating, spray coating, direct attachment, and the like.
The temporary substrate 22 may be made of the same material as the carrier 11, and includes, but is not limited to, a substrate that has a certain hardness and is not easily bent and deformed, such as a glass substrate, a silicon substrate, a sapphire substrate, a ceramic substrate, a metal substrate, etc., and a separation material layer may also be formed on the surface of the substrate to facilitate subsequent peeling.
As an example, the first molding compound layer 17 and/or the second molding compound layer 21 may be formed by a combination of one or more methods including, but not limited to, compression molding, transfer molding, liquid sealing, vacuum lamination, spin coating, and the like, and the materials of the first molding compound layer 17 and the second molding compound layer 21 include, but not limited to, a combination of one or more of polyimide, silicone, and epoxy. In order to simplify the manufacturing process, the material and the forming process of the first molding layer 17 and the second molding layer 21 are preferably the same.
The invention can package a plurality of chips at the same time, for example, package a wafer formed with a plurality of chips. Thus, after removing the temporary substrate 22, a step of cutting the resulting structure to separate into a plurality of individual devices is also required. Specifically, as shown in fig. 16, after the temporary substrate 22 is peeled, the resulting structure is transferred to a dicing station and then diced using techniques including, but not limited to, laser dicing to separate individual devices comprising the foregoing structures.
As shown in fig. 15, the present invention further provides a system wafer level chip package structure, which can be prepared based on any of the above packaging methods, so that the contents of the foregoing description can be incorporated herein in its entirety. The system wafer level chip package comprises a first wiring layer, a second wiring layer, first solder balls 15, second solder balls 23, an SMT (surface mount technology) element 16, a chip 20, a first plastic package layer 17 and a second plastic package layer 21; the first wiring layer comprises a first dielectric layer 13 and a first metal bump 14, the first metal bump 14 is exposed on the surface of the first dielectric layer 13, the second wiring layer comprises a second dielectric layer 18 and a second metal bump, and the second metal bump is exposed on the surface of the second dielectric layer 18; the first plastic package layer 17 is located between the first wiring layer and the second wiring layer, the second plastic package layer 21 is located on the surface of the second wiring layer away from the first plastic package layer 17, the SMT component 16 and the first solder ball 15 are located in the first plastic package layer 17, two ends of the first solder ball 15 are electrically connected with the first metal bump 14 and the second metal bump respectively, and the SMT component 16 is electrically connected with the first metal bump 14; the chip 20 is located in the second plastic package layer 21 and electrically connected to the second metal bump, and a surface of the chip 20 is exposed on a surface of the second plastic package layer 21 away from the second wiring layer; the second solder balls 23 are located on the surface of the first wiring layer away from the first molding layer 17, and are electrically connected to the first metal bumps 14.
In one example, the number of the first solder balls 15 and the number of the second solder balls 23 are two or more, and the number of the first solder balls 15 is greater than the number of the second solder balls 23. The material of the first solder ball 15 and the second solder ball 23 includes, but is not limited to, tin, gold, copper, or an alloy of tin and copper.
In one example, the SMT component 16 is located between the plurality of first solder balls 15, and may be single or multiple. The SMT component 16 may be an active component and/or a passive component, including but not limited to any one of a capacitor, an inductor, and a resistor.
The material of the first metal bump 14 and the second metal bump includes, but is not limited to, one or more of gold, silver, copper, aluminum, and the like.
The first molding compound layer 17 and the second molding compound layer 21 include, but are not limited to, a combination of one or more of polyimide, silicone, and epoxy.
For more descriptions of the wafer level chip package structure of the system, please refer to the foregoing description, which is omitted for brevity.
In summary, the present invention provides a method and structure for packaging a system wafer level chip. The invention adopts the plastic package technology to wrap the external chip and the SMT element in the packaging structure, and the MUF technology replaces the traditional Underfill to be applied to the wafer-level advanced integrated packaging, thereby not only meeting the plastic package requirements of different components, but also reducing the processing procedures, reducing the processing cost, reducing the bonding surfaces of different materials in the chip, reducing the failure risk of the device, improving the reliability of the device, effectively reducing the size of the packaging structure through a multilayer bonding structure, improving the heat radiation performance of the device and reducing the power consumption of the device. In addition, the invention adopts the metal bump process to interconnect the wafer level chips, thereby ensuring good conduction of the upper layer and the lower layer. The structure packaged by the method has better electric heating performance and high-efficiency transmission performance. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A system wafer level chip packaging method is characterized by comprising the following steps:
providing a carrier, and forming a first wiring layer on the carrier, wherein the first wiring layer comprises a first dielectric layer and a first metal bump, and the first metal bump is exposed on the surface of the first dielectric layer;
forming a first solder ball by ball-planting on the first wiring layer, wherein the first solder ball is electrically connected with the first metal bump, and the SMT component is mounted on the first metal bump;
forming a first plastic package layer, wherein the first solder balls and the SMT element are positioned in the first plastic package layer, and the first solder balls are exposed on the surface of the first plastic package layer;
forming a second wiring layer on the first plastic packaging layer, wherein the second wiring layer comprises a second dielectric layer and a second metal bump, the second metal bump is exposed on the surface of the second dielectric layer, and the second metal bump is electrically connected with the first solder ball;
mounting a chip on the second wiring layer, the chip being electrically connected to the second metal bump;
forming a second plastic package layer, wherein the chip is positioned in the second plastic package layer and is exposed on the surface of the second plastic package layer;
removing the carrier, and transferring the structure obtained after the carrier is removed to a temporary substrate in a mode that a chip faces downwards to expose the first wiring layer;
planting balls on the surface of the first wiring layer, which is far away from the first solder balls, so as to form second solder balls, wherein the second solder balls are electrically connected with the first metal bumps;
removing the temporary substrate.
2. The system wafer level chip packaging method according to claim 1, further comprising a step of forming a separation layer on the carrier after the carrier is provided, wherein the first wiring layer is formed on the separation layer, and the carrier is separated from the separation layer after the second molding layer is formed.
3. The system wafer level chip packaging method of claim 2, wherein the first solder balls are formed first, and then the SMT component is mounted on the first metal bumps.
4. The system wafer level chip packaging method of claim 1, further comprising a step of surface planarization after forming the first and second molding layers to expose the first solder balls and the chip, respectively.
5. The system wafer level chip packaging method of claim 1, further comprising a step of forming an opening in the first wiring layer by laser etching to expose the first metal bump before forming the second solder ball, wherein the second solder ball is located in the opening.
6. The system wafer level chip packaging method as claimed in claim 1, wherein the chip is electrically connected to the second metal bump by ball bonding.
7. The system wafer-level chip packaging method according to claim 1, further comprising a step of dicing the resulting structure to separate into a plurality of individual devices after removing the temporary substrate.
8. A system wafer level chip package structure is characterized in that the system wafer level chip package comprises a first wiring layer, a second wiring layer, a first solder ball, a second solder ball, an SMT element, a chip, a first plastic package layer and a second plastic package layer; the first wiring layer comprises a first dielectric layer and a first metal bump, the first metal bump is exposed on the surface of the first dielectric layer, the second wiring layer comprises a second dielectric layer and a second metal bump, and the second metal bump is exposed on the surface of the second dielectric layer; the first plastic package layer is located between the first wiring layer and the second wiring layer, the second plastic package layer is located on the surface, away from the first plastic package layer, of the second wiring layer, the SMT element and the first solder balls are located in the first plastic package layer, two ends of each first solder ball are electrically connected with the first metal bump and the second metal bump respectively, and the SMT element is electrically connected with the first metal bumps; the chip is positioned in the second plastic package layer and is electrically connected with the second metal bump, and the surface of the chip is exposed on the surface of the second plastic package layer, which is far away from the second wiring layer; the second solder balls are located on the surface, away from the first plastic packaging layer, of the first wiring layer and electrically connected with the first metal bumps.
9. The system wafer level chip package structure of claim 8, wherein the number of the first solder balls is greater than the number of the second solder balls.
10. The system wafer level chip package structure of claim 8, wherein the SMT component is located between a plurality of first solder balls.
CN202111235109.XA 2021-10-22 2021-10-22 System wafer level chip packaging method and structure Pending CN114975136A (en)

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