CN114975242A - Preparation method of 2.5D packaging structure - Google Patents
Preparation method of 2.5D packaging structure Download PDFInfo
- Publication number
- CN114975242A CN114975242A CN202210441937.7A CN202210441937A CN114975242A CN 114975242 A CN114975242 A CN 114975242A CN 202210441937 A CN202210441937 A CN 202210441937A CN 114975242 A CN114975242 A CN 114975242A
- Authority
- CN
- China
- Prior art keywords
- layer
- chip
- bottom metal
- semiconductor substrate
- tsv conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/111—Manufacture and pre-treatment of the bump connector preform
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
The invention provides a preparation method of a 2.5D packaging structure, which is characterized in that a process of removing a bottom metal layer is placed at the end, so that the bottom metal layer can isolate the influence of laser irradiation on the packaging structure, particularly a chip when a second supporting substrate is removed, the 2.5D packaging structure is protected to protect the chip, and the success rate and the yield of reliability test of the 2.5D packaging chip are improved; the bottom metal layer is easy to form and remove, the packaging cost cannot be increased, and the process is simple and effective; the second surface of the semiconductor substrate is subjected to chemical mechanical polishing, so that the flatness of the semiconductor substrate is improved, the bonding strength of a plurality of interfaces in subsequent packaging can be improved, and the contact resistance of the bottom metal layer and the TSV conductive column can be reduced; the TSV conductive columns, the connecting bonding pads and the metal bumps are located on the same vertical line, so that resistance can be effectively reduced, and signal delay can be effectively reduced.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a preparation method of a 2.5D packaging structure.
Background
With the continuous improvement of performance requirements of High Performance Computing (HPC) chips such as CPUs, GPUs, FPGAs and the like, the traditional packaging technologies such as flip chip packaging (FC), Package On Package (POP) and the like cannot meet the requirements, and the requirements for 2.5D/3D packaging technologies are gradually increasing. At present, the well-known 2.5D packaging technology has power-accumulating CoWoS, and can package a plurality of chips together, thereby achieving the effects of small packaging volume, low power consumption and few pins.
During 2.5D packaging, process changes can cause single or multiple chips to fail, which in turn can cause the reliability test results of the entire package structure to fail. Therefore, there is a need to continuously optimize and improve the process, and the present invention provides a method for manufacturing a 2.5D package structure to improve the yield.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a method for manufacturing a 2.5D package structure, which is used to solve the problem that the chip is prone to fail in reliability test and thus the yield is affected in the prior art.
In order to achieve the above objects and other related objects, the present invention provides a method for manufacturing a 2.5D package structure, wherein the method for manufacturing the 2.5D package structure includes the following steps:
s1, providing a semiconductor substrate, where the semiconductor substrate includes a first surface and a second surface that are disposed opposite to each other, and forming a TSV conductive pillar in the semiconductor substrate, where the TSV conductive pillar includes a TSV conductive pillar first end exposed at the first surface of the semiconductor substrate and a TSV conductive pillar second end located in the semiconductor substrate;
s2, forming a first dielectric layer on the first surface of the semiconductor substrate, and etching the first dielectric layer to expose the first end of the TSV conductive post;
s3, forming a connection pad electrically connected to the first end of the TSV conductive pillar on the first dielectric layer;
s4, providing a first supporting substrate, bonding the connecting pad to the first supporting substrate downwards, and thinning the semiconductor substrate to expose the TSV conductive columns second ends;
s5, forming a second dielectric layer on the second surface of the semiconductor substrate, and etching the second dielectric layer to expose the second end of the TSV conductive post;
s6, forming a bottom metal layer on the second dielectric layer, where the bottom metal layer completely covers the second dielectric layer and is electrically contacted with the second end of the TSV conductive pillar;
s7, forming a patterned mask layer on the bottom metal layer, forming a metal bump array electrically connected with the bottom metal layer, and removing the mask layer;
s8, providing a second supporting substrate, and bonding the metal bump array downward combination laser separation layer to the second supporting substrate;
s9, removing the first supporting substrate and exposing the connecting pad;
s10, providing a chip, and inversely mounting the chip on the connecting pad to be electrically connected with the connecting pad, wherein the projection of the chip on the bottom metal layer is completely positioned in the bottom metal layer;
s11, forming a plastic package material layer on the first dielectric layer, wherein the plastic package material layer wraps the chip and the first dielectric layer;
s12, removing the second supporting substrate to expose the metal bump array, and removing the exposed bottom metal layer.
Preferably, the formed TSV conductive pillars, the connection pads and the metal bumps are located on the same vertical line.
Preferably, the laser separation layer includes a LTHC layer to heat-peel the LTHC layer off the second support substrate based on laser light.
Preferably, the step of forming the TSV conductive pillars includes a step of preparing TSV holes by using one or a combination of laser drilling, mechanical drilling, deep reactive ion etching and photo-assisted electrochemical etching.
Preferably, the mask layer includes a dry film or a photoresist.
Preferably, the bottom metal layer comprises a diffusion barrier layer and/or a seed layer, wherein the diffusion barrier layer comprises one or a combination of Ti, TiN, Ta, TaN.
Preferably, a metal micro bump is arranged on the active surface of the chip, and is electrically contacted with the connecting pad through the metal micro bump.
Preferably, before the plastic package material layer is formed on the first dielectric layer, a step of filling underfill in a gap between the chip and the first dielectric layer is further included.
Preferably, the process of performing planarization treatment on the plastic packaging material layer is further included after the plastic packaging material layer is formed.
Preferably, the chips are one or a combination of bare chips and packaged chips, and the number of the chips is N, wherein N is more than or equal to 2.
As described above, the preparation method of the 2.5D package structure of the present invention has the following beneficial effects: the bottom metal layer under the metal bump array can isolate and remove the influence of laser irradiation on the packaging structure under the bottom metal layer, particularly the chip when the second supporting substrate is removed, so that the 2.5D packaging structure is protected to protect the chip, the success rate of reliability test of the 2.5D packaged chip is improved, and the yield of the 2.5D packaged chip is also improved; the bottom metal layer is easy to form and remove, the process for removing the bottom metal layer is placed, and finally, the 2.5D packaging structure can be protected, the packaging cost cannot be increased, and the process is simple and effective.
In addition, before the bottom metal layer is formed, the second surface of the semiconductor substrate is processed by methods such as chemical mechanical polishing, the flatness of the semiconductor substrate is improved, the bonding strength of a plurality of interfaces in subsequent packaging can be improved, the problems of layering, cracking and the like in the process are prevented, the contact resistance of the subsequent bottom metal layer and the TSV conductive columns is also reduced, and the reliability and the yield of the packaging structure are further improved; the TSV conductive columns, the connecting bonding pads and the metal bumps are located on the same vertical line, so that the resistance can be effectively reduced, and the signal delay can be effectively reduced.
Drawings
Fig. 1 is a flowchart illustrating a method for manufacturing a 2.5D package structure according to an embodiment of the present invention.
Fig. 2-7 are schematic structural diagrams of the steps shown in fig. 1.
Description of the element reference numerals
100 semiconductor substrate
110 TSV conductive post
120 first dielectric layer
130 connection pad
200 first support substrate
210 first separation layer
300 array of metal bumps
310 bottom metal layer
320 second dielectric layer
400 second support substrate
410 laser separation layer
500 chip
510 metal micro-bump
520 underfill
530 Plastic packaging Material layer
S1-S12 steps
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
In describing the embodiments of the present invention in detail, fig. 1-7 are partially enlarged and not drawn to scale, and the schematic diagrams are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Spatially relative terms, such as "under," "below," "lower," "below," "over," "upper," and the like, may be used herein for convenience in describing the relationship of one element or feature to another element or feature illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, the present invention provides a method for manufacturing a 2.5D package structure, which comprises the following steps:
s1, providing a semiconductor substrate 100, where the semiconductor substrate 100 includes a first surface and a second surface that are disposed opposite to each other, and forming a TSV conductive pillar 110 in the semiconductor substrate 100, where the TSV conductive pillar 110 includes a TSV conductive pillar 110 first end exposed at the first surface of the semiconductor substrate 100 and a TSV conductive pillar 110 second end located in the semiconductor substrate 100;
s2, forming a first dielectric layer 120 on the first surface of the semiconductor substrate 100, and etching the first dielectric layer 120 to expose the first end of the TSV conductive pillar 110;
s3, forming a connection pad 130 on the first dielectric layer 120, the connection pad being electrically connected to the first end of the TSV pillar 110;
s4, providing a first supporting substrate 200, bonding the connection pad 130 to the first supporting substrate 200 downward, and thinning the semiconductor substrate 100 to expose the TSV conductive pillar 110 second end;
s5, forming a second dielectric layer 320 on the second surface of the semiconductor substrate 100, and etching the second dielectric layer 320 to expose the second end of the TSV conductive pillar 110;
s6, forming a bottom metal layer 310 on the second dielectric layer 320, where the bottom metal layer 310 completely covers the second dielectric layer 320 and is electrically contacted to the second end of the TSV conductive pillar 110;
s7, forming a patterned mask layer (not shown) on the bottom metal layer 310, forming a metal bump array 300 electrically connected to the bottom metal layer 310, and removing the mask layer;
s8, providing a second supporting substrate 400, and bonding the metal bump array 300 to the second supporting substrate 400 by bonding the laser separation layer 410 downwards;
s9, removing the first supporting substrate 200 to expose the connection pads 130;
s10, providing a chip 500, and flip-chip mounting the chip 500 onto the connection pads 130 to electrically connect with the connection pads 130, wherein the projection of the chip 500 on the bottom metal layer 310 is completely located in the bottom metal layer 310;
s11, forming a plastic package material layer 530 on the first dielectric layer 120, where the plastic package material layer 530 covers the chip 500 and the first dielectric layer 120;
s12, removing the second supporting substrate 400 to expose the metal bump array 300, and removing the exposed bottom metal layer 310.
As shown in step S1 in fig. 1 and fig. 2, a semiconductor substrate 100 is provided, where the semiconductor substrate 100 includes a first surface and a second surface that are opposite to each other, TSV holes are formed from the first surface of the semiconductor substrate 100 into the semiconductor substrate 100, and conductive materials are filled in the TSV holes to form TSV conductive pillars 110; the TSV conductive pillars 110 include a first end of the TSV conductive pillar 110 and a second end of the TSV conductive pillar 110, the first end of the TSV conductive pillar 110 is exposed on the first surface of the semiconductor substrate 100, and the second end of the TSV conductive pillar 110 is located in the semiconductor substrate 100.
Specifically, the semiconductor substrate 100 includes but is not limited to a silicon substrate, a silicon germanium substrate, a gallium nitride substrate, or other semiconductor substrates, and the shape thereof is any structure including a circle, an ellipse, a polygon, or the like, which is not particularly limited herein and is specifically selected according to the need; forming a TSV hole on the first surface of the semiconductor substrate 100, wherein the method for forming the TSV hole includes one or a combination of laser drilling, mechanical drilling, deep reactive ion etching, and photo-assisted electrochemical etching; filling a conductive material in the TSV hole to form a TSV conductive pillar 110, wherein the conductive material is one or a combination of copper, aluminum, gold, silver, nickel, titanium, tantalum, and the like, the filling method is any one or a combination of electroplating, chemical plating, silk-screen printing, and wire bonding, and meanwhile, in order to prevent the conductive material from diffusing to the semiconductor substrate and increase the adhesion strength between the conductive material and the semiconductor substrate, a layer of one or a combination of Ta, TaN, Ti, and TiN is deposited as a diffusion barrier layer or an adhesion layer.
As shown in step S2 in fig. 1 and fig. 3, a first dielectric layer 120 is formed on the first surface of the semiconductor substrate 100, and the first dielectric layer 120 is etched to expose the first end of the TSV conductive pillar 110.
Specifically, the first dielectric layer 120 includes epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, fluorine-containing glass, and the like, in this embodiment, the first dielectric layer 120 is PI, and the first dielectric layer 120 is etched to expose the first end of the TSV conductive pillar 110 at the opening of the first dielectric layer 120.
As shown in step S3 in fig. 1 and fig. 3, a connection pad 130 electrically connected to the first end of the TSV conductive pillar 110 is formed on the first dielectric layer 120.
Specifically, a metal layer is deposited on the first dielectric layer 120 by electroplating, physical vapor deposition or chemical vapor deposition, and the like, the metal layer may be one or a combination of copper, aluminum, gold, silver, nickel, titanium, tantalum, and the like, and the metal layer is etched to form a connection pad 130, and the connection pad 130 is vertically located above the first end of the TSV conductive pillar 110 and electrically connected to the first end of the TSV conductive pillar 110. The connection pad in this embodiment is manufactured by a process of electroplating copper, nickel, and gold.
As shown in step S4 in fig. 1 and fig. 3, a first supporting substrate 200 is provided, the connection pad 130 is bonded to the first supporting substrate 200 downward, and the semiconductor substrate 100 is thinned to expose the second end of the TSV conductive pillar 110.
Specifically, the connection pad 130 is bonded to the first support substrate 200 through a first separation layer 210 in a downward direction, the first support substrate 200 may be one of a glass substrate, a ceramic substrate, a polymer substrate, and a metal substrate, the first support substrate 200 provides a support plane for a subsequent packaging structure to prevent the semiconductor chip from cracking, breaking, and warping in a subsequent manufacturing process, and the support plane needs to be removed in a later stage.
The first separation layer 210 is required to bond and fix the connection pad 130 to the first support substrate 200, so the first separation layer 210 must have a certain adhesion to the connection pad 130, and for peeling, the adhesion between the first separation layer 210 and the connection pad 130 is generally smaller than the adhesion between the first separation layer 210 and the first support substrate 200. The first separation layer 210 includes a polymer layer or an adhesive layer, and the polymer layer or the adhesive layer is coated on the surface of the first support substrate 200 by a spin coating process, and then cured by a curing process to bond the connection pad 130 to the first support substrate 200 in a downward direction. In this embodiment, the polymer layer is an LTHC light-to-heat conversion layer, and the first separation layer 210 may be peeled off by heating the LTHC light-to-heat conversion layer using a laser to separate the connection pad 130 and the first support substrate 200 from each other.
The semiconductor substrate 100 is turned over so that the second surface of the semiconductor substrate 100 faces upwards, then the semiconductor substrate 100 is thinned by adopting methods such as chemical mechanical polishing and the like to expose the second end of the TSV conductive post 110, the second surface has good flatness after being processed by methods such as chemical mechanical polishing and the like, the bonding strength of a plurality of interfaces in subsequent packaging can be improved, the problems of layering, cracking and the like in the process are prevented, the contact resistance between the subsequent bottom metal layer 310 and the TSV conductive post 110 is also reduced, and the reliability and the yield of the packaging structure are improved.
As shown in step S5 in fig. 1 and fig. 4, a second dielectric layer 320 is formed on the second surface of the semiconductor substrate 100, and the second dielectric layer 320 is etched to expose the second end of the TSV conductive pillar 110.
Specifically, the second dielectric layer 320 includes one or a combination of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, in this embodiment, the second dielectric layer 320 is PI, and the second dielectric layer 320 is etched to expose the second end of the TSV conductive pillar 110 at the opening of the second dielectric layer 320.
As shown in step S6 in fig. 1 and fig. 4, a bottom metal layer 310 is formed on the second dielectric layer 320, and the bottom metal layer 310 completely covers the second dielectric layer 320 and is electrically contacted to the second end of the TSV conductive pillar 110.
In detail, the bottom metal layer 310 is located on the surface of the second dielectric layer 320 and on the sidewall of the opening, and is in vertical electrical contact with the second end of the TSV pillar 110 at the bottom of the opening of the second dielectric layer 320, wherein the forming method of the bottom metal layer 310 includes a physical vapor deposition or a sputtering method.
As an example, the bottom metal layer 310 includes a diffusion barrier layer and/or a seed layer, wherein the diffusion barrier layer includes one or a combination of Ti, TiN, Ta, TaN. In detail, the diffusion barrier layer is also called an adhesion layer, which can not only prevent the seed layer from diffusing to the second dielectric layer 320, but also can increase the adhesion between the seed layer and the second dielectric layer, and the diffusion barrier layer comprises one or a combination of Ti, TiN, Ta and TaN; the seed layer is formed on the diffusion barrier layer, is generally a Cu seed layer, and can also be formed by Cu alloy, wherein the Cu alloy comprises one or a combination of gold, silver, nickel, tin and chromium. In this embodiment, the diffusion barrier layer is a Ti layer and the seed layer is a Cu seed layer.
As shown in step S7 in fig. 1 and fig. 5, a patterned mask layer (not shown) is formed on the bottom metal layer 310, and a metal bump array 300 electrically connected to the bottom metal layer 310 is formed, and the mask layer is removed.
As an example, the mask layer includes a dry film or a photoresist; forming a patterned mask layer on the bottom metal layer 310 after coating, exposing and developing the dry film or the photoresist, wherein an opening of the mask layer is correspondingly arranged vertically above the second end of the TSV conductive post 110, and a metallization layer and a welding layer are deposited in the opening of the mask layer by using methods such as electroplating and chemical plating, and are in vertical electrical contact with the bottom metal layer 310; removing the mask layer by etching, such as wet etching, dry etching or the like, forming a bump array on the solder layer by using a C4 soldering method, wherein the metallization layer, the solder layer and the bump array together form a metal bump array 300, the metal bump array 300 extends over the entire surface of the semiconductor substrate 100, and the metal bump array 300 is vertically and electrically connected to the second end of the TSV conductive pillar 110 through the bottom metal layer 310.
As an example, the TSV conductive pillars 110, the connection pads 130, and the metal bumps are formed on the same vertical line.
Specifically, the connection pad 130 is vertically located above the first end of the TSV conductive pillar 110 and is electrically connected to the first end of the TSV conductive pillar 110, and the metal bump array is vertically electrically connected to the second end of the TSV conductive pillar 110 through the bottom metal layer 310, so that the formed TSV conductive pillar 110, the connection pad 130 and the metal bump are located on the same vertical line, the resistance among the TSV conductive pillar 110, the connection pad 130 and the metal bump is reduced, and the signal delay among the TSV conductive pillar 110, the connection pad 130 and the metal bump is also reduced.
As shown in S8 of fig. 1 and fig. 6, a second supporting substrate 400 is provided, and the metal bump array 300 is bonded to the second supporting substrate 400 by bonding the laser separation layer 410 downward. The second supporting substrate 400 also serves to provide a supporting plane for a subsequent packaging structure to prevent the semiconductor chip from cracking, breaking, warping and the like in a subsequent manufacturing process, and needs to be removed later, so the second supporting substrate 400 can refer to the first supporting substrate, which will not be described in detail herein.
As an example, the laser separation layer 410 includes a LTHC layer to be thermally peeled off the second support substrate 400 based on laser. The LTHC layer, also called a light-to-heat conversion layer, is irradiated with laser light, so that the LTHC layer absorbs the light to generate heat and reduce viscosity, and the metal bump array 300 and the second supporting substrate 400 are separated from the laser separation layer 410, thereby facilitating the peeling of the second supporting substrate 400.
As shown in step S9 in fig. 1 and fig. 6, the first supporting substrate 200 is removed to expose the connection pads 130; in the embodiment, the first separation layer 210 is a LTHC light-to-heat conversion layer, and the LTHC light-to-heat conversion layer is heated by laser to reduce the viscosity of the LTHC light-to-heat conversion layer, so that the connection pad 130 and the first support substrate 200 are separated from the first separation layer 210, and the connection pad 130 is exposed.
As shown in step S10 in fig. 1 and fig. 6, a chip 500 is provided, and the chip 500 is flip-chip mounted on the connection pads 130 to be electrically connected to the connection pads 130, and the projection of the chip 500 on the bottom metal layer 310 is completely located in the bottom metal layer 310.
Specifically, the chip 500 includes one or a combination of a bare chip and a packaged chip, and is specifically configured according to actual needs, and is not particularly limited herein. In the present embodiment, the number of the chips 500 is shown as 3, but the number of the chips 500 is not limited thereto, and the number of the chips 500 may be greater than or equal to 2, such as 2, 4, 5, and so on, according to the requirement.
As an example, the chip 500 is provided with a metal micro bump on the active surface, and the bonding micro bump is electrically contacted with the connection pad 130.
Specifically, a micro solder bump is disposed on an active surface of the chip 500, the micro solder bump is electrically connected to an internal circuit of the chip 500, and electrically connected to the connection pad 130 through the micro solder bump, the chip 500 is flip-mounted on the first surface of the semiconductor substrate 100, the chip 500 may be arranged on the first surface of the semiconductor substrate 100 in parallel at intervals or in staggered intervals, and is specifically disposed as required, but in order to protect the chip 500 from laser radiation when the second support substrate 400 is peeled off, a projection of the chip 500 on the bottom metal layer 310 is completely located in the bottom metal layer 310, so that the bottom metal layer 310 can effectively isolate laser radiation and cannot affect the chip 500, thereby protecting the chip from a 2.5D package structure, the success rate of the reliability test of the 2.5D packaged chip is improved, and the yield of the 2.5D packaged chip is also improved.
As shown in step S11 in fig. 1 and fig. 6, a plastic package material layer 530 is formed on the first dielectric layer 120, and the plastic package material layer 530 covers the chip 500 and the first dielectric layer 120.
For example, before forming the molding compound layer 530 on the first dielectric layer 120, a step of filling a gap between the chip 500 and the first dielectric layer 120 with an underfill 520 is further included.
Specifically, in order to reinforce the connection between the chip 500 and the semiconductor substrate 100 and enhance the drop-resistant performance of the package structure, in this embodiment, a capillary underfill method is used to fill the gap between the chip 500 and the semiconductor substrate 100 with the underfill 520. The capillary underfill method uses capillary action to make the glue flow rapidly through the bottom of the bottom chip 600, and the minimum space for capillary flow is 10 μm. The method also meets the requirement of the lowest electrical property between the bonding pad and the soldering tin ball in the welding process, the glue can not flow through the gap of less than 4 mu m, so the electrical safety property of the welding process is ensured, and the bottom gap is filled in a large area by utilizing a heating curing mode, so the anti-falling performance of the packaging structure is enhanced.
The plastic package material layer 530 formed on the first dielectric layer 120 includes, but is not limited to, a polyimide layer, a silicone layer, and an epoxy resin layer, and the method for forming the plastic package material layer 530 includes one of compression molding, transfer molding, liquid seal molding, mold underfill, capillary underfill, vacuum lamination, and spin coating. In order to simplify the process, in this embodiment, the plastic package material layer 530 also adopts a capillary underfill method, and the chip 500 and the first dielectric layer 120 are covered by the plastic package material layer 530.
As an example, the process of planarizing the molding compound layer 530 is further included after the molding compound layer 530 is formed.
Specifically, in order to improve the roughness on the surface of the plastic packaging material layer 530, the thickness of the 2.5D packaging structure is controlled, and the plastic packaging material layer 530 is subjected to planarization and thinning, the plastic packaging material layer 530 is also improved at the same time the flatness on the surface of the plastic packaging material layer 530 facilitates further processing of the subsequent 2.5D packaging structure. Methods of planarization include mechanical polishing, chemical mechanical polishing, and the like.
As shown in step S12 in fig. 1 and fig. 7, the second supporting substrate 400 is removed to expose the metal bump array 300, and the exposed bottom metal layer 310 is removed.
Specifically, the second supporting substrate 400 is removed by the same or similar method as the first supporting substrate 200, and will not be described in detail here. The exposed bottom metal layer can be removed by dry etching or wet etching, but wet etching is widely used because the cost is low and etching residues do not need to be cleaned. In the embodiment, the Ti/Cu of the bottom metal layer is removed by wet etching; for etching the Cu crystal layer, the etching liquid is H 2 O 2 、H 3 PO4 throughThe Cu-Cu; after the etching of the Cu crystal layer is finished, the 2.5D packaging structure is sent to a Ti etching layer, and the etching liquid of Ti is changed from H 2 O 2 KOH is mixed by a certain proportion, and is evenly sprayed on the surface of the bottom metal layer 310 by etching equipment to complete the etching of Ti, and then DI water is used for washing and pure N is used for washing 2 Drying is performed to complete the entire etching process. Because the etching process of the bottom metal layer 310 is located after the second supporting substrate 400 is removed, the bottom metal layer 310 can isolate the influence of laser irradiation on the packaging structure below the bottom metal layer 310, particularly the chip 500, when the second supporting substrate 400 is removed, so that the 2.5D packaging structure is protected to protect the chip, the success rate of reliability test of the 2.5D packaged chip is improved, and the yield of the 2.5D packaged chip is also improved; the bottom metal layer 310 is easy to form and remove, the process of removing the bottom metal layer 310 is placed finally, the 2.5D packaging structure can be protected, the packaging cost cannot be increased, and the process is simple and effective.
In summary, the preparation method of the 2.5D package structure of the present invention has the following beneficial effects: the bottom metal layer under the metal bump array can isolate and remove the influence of laser irradiation on the packaging structure under the bottom metal layer, particularly the chip when the second supporting substrate is removed, so that the 2.5D packaging structure is protected to protect the chip, the success rate of reliability test of the 2.5D packaged chip is improved, and the yield of the 2.5D packaged chip is also improved; the bottom metal layer is easy to form and remove, the process for removing the bottom metal layer is placed, and finally, the 2.5D packaging structure can be protected, the packaging cost cannot be increased, and the process is simple and effective.
In addition, before the bottom metal layer is formed, the second surface of the semiconductor substrate is processed by methods such as chemical mechanical polishing, the flatness of the semiconductor substrate is improved, the bonding strength of a plurality of interfaces in subsequent packaging can be improved, the problems of layering, cracking and the like in the process are prevented, the contact resistance of the subsequent bottom metal layer and the TSV conductive columns is also reduced, and the reliability and the yield of the packaging structure are further improved; the TSV conductive columns, the connecting bonding pads and the metal bumps are located on the same vertical line, so that the resistance can be effectively reduced, and the signal delay can be effectively reduced.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A preparation method of a 2.5D packaging structure is characterized by comprising the following steps:
s1, providing a semiconductor substrate, where the semiconductor substrate includes a first surface and a second surface that are disposed opposite to each other, and forming a TSV conductive pillar in the semiconductor substrate, where the TSV conductive pillar includes a TSV conductive pillar first end exposed at the first surface of the semiconductor substrate and a TSV conductive pillar second end located in the semiconductor substrate;
s2, forming a first dielectric layer on the first surface of the semiconductor substrate, and etching the first dielectric layer to expose the first end of the TSV conductive post;
s3, forming a connecting pad electrically connected with the first end of the TSV conductive column on the first dielectric layer;
s4, providing a first supporting substrate, bonding the connection pad to the first supporting substrate downward, and thinning the semiconductor substrate to expose the TSV conductive pillar second end;
s5, forming a second dielectric layer on the second surface of the semiconductor substrate, and etching the second dielectric layer to expose the second end of the TSV conductive post;
s6, forming a bottom metal layer on the second dielectric layer, where the bottom metal layer completely covers the second dielectric layer and is electrically contacted with the second end of the TSV conductive pillar;
s7, forming a patterned mask layer on the bottom metal layer, forming a metal bump array electrically connected with the bottom metal layer, and removing the mask layer;
s8, providing a second supporting substrate, and bonding the metal bump array downward combination laser separation layer to the second supporting substrate;
s9, removing the first supporting substrate and exposing the connecting pad;
s10, providing a chip, and reversely mounting the chip on the connecting pad so as to be electrically connected with the connecting pad, wherein the projection of the chip on the bottom metal layer is completely positioned in the bottom metal layer;
s11, forming a plastic packaging material layer on the first medium layer, wherein the plastic packaging material layer wraps the chip and the first medium layer;
s12, removing the second supporting substrate to expose the metal bump array, and removing the exposed bottom metal layer.
2. The method for manufacturing a 2.5D package structure according to claim 1, wherein: the formed TSV conductive columns, the connecting bonding pads and the metal bumps are located on the same vertical line.
3. The method for manufacturing a 2.5D package structure according to claim 1, wherein: the laser separation layer includes a LTHC layer to heat the LTHC layer based on laser light to peel off the second support substrate.
4. The method for manufacturing a 2.5D package structure according to claim 1, wherein: the TSV conductive column forming step comprises the step of preparing TSV holes by adopting one or a combination of laser drilling, mechanical drilling, deep reactive ion etching and photo-assisted electrochemical etching.
5. The method for manufacturing a 2.5D package structure according to claim 1, wherein: the mask layer includes a dry film or a photoresist.
6. The method for manufacturing a 2.5D package structure according to claim 1, wherein: the bottom metal layer includes a diffusion barrier layer and/or a seed layer, wherein the diffusion barrier layer includes one or a combination of Ti, TiN, Ta, TaN.
7. The method for manufacturing a 2.5D package structure according to claim 1, wherein: and a metal micro-bump is arranged on the active surface of the chip and electrically contacted with the connecting bonding pad through the metal micro-bump.
8. The method for manufacturing a 2.5D package structure according to claim 1, wherein: and before the plastic package material layer is formed on the first medium layer, filling bottom filling glue into a gap between the chip and the first medium layer.
9. The method for manufacturing a 2.5D package structure according to claim 1, wherein: and forming the plastic packaging material layer and then carrying out planarization treatment on the plastic packaging material layer.
10. The method for manufacturing a 2.5D package structure according to claim 1, wherein: the chips are one or a combination of bare chips or packaged chips, and the number of the chips is N, wherein N is more than or equal to 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210441937.7A CN114975242B (en) | 2022-04-25 | 2022-04-25 | Preparation method of 2.5D packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210441937.7A CN114975242B (en) | 2022-04-25 | 2022-04-25 | Preparation method of 2.5D packaging structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114975242A true CN114975242A (en) | 2022-08-30 |
| CN114975242B CN114975242B (en) | 2023-06-27 |
Family
ID=82979642
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210441937.7A Active CN114975242B (en) | 2022-04-25 | 2022-04-25 | Preparation method of 2.5D packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114975242B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116613154A (en) * | 2023-07-20 | 2023-08-18 | 盛合晶微半导体(江阴)有限公司 | 2.5D packaging structure for improving power signal transmission and preparation method thereof |
| CN118448395A (en) * | 2024-07-08 | 2024-08-06 | 甬矽半导体(宁波)有限公司 | 2.5DHBM packaging structure and 2.5DHBM packaging method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014222728A (en) * | 2013-05-14 | 2014-11-27 | 凸版印刷株式会社 | Semiconductor package |
| CN110957284A (en) * | 2019-12-04 | 2020-04-03 | 中芯长电半导体（江阴）有限公司 | Three-dimensional packaging structure of chip and packaging method thereof |
| US20210091064A1 (en) * | 2019-09-23 | 2021-03-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and method of fabricating the same |
| CN113497008A (en) * | 2020-04-02 | 2021-10-12 | 盛合晶微半导体(江阴)有限公司 | Semiconductor packaging structure and preparation method thereof |
-
2022
- 2022-04-25 CN CN202210441937.7A patent/CN114975242B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014222728A (en) * | 2013-05-14 | 2014-11-27 | 凸版印刷株式会社 | Semiconductor package |
| US20210091064A1 (en) * | 2019-09-23 | 2021-03-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and method of fabricating the same |
| CN110957284A (en) * | 2019-12-04 | 2020-04-03 | 中芯长电半导体（江阴）有限公司 | Three-dimensional packaging structure of chip and packaging method thereof |
| CN113497008A (en) * | 2020-04-02 | 2021-10-12 | 盛合晶微半导体(江阴)有限公司 | Semiconductor packaging structure and preparation method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116613154A (en) * | 2023-07-20 | 2023-08-18 | 盛合晶微半导体(江阴)有限公司 | 2.5D packaging structure for improving power signal transmission and preparation method thereof |
| CN116613154B (en) * | 2023-07-20 | 2023-09-19 | 盛合晶微半导体(江阴)有限公司 | 2.5D packaging structure for improving power signal transmission and preparation method thereof |
| CN118448395A (en) * | 2024-07-08 | 2024-08-06 | 甬矽半导体(宁波)有限公司 | 2.5DHBM packaging structure and 2.5DHBM packaging method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114975242B (en) | 2023-06-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10861809B2 (en) | Semiconductor structure and method of forming | |
| US11056471B2 (en) | Semiconductor device and method of manufacture | |
| US11855018B2 (en) | Semiconductor device and method of manufacture | |
| US10103132B2 (en) | Semiconductor device and method of manufactures | |
| CN114975242B (en) | Preparation method of 2.5D packaging structure | |
| TW200903763A (en) | Inter-connecting structure for semiconductor device package and method of the same | |
| US10586763B2 (en) | Semiconductor device and method of manufacture | |
| KR20210122642A (en) | Chip-on-wafer structure with chiplet interposer | |
| US20210175210A1 (en) | Three-Dimensional Chip Packaging Structure And Method Thereof | |
| CN109727934B (en) | Packaging structure and preparation method thereof | |
| TWI713858B (en) | Integrated circuit package and method of forming same | |
| US11973070B2 (en) | Double-layer stacked 3D fan-out packaging structure and method making the same | |
| CN114695272A (en) | Method for forming integrated circuit package | |
| CN112466829A (en) | Chip packaging structure and preparation method thereof | |
| CN221041117U (en) | Package structure | |
| US20230057113A1 (en) | Semiconductor device, package structure and method of fabricating the same | |
| CN213546309U (en) | Chip packaging structure | |
| US12113045B2 (en) | Three-dimensional stacked fan-out packaging structure and method making the same | |
| US12027494B2 (en) | Semiconductor device and manufacturing method thereof | |
| US11205615B2 (en) | Semiconductor device and method of manufacture | |
| US11798888B2 (en) | Chip packaging structure and method for preparing same | |
| CN117690863A (en) | Preparation method of 2.5D packaging structure | |
| CN116960070A (en) | 3D fan-out type packaging structure and preparation method | |
| TW202431558A (en) | Electronic package, electronic structure and manufacturing method thereof | |
| TW202431567A (en) | Electronic package, electronic structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |