CN215988753U - Wafer level chip packaging structure - Google Patents
Wafer level chip packaging structure Download PDFInfo
- Publication number
- CN215988753U CN215988753U CN202122553602.8U CN202122553602U CN215988753U CN 215988753 U CN215988753 U CN 215988753U CN 202122553602 U CN202122553602 U CN 202122553602U CN 215988753 U CN215988753 U CN 215988753U
- Authority
- CN
- China
- Prior art keywords
- layer
- wafer
- chip
- level chip
- package structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The utility model provides a wafer-level chip packaging structure, which comprises a rewiring layer, a first welding ball, a chip, an SMT (surface mount technology) element and a plastic packaging layer, wherein the rewiring layer is arranged on the chip; the rewiring layer comprises a dielectric layer and a metal bump; the first solder ball is positioned on the first surface of the rewiring layer and is electrically connected with the metal bump; the plastic packaging layer is positioned on the second surface of the rewiring layer; the chip and the SMT element are arranged in the plastic package layer at intervals and are electrically connected with the metal bumps. According to the utility model, the external chip and the SMT element are coated in the plastic package layer, and the plastic package layer replaces a traditional bottom filling layer to be applied to wafer-level advanced integrated package, so that the number of packaged device structure layers is reduced, the plastic package requirements of different components can be met simultaneously, the packaging process of the device can be simplified, the packaging cost of the device is reduced, the bonding surfaces of different materials in the chip are reduced, the electric heating performance and the transmission performance of the device are improved, the risk of failure of the device is reduced, and the reliability of the device is improved.
Description
Technical Field
The utility model relates to the technical field of semiconductor manufacturing, in particular to the field of back-end packaging, and particularly relates to a wafer-level chip packaging structure.
Background
With the rapid development of integrated circuit technology, the integration degree of devices is increasing and the line width is shrinking, which brings more and more challenges to chip packaging. In the existing wafer-level chip packaging technology, after an electrical lead-out structure is prepared on a wafer-level chip, an external chip is electrically connected to the wafer-level chip, and then the external chip is wrapped by a capillary Underfill technology (Underfill), that is, the external chip is located in a capillary fill layer at the bottom of the wafer-level chip. The preparation process is complex, the packaging cost is increased, and the size of the packaged device is large and the heat dissipation performance of the device is poor due to the existence of the underfill layer.
SUMMERY OF THE UTILITY MODEL
In view of the above drawbacks of the prior art, an object of the present invention is to provide a wafer level chip package structure, which is used to solve the problems in the existing wafer level chip package technology that an external chip is disposed in a capillary filling layer at the bottom of a wafer level chip, the size of a packaged device is large and the heat dissipation performance of the device is not good due to the existence of the filling layer, and the device preparation process is complicated and the device preparation cost is high due to the increase of a structure layer.
In order to achieve the above and other related objects, the present invention provides a wafer level chip package structure, which includes a redistribution layer, a first solder ball, a chip, an SMT component, and a molding layer; the rewiring layer is provided with a first surface and a second surface which are opposite to each other, and comprises a dielectric layer and a metal bump; the first solder balls are positioned on the first surface of the rewiring layer and are electrically connected with the metal bumps; the plastic packaging layer is positioned on the second surface of the rewiring layer; the chip and the SMT element are arranged in the plastic package layer at intervals and are electrically connected with the metal lug.
Optionally, an opening is formed in the dielectric layer, the metal bump is exposed from the opening, a second solder ball is disposed on the chip, the second solder ball is located in the opening, and the chip is flip-chip bonded to the metal bump through the second solder ball.
More optionally, the upper opening size of the aperture is larger than the lower opening size.
Optionally, the number of the second solder balls and the number of the first solder balls are two or more.
Optionally, the first solder ball and the second solder ball include any one of a copper ball, a gold ball, a solder ball, and an alloy ball.
Optionally, the first solder balls and the second solder balls correspond to each other one by one.
Optionally, the molding layer includes one of a polyimide layer, a silicone layer, and an epoxy layer.
Optionally, the metal bump includes any one of a gold block, a silver block, a nickel block, a titanium block, a copper block, and an aluminum block.
Optionally, the SMT component comprises an active component and/or a passive component.
Optionally, the SMT component includes one or more of a resistor, an inductor, and a capacitor.
As described above, the wafer level chip package structure of the present invention has the following advantages: according to the utility model, the external chip and the SMT element are coated in the plastic package layer, and the MUF (molded Underfill) layer replaces the traditional Underfill layer to be applied to wafer level (wafer level) advanced integrated package, so that the number of packaged device structure layers is reduced, the plastic package requirements of different components can be met, the package process of the devices can be simplified, the package cost of the devices can be reduced, different material joint surfaces in the chip can be reduced, the electric heating performance and the transmission performance of the devices can be improved, the risk of device failure can be reduced, and the reliability of the devices can be improved. In addition, the utility model adopts the metal bump (bump) to interconnect the wafer level chips, thereby ensuring good conduction of the upper layer and the lower layer.
Drawings
Fig. 1 is a schematic cross-sectional view illustrating a wafer-level chip package structure according to an exemplary embodiment of the utility model.
Fig. 2-11 are schematic cross-sectional views of the wafer-level chip package structure of fig. 1 at various steps during the fabrication process.
Description of the element reference numerals
11 dielectric layer
12 metal bump
13 first solder ball
14 chips
15 SMT component
16 plastic packaging layer
17 second solder ball
18 vector
19 separating layer
20 temporary substrate
21 cutting table
22 open pores
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The utility model is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated. In order to keep the drawings as concise as possible, not all features of a single figure may be labeled in their entirety.
As shown in fig. 1, the present invention provides a wafer level chip 14 package structure, which includes a redistribution layer, first solder balls 13, a chip 14, an SMT component 15 and a molding layer 16; the rewiring layer is provided with a first surface and a second surface which are opposite to each other, and comprises a dielectric layer 11 and a metal bump 12; the first solder balls 13 are located on the first surface of the redistribution layer and are electrically connected to the metal bumps 12; the plastic sealing layer 16 is positioned on the second surface of the rewiring layer; the chip 14 and the SMT component 15 are disposed in the molding layer 16 at intervals, and are electrically connected to the metal bump 12. According to the utility model, the external chip and the SMT element are coated in the plastic package layer, and the MUF (molded Underfill) layer replaces the traditional Underfill layer to be applied to wafer level (wafer level) advanced integrated package, so that the number of packaged device structure layers is reduced, the plastic package requirements of different components can be met, the package process of the devices can be simplified, the package cost of the devices can be reduced, different material joint surfaces in the chip can be reduced, the electric heating performance and the transmission performance of the devices can be improved, the risk of device failure can be reduced, and the reliability of the devices can be improved. In addition, the utility model adopts the metal bump (bump) to interconnect the wafer level chips, thereby ensuring good conduction of the upper layer and the lower layer.
In an example, an opening is formed in the dielectric layer 11, the opening exposes the metal bump 12, a second solder ball 17 is disposed on the chip 14, the second solder ball 17 is located in the opening, and the chip 14 is flip-chip bonded to the metal bump 12 through the second solder ball 17. Such a structural arrangement helps to improve the reliability of the electrical connection between the chip 14 and the metal bump 12. In a further example, the upper opening size of the opening is larger than the lower opening size so that the second solder ball 17 can be stably disposed in the opening.
The second solder balls 17 and the first solder balls 13 may be single, but preferably, two or more of them are used to ensure electrical connection. The first solder balls 13 and the second solder balls 17 include, but are not limited to, any one of copper balls, gold balls, solder balls, and alloy balls. The first solder balls 13 and the second solder balls 17 preferably correspond to each other one on top of the other to ensure electrical connection.
By way of example, the molding layer 16 includes, but is not limited to, one of a polyimide layer, a silicone layer, and an epoxy layer.
The metal bump 12 includes, but is not limited to, any one of gold, silver, nickel, titanium, copper, and aluminum, by way of example.
By way of example, the SMT components 15 may be active components and/or passive components. For example, the SMT component 15 may include one or more of a resistor, an inductor, and a capacitor.
To make the technical solution and advantages of the present invention more prominent, the following exemplary process for manufacturing the wafer level chip 14 package structure of the present invention includes the following steps:
providing a carrier 18, forming the redistribution layer on the carrier 18; the carrier 18 may be a single-layer or multi-layer structure, and specifically refer to fig. 2, in order to facilitate peeling of a subsequent structure, as an example, after the carrier 18 is provided, a separation layer 19 may be formed on the surface of the carrier 18 by a coating process, including but not limited to, and the resulting structure is shown in fig. 3; forming the redistribution layer on the separation layer 19, where the redistribution layer includes the dielectric layer 11 and a plurality of metal bumps 12 located on the surface of the dielectric layer 11 and distributed at intervals, and a structure obtained in this step is as shown in fig. 4;
forming a first solder ball 13 on the ball mount on the redistribution layer, wherein the first solder ball 13 is electrically connected to the metal bump 12, and the structure obtained after the step is shown in fig. 5;
peeling the carrier 18 and transferring the structure obtained after peeling the carrier 18 to a temporary substrate 20 to reveal the rewiring layer, the structure obtained by this step being shown in fig. 6; for example, in the case where the separation layer 19 of the UV resin material is formed in advance, laser irradiation may be performed from the back surface (surface on which other structures are not formed) of the carrier 18 to peel off the carrier 18;
forming an opening 22 in the dielectric layer 11 by using a process including, but not limited to, laser etching to expose the metal bump 12, obtaining the structure shown in fig. 7, then mounting the SMT component 15 on the metal bump 12 (refer to fig. 8), and flip-chip bonding the chip 14 to the metal bump 12 through the opening 22 (refer to fig. 9);
forming a molding layer 16, wherein the molding layer 16 encapsulates the chip 14 and the SMT component 15, as shown in fig. 10;
the temporary substrate 20 is removed, and the structure shown in fig. 1 is finally obtained.
Since a plurality of functional chips are formed on the wafer at the same time, the structure packaged by the above steps has a plurality of independent devices, and therefore, the structure shown in fig. 1 is generally transferred to a cutting table 21 for cutting, so as to obtain the individual devices.
As an example, the redistribution layer is formed by forming a dielectric layer 11 on the carrier 18 by using a vapor deposition process, and then forming a metal material layer on the surface of the dielectric layer 11 by using one or more methods, including but not limited to sputtering, electroplating, chemical plating, and the like, and then performing photolithography etching on the metal material layer to form a plurality of independent metal bumps 12. The material of the dielectric layer 11 includes but is not limited to one or a combination of more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass, and can also be other high-K dielectric materials; the metal bump 12 includes any one of a gold block, a silver block, a nickel block, a titanium block, a copper block, and an aluminum block (preferably a copper layer). The dielectric layer 11 and the metal bumps 12 may be of a single-layer or multi-layer structure, but it is necessary to ensure that the metal bumps 12 of different layers are electrically connected to each other.
The carrier 18 mainly plays a supporting role, and avoids the defects of bending deformation and the like in the device preparation process. By way of example, the carrier 18 includes, but is not limited to, a glass, a silicon substrate, a sapphire substrate, a ceramic substrate, a metal substrate, and the like, which have a certain hardness and are not easily bent. In this embodiment, a transparent substrate such as a glass substrate is preferable, which facilitates that UV light irradiation can be performed from the back surface of the carrier 18 to peel the carrier 18 from the separation layer 19 later when the separation layer 19 is peeled. The carrier 18 may be washed and dried before the separation layer 19 is prepared.
The separation layer 19 may be a single layer or a multi-layer structure, and may include, for example, a release layer and a protective layer on the surface of the release layer. Specifically, the release layer includes, but is not limited to, a combination of one or more of a carbon material layer, a resin material layer, and an organic material layer, and the protective layer includes, but is not limited to, a polyimide layer. For example, the carrier 18 is a transparent substrate such as glass, and the separation layer 1912 is a UV resin layer, and the separation layer 19 is irradiated from the back surface of the carrier 18 to be peeled off at the time of subsequent peeling, whereby peeling is performed. The separation layer 19 may also be an LTHC light-to-heat conversion layer, and the subsequent step may be heating the LTHC light-to-heat conversion layer based on a method such as laser, so as to separate the carrier 18 from the LTHC light-to-heat conversion layer, thereby reducing the difficulty of the stripping process and preventing the device from being damaged. The method for forming the separation layer 19 may be determined depending on the material thereof, and may be one or more selected from spin coating, spray coating, direct attachment, and the like.
The temporary substrate 20 may be made of the same material as the carrier 18, and includes, but is not limited to, a substrate that has a certain hardness and is not easily bent and deformed, such as a glass substrate, a silicon substrate, a sapphire substrate, a ceramic substrate, a metal substrate, etc., and a separation material layer may also be formed on the surface of the substrate to facilitate subsequent peeling.
By way of example, the molding layer 16 may be formed by one or more of compression molding, transfer molding, liquid sealing, vacuum lamination, spin coating, and the like, and the material of the molding layer 16 may include one or more of polyimide, silicone, and epoxy.
In summary, the present invention provides a wafer level chip package structure, which includes a redistribution layer, a first solder ball, a chip, an SMT component, and a molding layer; the rewiring layer is provided with a first surface and a second surface which are opposite to each other, and comprises a dielectric layer and a metal bump; the first solder balls are positioned on the first surface of the rewiring layer and are electrically connected with the metal bumps; the plastic packaging layer is positioned on the second surface of the rewiring layer; the chip and the SMT element are arranged in the plastic package layer at intervals and are electrically connected with the metal lug. According to the utility model, the external chip and the SMT element are coated in the plastic package layer, and the MUF layer replaces the traditional Underfill layer to be applied to wafer-level advanced integrated package, so that the number of packaged device structure layers is reduced, the plastic package requirements of different components can be met simultaneously, the packaging process of the devices can be simplified, the packaging cost of the devices is reduced, the bonding surfaces of different materials in the chip are reduced, the electric heating performance and the transmission performance of the devices are improved, the risk of failure of the devices is reduced, and the reliability of the devices is improved. In addition, the utility model adopts the metal lug to interconnect the wafer level chips, and can ensure good conduction of the upper layer and the lower layer. Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the utility model. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A wafer level chip packaging structure is characterized by comprising a rewiring layer, a first welding ball, a chip, an SMT element and a plastic packaging layer; the rewiring layer is provided with a first surface and a second surface which are opposite to each other, and comprises a dielectric layer and a metal bump; the first solder ball is positioned on the first surface of the rewiring layer and is electrically connected with the metal bump; the plastic packaging layer is positioned on the second surface of the rewiring layer; the chip and the SMT element are arranged in the plastic package layer at intervals and are electrically connected with the metal lug.
2. The wafer-level chip package structure of claim 1, wherein an opening is formed in the dielectric layer, the opening exposes the metal bump, a second solder ball is disposed on the chip, the second solder ball is located in the opening, and the chip is flip-chip bonded to the metal bump through the second solder ball.
3. The wafer-level chip package structure of claim 2, wherein an upper opening size of the opening is larger than a lower opening size.
4. The wafer-level chip package structure of claim 2, wherein the number of the second solder balls and the number of the first solder balls are two or more.
5. The wafer level chip package structure of claim 2, wherein the first solder balls and the second solder balls comprise any one of copper balls, gold balls, solder balls, and alloy balls.
6. The wafer-level chip package structure of claim 2, wherein the first solder balls and the second solder balls are in one-to-one correspondence.
7. The wafer-level chip package structure of claim 1, wherein the molding layer comprises one of a polyimide layer, a silicone layer, and an epoxy layer.
8. The wafer-level chip package structure of claim 1, wherein the metal bump comprises any one of a gold block, a silver block, a nickel block, a titanium block, a copper block, and an aluminum block.
9. The wafer-level chip package structure according to claim 1, wherein the SMT components comprise active components and/or passive components.
10. The wafer-level chip package structure according to claim 9, wherein the SMT components include one or more of a resistor, an inductor, and a capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122553602.8U CN215988753U (en) | 2021-10-22 | 2021-10-22 | Wafer level chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122553602.8U CN215988753U (en) | 2021-10-22 | 2021-10-22 | Wafer level chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN215988753U true CN215988753U (en) | 2022-03-08 |
Family
ID=80512755
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122553602.8U Active CN215988753U (en) | 2021-10-22 | 2021-10-22 | Wafer level chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN215988753U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114937611A (en) * | 2022-05-27 | 2022-08-23 | 盛合晶微半导体(江阴)有限公司 | Fan-out type wafer level packaging structure and preparation method thereof |
-
2021
- 2021-10-22 CN CN202122553602.8U patent/CN215988753U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114937611A (en) * | 2022-05-27 | 2022-08-23 | 盛合晶微半导体(江阴)有限公司 | Fan-out type wafer level packaging structure and preparation method thereof |
| CN114937611B (en) * | 2022-05-27 | 2024-01-30 | 盛合晶微半导体(江阴)有限公司 | Fan-out type wafer level packaging structure and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11233036B2 (en) | Interconnect structure with redundant electrical connectors and associated systems and methods | |
| KR102591618B1 (en) | Semiconductor package and method of manufacturing the semiconductor package | |
| US10553458B2 (en) | Chip packaging method | |
| WO2018171099A1 (en) | Encapsulation method for encapsulation structure with integrated power transmission chip | |
| CN111370385A (en) | Fan-out type system-in-package structure and manufacturing method thereof | |
| CN111370387A (en) | Fan-out type system-in-package structure and manufacturing method thereof | |
| WO2018171100A1 (en) | Encapsulation method for encapsulation structure with integrated power transmission chip | |
| CN212084995U (en) | Wafer level package structure | |
| CN111370386A (en) | Fan-out type system-in-package structure and manufacturing method thereof | |
| CN112289742A (en) | Wafer system level three-dimensional fan-out type packaging structure and manufacturing method thereof | |
| CN211480019U (en) | Fan-out type system-in-package structure | |
| CN112289743A (en) | Wafer system level fan-out package structure and manufacturing method thereof | |
| CN110957284A (en) | Three-dimensional packaging structure of chip and packaging method thereof | |
| CN215988753U (en) | Wafer level chip packaging structure | |
| CN113497008A (en) | Semiconductor packaging structure and preparation method thereof | |
| US11894357B2 (en) | System-level packaging structure and method for LED chip | |
| CN215342506U (en) | Wafer-level ASIC 3D integrated substrate and packaging device | |
| CN112151394A (en) | Packaging structure and packaging method of three-dimensional fan-out type fingerprint identification chip | |
| CN212303700U (en) | System-in-package structure of LED chip | |
| CN213242537U (en) | Wafer system level three-dimensional fan-out type packaging structure | |
| CN215342505U (en) | Wafer-level ASIC 3D integrated substrate and packaging device | |
| CN114975242A (en) | Preparation method of 2.5D packaging structure | |
| CN112259954B (en) | Packaged antenna module and preparation method thereof | |
| CN211045375U (en) | Wafer level chip packaging structure | |
| CN109768032B (en) | Antenna packaging structure and packaging method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |