CN112018047A - Chip packaging structure and chip packaging method - Google Patents

Chip packaging structure and chip packaging method Download PDF

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Publication number
CN112018047A
CN112018047A CN201910455795.8A CN201910455795A CN112018047A CN 112018047 A CN112018047 A CN 112018047A CN 201910455795 A CN201910455795 A CN 201910455795A CN 112018047 A CN112018047 A CN 112018047A
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China
Prior art keywords
layer
chip
bonding
substrate
bump
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CN201910455795.8A
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Chinese (zh)
Inventor
吕娇
陈彦亨
林正忠
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SJ Semiconductor Jiangyin Corp
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SJ Semiconductor Jiangyin Corp
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Priority to CN201910455795.8A priority Critical patent/CN112018047A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a chip packaging structure and a chip packaging method, wherein the chip packaging structure comprises: the back of the chip is provided with a first bonding lug; the upper surface of the substrate is provided with a second bonding lug; the chip is bonded on the upper surface of the substrate through the first bonding lug and the second bonding lug; the plastic packaging layer is positioned on the upper surface of the substrate and is used for plastically packaging the chip, the first bonding lug and the second bonding lug; the rewiring layer is positioned on the upper surface of the plastic packaging layer and is electrically connected with the chip; and the solder ball bump is positioned on the upper surface of the rewiring layer and is electrically connected with the rewiring layer. The chip in the chip packaging structure is bonded on the upper surface of the substrate through the first bonding lug arranged on the back surface of the chip and the second bonding lug arranged on the upper surface of the substrate, the first bonding lug and the second bonding lug can enhance the bonding capability of the chip on the upper surface of the substrate, and the bonded chip is prevented from shifting on the upper surface of the substrate, so that the performance of the chip packaging structure is ensured.

Description

Chip packaging structure and chip packaging method
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a chip packaging structure and a chip packaging method.
Background
With the continuous demand for higher functionality, better performance and higher energy efficiency, it is the pursuit of the prior art to manufacture smaller-sized package structures at lower manufacturing costs; Fan-Out Wafer Level Package (FOWLP) has become one of the technologies that can meet the above requirements.
However, in the existing fan-out package structure, the chip is directly bonded to the surface of the substrate before the plastic layer is formed, and the chip is displaced under the action of external force during the formation of the plastic layer and the subsequent processes, thereby affecting the performance of the finally formed package structure.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a chip packaging structure and a chip packaging method, which are used to solve the problem in the prior art that the chip is easily displaced due to the direct bonding of the chip to the surface of the substrate, thereby affecting the performance of the finally formed packaging structure.
To achieve the above and other related objects, the present invention provides a chip package structure, including:
the back surface of the chip is provided with a first bonding lug;
the upper surface of the substrate is provided with a second bonding lug; the chip is bonded on the upper surface of the substrate through the first bonding bump and the second bonding bump;
the plastic packaging layer is positioned on the upper surface of the substrate and is used for plastically packaging the chip, the first bonding lug and the second bonding lug;
the rewiring layer is positioned on the upper surface of the plastic packaging layer and is electrically connected with the chip;
and the solder ball bump is positioned on the upper surface of the rewiring layer and is electrically connected with the rewiring layer.
Optionally, a connection pad is formed on the front surface of the chip, and the connection pad is electrically connected with a device structure inside the chip; the connection pad is electrically connected with the rewiring layer; the first bonding bump is located on the back surface of the chip.
Optionally, the upper surface of the molding layer is flush with the front surface of the chip.
Optionally, the chip package structure includes a plurality of the chips, a plurality of the first bonding bumps, and a plurality of the second bonding bumps; the chips are arranged on the upper surface of the substrate at intervals.
Optionally, the second bonding bump includes:
the plastic packaging material layer is positioned on the upper surface of the substrate;
the seed layer is positioned on the upper surface of the plastic packaging material layer;
and the bonding pad is positioned on the upper surface of the seed layer.
Optionally, the redistribution layer includes at least:
a first dielectric layer;
the metal laminated structure is positioned in the first dielectric layer and comprises a plurality of metal wire layers which are arranged at intervals and metal plugs, and the metal plugs are positioned between the adjacent metal wire layers so as to electrically connect the adjacent metal wire layers;
the chip is connected with the metal laminated structure, and the solder ball bump is connected with the metal laminated structure.
Optionally, the chip package structure further includes:
the sacrificial layer is positioned on the upper surface of the substrate;
the second dielectric layer is positioned on the upper surface of the sacrificial layer;
the second bonding lug and the plastic packaging layer are both positioned on the upper surface of the second medium layer.
In order to achieve the above and other related objects, the present invention further provides a chip packaging method, including the steps of:
preparing a chip, wherein a first bonding lug is formed on the back surface of the chip;
providing a substrate, and forming a second bonding bump on the upper surface of the substrate;
bonding the chip on the upper surface of the substrate through the first bonding bump and the second bonding bump;
forming a plastic packaging layer on the upper surface of the substrate, wherein the chip, the first bonding bump and the second bonding bump are subjected to plastic packaging by the plastic packaging layer;
forming a rewiring layer on the upper surface of the plastic packaging layer, wherein the rewiring layer is electrically connected with the chip;
forming a solder ball bump on the upper surface of the rewiring layer, wherein the solder ball bump is electrically connected with the rewiring layer;
and removing the substrate.
Optionally, the step of forming the second bonding bump on the upper surface of the substrate includes:
forming a plastic packaging material layer on the upper surface of the substrate;
forming a seed layer on the upper surface of the plastic packaging material layer;
patterning the plastic packaging material layer and the seed layer;
and forming a bonding welding pad on the upper surface of the patterned seed layer.
Optionally, the forming the redistribution layer on the upper surface of the molding compound layer includes the following steps: forming a first dielectric layer and a metal laminated structure on the upper surface of the plastic packaging layer, wherein the metal laminated structure is positioned in the first dielectric layer and comprises a plurality of metal wire layers and metal plugs which are arranged at intervals, and the metal plugs are positioned between the adjacent metal wire layers so as to electrically connect the adjacent metal wire layers.
Optionally, before forming the second bonding bump on the upper surface of the substrate, the method further includes the following steps:
forming a sacrificial layer on the upper surface of the substrate;
forming a second dielectric layer on the upper surface of the sacrificial layer;
the second bonding lug and the plastic package layer are formed on the upper surface of the second medium layer.
Optionally, the substrate is removed while the sacrificial layer is removed.
Optionally, the step of removing the second dielectric layer is further included after removing the sacrificial layer.
Optionally, the number of prepared chips is multiple, and the multiple chips are bonded on the upper surface of the substrate through the different first bonding bumps and the different second bonding bumps respectively; and after removing the substrate, carrying out slicing processing on the obtained structure to obtain a plurality of packaging structures comprising single chips.
As described above, the chip packaging structure and the chip packaging method of the present invention have the following advantages:
the chip in the chip packaging structure is bonded on the upper surface of the substrate through the first bonding lug arranged on the back surface of the chip and the second bonding lug arranged on the upper surface of the substrate, the first bonding lug and the second bonding lug can enhance the bonding capacity of the chip on the upper surface of the substrate, and the bonded chip is prevented from shifting on the upper surface of the substrate, so that the performance of the chip packaging structure is ensured;
the chip packaging method of the invention firstly forms the first bonding lug on the back of the chip, forms the second bonding lug on the upper surface of the substrate, and then bonds the chip on the upper surface of the substrate through the first bonding lug and the second bonding lug, the first bonding lug and the second bonding lug can enhance the capability of bonding the chip on the upper surface of the substrate, and prevent the bonded chip from shifting on the upper surface of the substrate when forming the plastic packaging layer, the rewiring layer and other structures, thereby ensuring the performance of the chip packaging structure.
Drawings
Fig. 1 is a schematic flow chart illustrating a chip packaging method according to a first embodiment of the invention.
Fig. 2 to fig. 20 are schematic cross-sectional structures of structures presented in steps of a chip packaging method according to a first embodiment of the present invention.
Fig. 21 is a schematic cross-sectional view illustrating a chip package structure according to a second embodiment of the invention.
Description of the element reference numerals
10 wafer
11 chip
111 connection pad
12 protective film
13 first bonding bump
131 seed layer
14 base
15 second bonding bump
151 plastic packaging material layer
152 seed layer
153 bond pad
16 plastic packaging layer
17 rewiring layer
171 first dielectric layer
1711 opening (C)
172 metal stack structure
18 solder ball bump
19 sacrificial layer
20 second dielectric layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 21. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
Referring to fig. 1, the present invention provides a chip packaging method, which includes the following steps:
1) preparing a chip, wherein a first bonding lug is formed on the back surface of the chip;
2) providing a substrate, and forming a second bonding bump on the upper surface of the substrate;
3) bonding the chip on the upper surface of the substrate through the first bonding bump and the second bonding bump;
4) forming a plastic packaging layer on the upper surface of the substrate, wherein the chip, the first bonding bump and the second bonding bump are subjected to plastic packaging by the plastic packaging layer;
5) forming a rewiring layer on the upper surface of the plastic packaging layer, wherein the rewiring layer is electrically connected with the chip;
6) forming a solder ball bump on the upper surface of the rewiring layer, wherein the solder ball bump is electrically connected with the rewiring layer;
7) and removing the substrate.
In step 1), please refer to step S1 in fig. 1 and fig. 2 to 7, a chip 11 is prepared, and a first bonding bump 13 is formed on a back surface of the chip 11.
As an example, step 1) may include the steps of:
1-1) providing a wafer 10, wherein a plurality of chips 11 are formed in the wafer 10, as shown in fig. 2; the number of the chips 11 in the wafer 10 may be set according to actual needs, and fig. 2 only illustrates two chips 11 in the wafer 10; a device structure (not shown) is formed in the chip 11, a connection pad 111 is formed on the front surface of the chip 11 (i.e. the front surface of the wafer 10), and the connection pad 111 is electrically connected to the device structure;
1-2) forming a protective film 12 on the front surface of the wafer 10, wherein the protective film 12 covers the front surface of the wafer 10 to ensure that the protective film 12 covers the connection pads 111, as shown in fig. 3;
1-3) forming a seed layer 131 on the back side of the wafer 10, wherein the seed layer 131 covers the back side of the wafer 10, as shown in fig. 4;
1-5) performing a patterning process on the seed layer 131 to form a first bonding bump 13 on the back side of the wafer 10, as shown in fig. 5; after the first bonding bumps 13 are formed, it is necessary to ensure that the back surface of each chip 11 is provided with a plurality of first bonding bumps 13;
1-6) performing a dicing process on the wafer 10 to separate the chips 11, as shown in fig. 6 and 7;
1-7) removing said protective film 12, as shown in fig. 7.
By way of example, the wafer 10 may include a silicon wafer, a gallium nitride wafer, and the like.
As an example, the protection film 12 may include any film structure that can protect the front surface of the chip 11 in the process after the step 1-2), such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an organic material layer (such as a photoresist layer, etc.), and the like.
As an example, the seed layer 131 may be formed using a process such as plating or sputtering, and may include at least one of a titanium (Ti) layer and a copper (Cu) layer.
As an example, the seed layer 131 may be patterned by using a photolithography process to obtain the first bonding bump 131.
As an example, the wafer 10 may be diced by any dicing process, and the specific method for dicing the wafer 10 to separate the chips 11 is known to those skilled in the art, and will not be described herein again.
As an example, the protective film 12 may be removed using an etching process, a grinding process, or the like.
As an example, a schematic cross-sectional structure of the chip 11 obtained after step 1) is shown in fig. 7.
In step 2), please refer to step S2 in fig. 1 and fig. 8 to 10, a substrate 14 is provided, and a second bonding bump 15 is formed on the upper surface of the substrate 14.
By way of example, the substrate 14 may be made of one or a composite of two or more of silicon, glass, silicon oxide, ceramic, polymer, and metal, and may have a circular, square, or any other desired shape. Preferably, in this embodiment, the material of the substrate 14 is silicon.
As an example, before forming the second bonding bump 15 on the upper surface of the substrate 14, the method further includes the following steps:
forming a sacrificial layer 19 on the upper surface of the substrate 14, as shown in fig. 8;
a second dielectric layer 20 is formed on the upper surface of the sacrificial layer 19, as shown in fig. 8.
As an example, the sacrificial layer 19 is used as a separation layer between the second dielectric layer 20 and the substrate 14 in the subsequent process, and is preferably made of an adhesive material with a smooth surface, which must have a certain bonding force with the second dielectric layer 20 and a strong bonding force with the substrate 14, and generally, the bonding force between the sacrificial layer 19 and the substrate 14 needs to be greater than that with the second dielectric layer 20.
As an example, the sacrificial layer 19 may include a polymer layer or a tape-shaped adhesive layer; specifically, the material of the sacrificial layer 19 may be selected from an adhesive tape (e.g., a die attach film, a non-conductive film, or the like) having two adhesive surfaces, an adhesive glue formed by a spin coating process, or the like; preferably, in this embodiment, the sacrificial layer 19 is preferably a UV tape, which is easily torn off after being irradiated by UV light (ultraviolet light); of course, in other examples, the sacrificial layer 19 may also be formed by other material layers formed by a physical vapor deposition method or a chemical vapor deposition method, such as Epoxy resin (Epoxy), silicone rubber (silicone rubber), Polyimide (PI), Polybenzoxazole (PBO), benzocyclobutene (BCB), and the like, and when the substrate 14 is subsequently separated, the sacrificial layer 19 may be removed by wet etching, chemical mechanical polishing, and the like.
The sacrificial layer 19 may also be formed by an automatic patch process, as an example.
As an example, the material of the second dielectric layer 20 may include a low-k dielectric material. Specifically, the material of the second dielectric layer 20 may include one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass; the second dielectric layer 20 may be formed using a process such as spin-on coating, CVD, plasma enhanced CVD, or the like.
As an example, the step 2) of forming the second bonding bump 15 on the upper surface of the substrate 14 may include the steps of:
2-1) forming a molding compound layer 151 on the upper surface of the substrate 14, as shown in fig. 9;
2-2) forming a seed layer 152 on the upper surface of the plastic packaging material layer 151, as shown in fig. 9;
2-3) patterning the plastic package material layer 151 and the seed layer 152, and defining the position and the shape of the second bonding bump 15 by the patterned plastic package material layer 151 and the patterned seed layer 152, as shown in fig. 10;
2-4) forming bonding pads 153 on the upper surface of the patterned seed layer 152, as shown in fig. 10.
It should be noted that, when the sacrificial layer 19 is formed on the upper surface of the substrate 14 and the second dielectric layer 20 is formed on the upper surface of the sacrificial layer 19, the plastic package material layer 151 is formed on the upper surface of the second dielectric layer 20.
As an example, the material of the molding compound layer 151 may include, but is not limited to, polyimide, silicon gel, epoxy resin, or the like.
As an example, the seed layer 152 may be formed using, but not limited to, a sputtering process; the material of the seed layer 152 may include at least one of Ti (titanium) and Cu (copper); specifically, the seed layer 152 may be a titanium layer, a copper layer, a stacked structure of a titanium layer and a copper layer, or a titanium-copper alloy layer.
As an example, the material of the bonding pad 153 may include at least one of Cu and Sn (tin); specifically, the bonding pad 153 may include a copper pad, a tin pad, a copper layer stacked with a tin layer, and a copper-tin alloy pad.
As an example, the number of the second bonding bumps 15 is the same as the number of the first bonding bumps 13.
In step 3), please refer to step S3 in fig. 1 and fig. 11, the chip 11 is bonded on the upper surface of the substrate 14 through the first bonding bump 13 and the second bonding bump 15.
As an example, the first bonding bump 13 is bonded to the second bonding bump 15 to achieve bonding of the chip 11 to the upper surface of the substrate 14.
As an example, after the chips 11 are bonded to the upper surface of the substrate 14, the first bonding bumps 13 and the second bonding bumps 15 are arranged in a one-to-one correspondence, that is, the first bonding bumps 13 and the second bonding bumps 15 are bonded in a one-to-one correspondence.
As an example, the number of the chips 11 bonded on the upper surface of the substrate 14 may be set according to actual needs, for example, the number of the chips 11 bonded on the upper surface of the substrate 14 may be one, two, three or more.
In step 4), please refer to step S4 in fig. 1 and fig. 12 to 13, a molding layer 16 is formed on the upper surface of the substrate 14, and the chip 11, the first bonding bump 13 and the second bonding bump 15 are molded by the molding layer 16.
It should be noted that, when the sacrificial layer 19 is formed on the upper surface of the substrate 14 and the second dielectric layer 20 is formed on the upper surface of the sacrificial layer 19, the molding compound layer 16 is formed on the upper surface of the second dielectric layer 20.
By way of example, but not limitation, a mold underfill process, an imprint molding process, a transfer molding process, a liquid seal molding process, a vacuum lamination process, or a spin coating process may be used to form the molding layer 16 on the upper surface of the substrate 14; preferably, in this embodiment, the molding underfill process is used to form the molding layer 16 on the upper surface of the substrate 14. The plastic-sealed layer 16 is formed by adopting a molding underfill process, and the plastic-sealed layer 16 can smoothly and rapidly fill the gaps among the chip 11, the first bonding bump 13 and the second bonding bump 15, so that interface delamination can be effectively avoided; and the molding underfill process is not limited as the capillary underfill operation in the prior art, greatly reduces the process difficulty, can be used for smaller connection gaps, and is more suitable for stacked structures.
By way of example, the molding layer 16 may include, but is not limited to, a polymer-based material, a resin-based material, polyimide, silicone, epoxy, or the like.
As an example, the upper surface of the initially formed molding compound layer 16 may be higher than the front surface of the chip 11, as shown in fig. 12, in this case, after the molding compound layer 16 is formed, a process of thinning the molding compound layer 16 is further performed, and specifically, the molding compound layer 16 may be thinned by, but not limited to, a chemical mechanical polishing process, so that the remaining upper surface of the molding compound layer 16 is flush with the upper surface of the chip 11, as shown in fig. 13. Of course, in other examples, the upper surface of the initially formed molding compound layer 16 is flush with the upper surface of the chip 11, as shown in fig. 13, and in this case, the process of thinning the molding compound layer 16 may be omitted.
In step 5), please refer to step S1 in fig. 1 and fig. 14 to fig. 15, a redistribution layer 17 is formed on the upper surface of the molding layer 16, and the redistribution layer 17 is electrically connected to the chip 11.
As an example, forming the redistribution layer 17 on the upper surface of the molding compound layer 16 includes the following steps: a first dielectric layer 171 and a metal stack structure 172 are formed on the upper surface of the plastic package layer 16, the metal stack structure 172 is located in the first dielectric layer 171, the metal stack structure 172 includes a plurality of metal wire layers (not shown) arranged at intervals and metal plugs (not shown), and the metal plugs are located between adjacent metal wire layers to electrically connect the adjacent metal wire layers.
Specifically, the step of forming the redistribution layer 17 on the upper surface of the molding compound layer 16 may include the following steps:
5-1) forming a layer of the first dielectric layer 171 on the upper surface of the molding layer 16, and forming an opening 1711 in the first dielectric layer 171, the opening exposing the connection pad 111, as shown in fig. 14;
5-2) forming the metal laminated structure 172 and other layers of the first dielectric layer 171 on the layer of the first dielectric layer 171 formed in the step 5-1); the first dielectric layer 171 exposes the metal wire layer located at the top layer in the metal stack structure 172, as shown in fig. 15.
As an example, the material of the first dielectric layer 171 may include a low-k dielectric material. As an example, the first dielectric layer 171 may be made of one of epoxy, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the first dielectric layer 171 may be formed by a process such as spin coating, CVD, plasma enhanced CVD, or the like.
As an example, the metal line layer may include a single metal layer, and may also include two or more metal layers. As an example, the material of the metal wire layer and the material of the metal plug may include one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
In step 6), please refer to step S6 in fig. 1 and fig. 16, a solder ball bump 18 is formed on the upper surface of the redistribution layer 17, and the solder ball bump 18 is electrically connected to the redistribution layer 17.
As an example, the material of the solder ball bump 18 may include at least one of copper and tin.
Specifically, the solder ball bumps 18 are electrically connected to the metal wire layer in the redistribution layer 17. The specific process for forming the solder ball bump 18 is known to those skilled in the art and will not be described herein.
In step 7), please refer to step S7 in fig. 1 and fig. 17, the substrate 14 is removed.
As an example, the sacrificial layer 19 may be removed at the same time as the substrate 14 is removed.
As an example, a grinding process, a thinning process, or a tearing process may be used to remove the sacrificial layer 19 and the substrate 14; preferably, in this embodiment, the substrate 14 is removed by tearing off the sacrificial layer 19.
Illustratively, the step of removing the second dielectric layer 20 is further included after removing the sacrificial layer 19, as shown in fig. 18. Specifically, the second dielectric layer 20 may be removed by a grinding process or an etching process.
As an example, a plurality of chips 11 are bonded on the upper surface of the substrate 14, and after the substrate 14 is removed, a step of dicing the resulting structure is further included to obtain a plurality of package structures including a single chip 11, as shown in fig. 19 and 20.
Example two
Referring to fig. 21 in conjunction with fig. 2 to fig. 20, the present invention further provides a chip package structure, including: the chip comprises a chip 11, wherein a first bonding bump 13 is arranged on the back surface of the chip 11; a substrate 14, wherein a second bonding bump 15 is arranged on the upper surface of the substrate 14; the chip 11 is bonded on the upper surface of the substrate 14 via the first bonding bump 13 and the second bonding bump 15; the plastic packaging layer 16 is positioned on the upper surface of the substrate 14, and the chip 11, the first bonding bump 13 and the second bonding bump 15 are subjected to plastic packaging; a rewiring layer 17, wherein the rewiring layer 17 is positioned on the upper surface of the plastic packaging layer 16 and is electrically connected with the chip 11; and the solder ball bump 18 is positioned on the upper surface of the redistribution layer 17, and the solder ball bump 18 is electrically connected with the redistribution layer 17.
By way of example, the chip 11 may include a silicon chip, a gallium nitride chip, or the like.
As an example, a device structure (not shown) is formed in the chip 11, and a connection pad 111 is formed on the front surface of the chip 11, wherein the connection pad 111 is electrically connected to the device structure.
As an example, the first bonding bump 13 may include at least one of a titanium layer or a copper layer.
By way of example, the substrate 14 may be made of one or a composite of two or more of silicon, glass, silicon oxide, ceramic, polymer, and metal, and may have a circular, square, or any other desired shape. Preferably, in this embodiment, the material of the substrate 14 is silicon.
As an example, the chip package structure may include a plurality of the chips 11, a plurality of the first bonding bumps 13, and a plurality of the second bonding bumps 15; a plurality of the chips 11 are arranged at intervals on the upper surface of the substrate 14. Of course, in other examples, the chip package structure may also include one chip 11.
As an example, referring to fig. 10, the second bonding bump 15 may include: a layer of molding compound 151, the layer of molding compound 151 being located on the upper surface of the substrate 14; a seed layer 152, wherein the seed layer 152 is located on the upper surface of the plastic package material layer 151; and a bonding pad 153, wherein the bonding pad 153 is positioned on the upper surface of the seed layer 152.
As an example, the material of the molding compound layer 151 may include, but is not limited to, polyimide, silicon gel, epoxy resin, or the like.
As an example, the seed layer 152 may be formed using, but not limited to, a sputtering process; the material of the seed layer 152 may include at least one of Ti (titanium) and Cu (copper); specifically, the seed layer 152 may be a titanium layer, a copper layer, a stacked structure of a titanium layer and a copper layer, or a titanium-copper alloy layer.
As an example, the material of the bonding pad 153 may include at least one of Cu and Sn (tin); specifically, the bonding pad 153 may include a copper pad, a tin pad, a copper layer stacked with a tin layer, and a copper-tin alloy pad.
As an example, the number of the second bonding bumps 15 is the same as the number of the first bonding bumps 13.
By way of example, the molding layer 16 may include, but is not limited to, a polymer-based material, a resin-based material, polyimide, silicone, epoxy, or the like.
As an example, the upper surface of the molding layer 16 may be flush with the front surface of the chip 11.
As an example, the re-wiring layer 17 includes at least: a first dielectric layer 171; a metal stack structure 172, wherein the metal stack structure 172 is located in the first dielectric layer 171, the metal stack structure 172 includes a plurality of metal wire layers (not shown) arranged at intervals, and metal plugs (not shown) located between adjacent metal wire layers to electrically connect the adjacent metal wire layers; the chip 11 is electrically connected to the metal stack structure 172.
As an example, the material of the first dielectric layer 171 may include a low-k dielectric material. As an example, the first dielectric layer 171 may be made of one of epoxy, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the first dielectric layer 171 may be formed by a process such as spin coating, CVD, plasma enhanced CVD, or the like.
As an example, the metal line layer may include a single metal layer, and may also include two or more metal layers. As an example, the material of the metal wire layer and the material of the metal plug may include one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
As an example, the material of the solder ball bump 18 may include at least one of copper and tin. The solder ball bumps 18 are electrically connected to the metal line layer in the re-wiring layer 17.
As an example, the chip packaging structure further includes: a sacrificial layer 19, the sacrificial layer 19 being located on an upper surface of the substrate 14; the second dielectric layer 20, the second dielectric layer 20 is located on the upper surface of the sacrificial layer 19; the second bonding bump 15 and the molding compound layer 16 are both located on the upper surface of the second dielectric layer 20.
As an example, the sacrificial layer 19 is used as a separation layer between the second dielectric layer 20 and the substrate 14 in the subsequent process, and is preferably made of an adhesive material with a smooth surface, which must have a certain bonding force with the second dielectric layer 20 and a strong bonding force with the substrate 14, and generally, the bonding force between the sacrificial layer 19 and the substrate 14 needs to be greater than that with the second dielectric layer 20.
As an example, the sacrificial layer 19 may include a polymer layer or a tape-shaped adhesive layer; specifically, the material of the sacrificial layer 19 may be selected from an adhesive tape (e.g., a die attach film, a non-conductive film, or the like) having two adhesive surfaces, an adhesive glue formed by a spin coating process, or the like; preferably, in this embodiment, the sacrificial layer 19 is preferably a UV tape, which is easily torn off after being irradiated by UV light (ultraviolet light); of course, in other examples, the sacrificial layer 19 may also be formed by other material layers formed by a physical vapor deposition method or a chemical vapor deposition method, such as Epoxy resin (Epoxy), silicone rubber (silicone rubber), Polyimide (PI), Polybenzoxazole (PBO), benzocyclobutene (BCB), and the like, and when the substrate 14 is subsequently separated, the sacrificial layer 19 may be removed by wet etching, chemical mechanical polishing, and the like.
As an example, the material of the second dielectric layer 20 may include a low-k dielectric material. Specifically, the material of the second dielectric layer 20 may include one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass; the second dielectric layer 20 may be formed using a process such as spin-on coating, CVD, plasma enhanced CVD, or the like.
In summary, the present invention provides a chip package structure and a chip package method, wherein the chip package structure includes: the back surface of the chip is provided with a first bonding lug; the upper surface of the substrate is provided with a second bonding lug; the chip is bonded on the upper surface of the substrate through the first bonding bump and the second bonding bump; the plastic packaging layer is positioned on the upper surface of the substrate and is used for plastically packaging the chip, the first bonding lug and the second bonding lug; the rewiring layer is positioned on the upper surface of the plastic packaging layer and is electrically connected with the chip; and the solder ball bump is positioned on the upper surface of the rewiring layer and is electrically connected with the rewiring layer. The chip in the chip packaging structure is bonded on the upper surface of the substrate through the first bonding lug arranged on the back surface of the chip and the second bonding lug arranged on the upper surface of the substrate, the first bonding lug and the second bonding lug can enhance the bonding capacity of the chip on the upper surface of the substrate, and the bonded chip is prevented from shifting on the upper surface of the substrate, so that the performance of the chip packaging structure is ensured; the chip packaging method of the invention firstly forms the first bonding lug on the back of the chip, forms the second bonding lug on the upper surface of the substrate, and then bonds the chip on the upper surface of the substrate through the first bonding lug and the second bonding lug, the first bonding lug and the second bonding lug can enhance the capability of bonding the chip on the upper surface of the substrate, and prevent the bonded chip from shifting on the upper surface of the substrate when forming the plastic packaging layer, the rewiring layer and other structures, thereby ensuring the performance of the chip packaging structure.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (14)

1. A chip package structure, comprising:
the back surface of the chip is provided with a first bonding lug;
the upper surface of the substrate is provided with a second bonding lug; the chip is bonded on the upper surface of the substrate through the first bonding bump and the second bonding bump;
the plastic packaging layer is positioned on the upper surface of the substrate and is used for plastically packaging the chip, the first bonding lug and the second bonding lug;
the rewiring layer is positioned on the upper surface of the plastic packaging layer and is electrically connected with the chip;
and the solder ball bump is positioned on the upper surface of the rewiring layer and is electrically connected with the rewiring layer.
2. The chip package structure according to claim 1, wherein: a connecting welding pad is formed on the front surface of the chip and is electrically connected with a device structure in the chip; the connection pad is electrically connected with the rewiring layer; the first bonding bump is located on the back surface of the chip.
3. The chip package structure according to claim 1, wherein: the upper surface of the plastic packaging layer is flush with the front surface of the chip.
4. The chip package structure according to claim 1, wherein: the chip packaging structure comprises a plurality of chips, a plurality of first bonding bumps and a plurality of second bonding bumps; the chips are arranged on the upper surface of the substrate at intervals.
5. The chip package structure according to claim 1, wherein: the second bonding bump includes:
the plastic packaging material layer is positioned on the upper surface of the substrate;
the seed layer is positioned on the upper surface of the plastic packaging material layer;
and the bonding pad is positioned on the upper surface of the seed layer.
6. The chip packaging structure according to any one of claims 1 to 5, wherein: the re-routing layer includes at least:
a first dielectric layer;
the metal laminated structure is positioned in the first dielectric layer and comprises a plurality of metal wire layers which are arranged at intervals and metal plugs, and the metal plugs are positioned between the adjacent metal wire layers so as to electrically connect the adjacent metal wire layers;
the chip is connected with the metal laminated structure, and the solder ball bump is connected with the metal laminated structure.
7. The chip package structure according to claim 6, wherein: the chip packaging structure further comprises:
the sacrificial layer is positioned on the upper surface of the substrate;
the second dielectric layer is positioned on the upper surface of the sacrificial layer;
the second bonding lug and the plastic packaging layer are both positioned on the upper surface of the second medium layer.
8. A chip packaging method is characterized by comprising the following steps:
preparing a chip, wherein a first bonding lug is formed on the back surface of the chip;
providing a substrate, and forming a second bonding bump on the upper surface of the substrate;
bonding the chip on the upper surface of the substrate through the first bonding bump and the second bonding bump;
forming a plastic packaging layer on the upper surface of the substrate, wherein the chip, the first bonding bump and the second bonding bump are subjected to plastic packaging by the plastic packaging layer;
forming a rewiring layer on the upper surface of the plastic packaging layer, wherein the rewiring layer is electrically connected with the chip;
forming a solder ball bump on the upper surface of the rewiring layer, wherein the solder ball bump is electrically connected with the rewiring layer;
and removing the substrate.
9. The chip packaging method according to claim 8, wherein: forming the second bonding bump on the upper surface of the substrate includes the following steps:
forming a plastic packaging material layer on the upper surface of the substrate;
forming a seed layer on the upper surface of the plastic packaging material layer;
patterning the plastic packaging material layer and the seed layer;
and forming a bonding welding pad on the upper surface of the patterned seed layer.
10. The chip packaging method according to claim 8, wherein: forming the redistribution layer on the upper surface of the plastic package layer includes the following steps: forming a first dielectric layer and a metal laminated structure on the upper surface of the plastic packaging layer, wherein the metal laminated structure is positioned in the first dielectric layer and comprises a plurality of metal wire layers and metal plugs which are arranged at intervals, and the metal plugs are positioned between the adjacent metal wire layers so as to electrically connect the adjacent metal wire layers.
11. The chip packaging method according to claim 10, wherein: before forming the second bonding bump on the upper surface of the substrate, the method further includes the following steps:
forming a sacrificial layer on the upper surface of the substrate;
forming a second dielectric layer on the upper surface of the sacrificial layer;
the second bonding lug and the plastic package layer are formed on the upper surface of the second medium layer.
12. The chip packaging method according to claim 11, wherein: and removing the substrate and the sacrificial layer at the same time.
13. The chip packaging method according to claim 12, wherein: and removing the second dielectric layer after removing the sacrificial layer.
14. The chip packaging method according to any one of claims 8 to 13, wherein: preparing a plurality of chips, wherein the plurality of chips are bonded on the upper surface of the substrate through the different first bonding bumps and the different second bonding bumps; and after removing the substrate, carrying out slicing processing on the obtained structure to obtain a plurality of packaging structures comprising single chips.
CN201910455795.8A 2019-05-29 2019-05-29 Chip packaging structure and chip packaging method Pending CN112018047A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112786462A (en) * 2020-12-25 2021-05-11 上海易卜半导体有限公司 Semiconductor packaging method, semiconductor assembly and electronic equipment comprising semiconductor assembly
US11955396B2 (en) 2020-11-27 2024-04-09 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11955396B2 (en) 2020-11-27 2024-04-09 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly
US12046525B2 (en) 2020-11-27 2024-07-23 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly
CN112786462A (en) * 2020-12-25 2021-05-11 上海易卜半导体有限公司 Semiconductor packaging method, semiconductor assembly and electronic equipment comprising semiconductor assembly
CN112786462B (en) * 2020-12-25 2023-08-22 上海易卜半导体有限公司 Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly

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