CN206931596U - Fan-out-type laminated packaging structure - Google Patents
Fan-out-type laminated packaging structure Download PDFInfo
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- CN206931596U CN206931596U CN201720806310.1U CN201720806310U CN206931596U CN 206931596 U CN206931596 U CN 206931596U CN 201720806310 U CN201720806310 U CN 201720806310U CN 206931596 U CN206931596 U CN 206931596U
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- wiring layer
- soldered ball
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The utility model provides a kind of fan-out-type laminated packaging structure, including re-wiring layer；Soldered ball is connected, is electrically connected positioned at the upper surface of the re-wiring layer, and with the re-wiring layer；First semiconductor chip, electrically connected positioned at the upper surface of the re-wiring layer, and with the re-wiring layer；Plastic packaging layer, the gap filled up between the connection soldered ball and first semiconductor chip, and by the connection soldered ball and the first semiconductor chip plastic packaging, the upper surface of the plastic packaging layer is not higher than the upper surface of the connection soldered ball；Solder projection, electrically connected positioned at the lower surface of the re-wiring layer, and with the re-wiring layer.The utility model uses connecting pole of the connection soldered ball as connection re-wiring layer in plastic packaging layer, and the plant ball technique that connection soldered ball can use technics comparing ripe is directly formed, and technique is simple, cost is relatively low.
Description
Technical field
Technical field of semiconductor encapsulation is the utility model is related to, more particularly to a kind of fan-out-type laminated packaging structure.
Background technology
It is more inexpensive, more reliable, faster and more highdensity circuit be integrated antenna package pursue target.In future,
Integrated antenna package will improve the integration density of various electronic components by constantly reducing minimum feature size.At present, first
The method for packing entered includes：Wafer chip level chip-scale package (Wafer Level Chip Scale Packaging,
WLCSP), fan-out-type wafer-level packaging (Fan-Out Wafer Level Package, FOWLP), flip-chip (Flip
Chip), stacked package (Package on Package, POP) etc..
Fan-out-type wafer-level packaging is a kind of embedded chip method for packing of wafer level processing, be current a kind of input/
One of preferable Advanced Packaging method of more, the integrated flexibility of output port (I/O).Fan-out-type wafer-level packaging is compared to routine
Wafer-level packaging have its it is unique the advantages of：1. I/O spacing is flexible, independent of chip size；2. only use effective nude film
(die), product yield improves；3. there is flexible 3D package paths, you can to form the figure of General Cell at top；4. have
There are preferable electrical property and hot property；5. frequency applications；6. easily realize high-density wiring in re-wiring layer (RDL).Mesh
Before, fan-out-type wafer-level packaging method is generally：Carrier is provided, peel ply is formed in carrier surface；Photoetching, electricity on peel ply
Plate out re-wiring layer (Redistribution Layers, RDL)；Chip is installed to by cloth again using chip bonding process
On line layer, and in formation metal connecting pole on the re-wiring layer；Using Shooting Technique by chip plastic packaging in capsulation material layer
In；Remove carrier and peel ply；Photoetching, plating form Underbump metallization layer (UBM) on re-wiring layer；Carried out on UBM
Ball backflow is planted, forms soldered ball projection.However, in existing technique, metal connecting pole is using shapes such as electroplating technology, routing techniques
Into technics comparing is complicated, and cost is higher.
Utility model content
In view of the above the shortcomings that prior art, the purpose of this utility model is to provide a kind of fan-out-type stacked package
Structure, for solving the problems, such as that complex process, cost are higher existing for fan-out-type laminated packaging structure of the prior art.
In order to achieve the above objects and other related objects, the utility model provides a kind of system of fan-out-type laminated packaging structure
Preparation Method, the preparation method of the fan-out-type laminated packaging structure comprise the following steps：
1) carrier is provided；
2) re-wiring layer is formed in the upper surface of the carrier；
3) connection soldered ball, the connection soldered ball and re-wiring layer electricity are formed in the upper surface of the re-wiring layer
Connection；
4) in the re-wiring layer upper surface formed the first semiconductor chip, first semiconductor chip with it is described
Re-wiring layer electrically connects；Upper surface of the upper surface of first semiconductor chip less than the connection soldered ball；
5) in the re-wiring layer upper surface formed plastic packaging layer, the plastic packaging layer fill up it is described connection soldered ball with it is described
Gap between first semiconductor chip, and connect soldered ball and the first semiconductor chip plastic packaging by described；The plastic packaging layer
Upper surface not higher than it is described connection soldered ball upper surface；
6) carrier is removed；
7) solder projection, the solder projection and re-wiring layer electricity are formed in the lower surface of the re-wiring layer
Connection.
Preferably, the step of upper surface formation peel ply of the carrier is also included between step 1) and step 2)；Step
It is rapid 2) in, the re-wiring layer is formed at the upper surface of the peel ply.
Preferably, step 2) comprises the following steps：
2-1) metal line layer is formed in the upper surface of the carrier；
Dielectric layer 2-2) is formed in the upper surface of the carrier, the dielectric wraps up the metal line layer, and institute
State the upper surface of dielectric layer and the upper surface flush of the metal line layer.
Preferably, step 2) comprises the following steps：
2-1) first layer metal line layer is formed in the upper surface of the carrier；
Dielectric layer 2-2) is formed in the upper surface of the carrier, the dielectric seals metal line layer described in first layer
Wrap up in, and the upper surface of the dielectric layer is higher than the upper surface of the metal line layer；
If 2-3) the stacked spaced apart row electrically connected in formation dried layer in the dielectric layer with metal line layer described in first layer
Other metal line layers of cloth, electrically connected via metal plug between the adjacent metal line layer.
Preferably, in step 3), the connection soldered ball is formed in the upper surface of the re-wiring layer using ball technique is planted.
Preferably, in step 5), using compressing and forming process, transfer shaping technology, hydraulic seal moulding process, vacuum layer
Pressure technique or spin coating proceeding form the plastic packaging layer in the upper surface of the re-wiring layer.
Preferably, in step 5), the height according to the connection soldered ball forms the plastic packaging layer.
Preferably, step 5) comprises the following steps：
Plastic packaging layer 5-1) is formed in the upper surface of the re-wiring layer, the plastic packaging layer fills up the connection soldered ball and institute
The gap between the first semiconductor chip is stated, and the connection soldered ball and first semiconductor chip are encapsulated into plastic packaging completely；
5-2) remove the part plastic packaging layer and the part connection soldered ball so that the upper surface of the connection soldered ball and institute
State the upper surface flush of plastic packaging layer.
Preferably, in step 7), form solder projection in the lower surface of the re-wiring layer and comprise the following steps：
7-1) metal column is formed in the upper surface of the re-wiring layer；
7-2) soldered ball is formed in the upper surface of the metal column.
Preferably, after step 7), be also included in the plastic packaging layer upper surface be bonded the second semiconductor chip the step of,
Second semiconductor chip electrically connects with the connection soldered ball.
The utility model also provides a kind of fan-out-type laminated packaging structure, and the fan-out-type laminated packaging structure includes：
Re-wiring layer；
Soldered ball is connected, is electrically connected positioned at the upper surface of the re-wiring layer, and with the re-wiring layer；
First semiconductor chip, electrically connected positioned at the upper surface of the re-wiring layer, and with the re-wiring layer；
Plastic packaging layer, the gap filled up between the connection soldered ball and first semiconductor chip, and the connection is welded
Ball and the first semiconductor chip plastic packaging, the upper surface of the plastic packaging layer is not higher than the upper surface for connecting soldered ball；
Solder projection, electrically connected positioned at the lower surface of the re-wiring layer, and with the re-wiring layer.
Preferably, the re-wiring layer includes：
Dielectric layer；
Metal line layer, in the dielectric layer, and the upper surface of the metal line layer and the dielectric layer is upper
Surface flush, the lower surface of the metal line layer and the lower surface flush of the dielectric layer.
Preferably, the re-wiring layer includes：
Dielectric layer；
Metallic stacked structure, in the dielectric layer；The metallic stacked structure includes the gold of Spaced arrangement
Belong to line layer and metal plug, the metal plug is between the adjacent metal line layer, by the adjacent metal line layer
Electrical connection.
Preferably, the upper surface of the plastic packaging layer and the upper surface flush of the connection soldered ball.
Preferably, the plastic packaging layer includes polyimide layer, layer of silica gel, epoxy resin layer, curable polymeric substrate
The bed of material or the curable resin base material bed of material.
Preferably, the soldered ball projection includes：
Metal column, electrically connected positioned at the lower surface of the re-wiring layer, and with the re-wiring layer；
Soldered ball, positioned at the lower surface of the metal column.
Preferably, the solder projection is soldered ball.
Preferably, the fan-out-type laminated packaging structure also includes the second semiconductor chip, second semiconductor chip
Electrically connected positioned at the upper surface of the plastic packaging layer, and with the connection soldered ball.
As described above, fan-out-type laminated packaging structure of the present utility model, has the advantages that：The utility model makes
The connecting pole of re-wiring layer is connected in by the use of connection soldered ball as plastic packaging layer, connection soldered ball can use the ripe plant of technics comparing
Ball technique is directly formed, and technique is simple, cost is relatively low.
Brief description of the drawings
Fig. 1 is shown as the stream of the preparation method of the fan-out-type system-in-package structure provided in the utility model embodiment one
Cheng Tu.
Fig. 2 to Figure 11 is shown as the preparation side of the fan-out-type system-in-package structure provided in the utility model embodiment one
Structural representation corresponding to each step in method.
Component label instructions
1 carrier
11 peel plies
2 re-wiring layers
21 metal line layers
22 dielectric layers
3 connection soldered balls
4 first semiconductor chips
41 solder dimpling blocks
5 plastic packaging layers
6 solder projections
61 metal columns
62 soldered balls
7 second semiconductor chips
Embodiment
Illustrate embodiment of the present utility model below by way of specific instantiation, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the present utility model easily.The utility model can also be by addition
Different embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints with answering
With, without departing from it is of the present utility model spirit under carry out various modifications or alterations.
Fig. 1 is referred to Figure 11.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, though when the component relevant with the utility model is only shown in diagram rather than being implemented according to reality
Component count, shape and size are drawn, and it is actual when implementing form, quantity and the ratio of each component can be a kind of changing arbitrarily
Become, and its assembly layout form may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the present embodiment provides a kind of preparation method of fan-out-type laminated packaging structure, the fan-out-type lamination
The preparation method of encapsulating structure comprises the following steps：
1) carrier is provided；
2) re-wiring layer is formed in the upper surface of the carrier；
3) connection soldered ball, the connection soldered ball and re-wiring layer electricity are formed in the upper surface of the re-wiring layer
Connection；
4) in the re-wiring layer upper surface formed the first semiconductor chip, first semiconductor chip with it is described
Re-wiring layer electrically connects；Upper surface of the upper surface of first semiconductor chip less than the connection soldered ball；
5) in the re-wiring layer upper surface formed plastic packaging layer, the plastic packaging layer fill up it is described connection soldered ball with it is described
Gap between first semiconductor chip, and connect soldered ball and the first semiconductor chip plastic packaging by described；The plastic packaging layer
Upper surface not higher than it is described connection soldered ball upper surface；
6) carrier is removed；
7) solder projection, the solder projection and re-wiring layer electricity are formed in the lower surface of the re-wiring layer
Connection.
In step 1), S1 steps and Fig. 2 in Fig. 1 are referred to, there is provided a carrier 1.
As an example, the material of the carrier 1 can include in silicon, glass, silica, ceramics, polymer and metal
One or more kinds of composites, its shape can be wafer shape, it is square or it is other it is any needed for shape；The present embodiment
The problems such as by the carrier 1 to prevent subsequent preparation process SMIS chip architecture 3 from rupture, warpage, fracture occurs.
As an example, as shown in Figure 3, there is provided after the carrier 1, the upper surface for being also included in the carrier 1 forms stripping
The step of absciss layer 11.
As an example, the peel ply 11 as the re-wiring layer 2 being subsequently formed and is located in subsequent technique
The separating layer between other structures and the carrier 1 on the re-wiring layer 2, it is preferably from viscous with smooth finish surface
Condensation material is made, and it must have certain adhesion with re-wiring layer 2, to ensure the re-wiring layer 2 in follow-up work
Situations such as mobile will not be produced in skill, in addition, it also has stronger adhesion with the carrier 1, in general, its with it is described
The adhesion of carrier 1 needs to be more than the adhesion with the re-wiring layer 2.As an example, the material choosing of the peel ply 11
From the two-sided adhesive tape for being respectively provided with viscosity or the adhesive glue made by spin coating proceeding etc..Adhesive tape preferably uses UV adhesive tapes, and it is in UV
It is easy to pull off after light irradiation.In other embodiments, physical vaporous deposition or change also can be selected in the peel ply 11
The other materials layer that vapour deposition process is formed is learned, as epoxy resin (Epoxy), silicon rubber (silicone rubber), polyamides are sub-
Amine (PI), polybenzoxazoles (PBO), benzocyclobutene (BCB) etc..In carrier 1 described in later separation, wet method can be used rotten
Erosion, cmp, the methods of removing, remove the peel ply 11.
In step 2), S2 steps and Fig. 4 in Fig. 1 are referred to, re-wiring layer is formed in the upper surface of the carrier 1
2。
In one example, layer of metal line layer 21 and one layer of dielectric layer 22 are included in the re-wiring layer 2, in described
The upper surface of carrier 1 forms the re-wiring layer 2 and comprised the following steps：
The dielectric layer 22 2-1) is formed in the upper surface of the peel ply 11, by photoetching and etching technics in described
Groove is formed in dielectric layer 22, the groove is defined as the shape of the metal line layer 21；
2-2) in forming the metal line layer 21 in the groove.
In another example, the re-wiring layer 2 includes at least double layer of metal line layer 21 and at least one layer of dielectric layer
22, form the re-wiring layer 2 in the upper surface of the carrier 1 and comprise the following steps：
2-1) first layer metal line layer 21 is formed in the upper surface of the peel ply 11；
The dielectric layer of metal line layer 21 described in one layer of covering first layer 2-2) is formed in the upper surface of the peel ply 11
22；
2-3) in other layer of metal wire that formation electrically connects with metal line layer described in first layer 21 in the dielectric layer 22
Layer 21, electrically connected via metal plug (not shown) between metal line layer 21 described in adjacent two layers.
As an example, in above-mentioned example, the material of the metal line layer 21 can be but be not limited only to copper, aluminium, nickel, gold,
Silver, a kind of material in titanium or two kinds and two or more combined materials, and PVD, CVD, sputtering, plating or chemical plating can be used
The metal line layer 21 is formed etc. technique.The material of the dielectric layer 22 can be low k dielectric；Specifically, the electricity
Dielectric layer 22 can use a kind of material in epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass
Material, and the techniques such as spin coating, CVD, plasma enhanced CVD can be used to form the dielectric layer 22.
As an example, in above-mentioned example, the electricity can be exposed to positioned at the upper surface of the metal line layer 21 of top layer
, i.e., can be with the dielectric layer 22 positioned at the upper surface of the metal line layer 21 of top layer outside the upper surface of dielectric layer 22
Upper surface flush, the top of the upper surface of the dielectric layer 22 can also be protruded from.Certainly, in other examples, it is located at
The upper surface of the metal line layer 21 of top layer can also be less than the upper surface of the dielectric layer 22, i.e., positioned at described in top layer
Metal line layer 21 is located at the inside of the dielectric layer 22.
As an example, in above-mentioned example, the electricity can be exposed to positioned at the lower surface of the metal line layer 21 of bottom
, i.e., can be with the dielectric layer 22 positioned at the lower surface of the metal line layer 21 of bottom outside the lower surface of dielectric layer 22
Lower surface flush, the lower section of the lower surface of the dielectric layer 22 can also be protruded from.Certainly, in other examples, it is located at
The lower surface of the metal line layer 21 of bottom can also be higher than the lower surface of the dielectric layer 22, i.e., positioned at described in bottom
Metal line layer 21 is located at the inside of the dielectric layer 22.
In step 3), S3 steps and Fig. 5 in Fig. 1 are referred to, connection is formed in the upper surface of the re-wiring layer 2
Soldered ball 3, the connection soldered ball 3 electrically connect with the re-wiring layer 2.
As an example, can be by the way of any one existing formation soldered ball 3 in the upper table of the re-wiring layer 2
Face forms the connection soldered ball 3；Preferably, in the present embodiment, using plant ball technique in the upper surface shape of the re-wiring layer 2
Into the connection soldered ball 3.
In step 4), S4 steps and Fig. 6 in Fig. 1 are referred to, first is formed in the upper surface of the re-wiring layer 2
Semiconductor chip 4, first semiconductor chip 4 electrically connect with the re-wiring layer 2；First semiconductor chip 4
Upper surface of the upper surface less than the connection soldered ball 3.
As an example, bonding back tracking method (bond-on-trace) can be used to be bonded to first semiconductor chip 4
The upper surface of the re-wiring layer 2；The bonding back tracking method is described in those skilled in the art, is not repeated herein.Certainly, also may be used
So that first semiconductor chip 4 to be bonded to the upper surface of the re-wiring layer 2 using other any one bonding methods.
As an example, first semiconductor chip 4 can be bonded to the re-wiring layer 2 via solder dimpling block 41
Upper surface；The material of the solder dimpling block 41 can be at least one of copper, nickel, tin and silver.
As an example, the upside-down mounting of the first semiconductor chip 4 is in the upper surface of the re-wiring layer 2, it is described to ensure
The internal structure of first semiconductor chip 4 electrically connects with the re-wiring layer 2.
Addressed on it should be noted that follow-up described " being electrically connected with the re-wiring layer 2 " refer both to it is described again
Metal line layer 21 in wiring layer 2 electrically connects.
It should be further stated that step 3) with that can also be exchanged the step of step 4), i.e., first carries out step except above-mentioned
It is rapid 3) to perform again outside step 4), step 4) can also be first carried out and perform step 3) again, i.e., can also be prior to the rewiring
The upper surface of layer 2 forms first semiconductor chip 4, then forms the company in the upper surface of the re-wiring layer 2 again
Connect soldered ball 3.
In step 5), S5 steps and Fig. 7 to Fig. 8 in Fig. 1 are referred to, in the upper surface shape of the re-wiring layer 2
Into plastic packaging layer 5, gap that the plastic packaging layer 5 is filled up between the connection soldered ball 3 and first semiconductor chip 4, and by institute
State connection soldered ball 3 and the plastic packaging of the first semiconductor chip 4；The upper surface of the plastic packaging layer 5 is not higher than the connection soldered ball 3
Upper surface.
As an example, compressing and forming process, transfer shaping technology, hydraulic seal moulding process, molding bottom can be used
Fill process, capillary underfill technique, vacuum lamination process or spin coating proceeding are formed in the upper surface of the re-wiring layer 2
The plastic packaging layer 5.Preferably, in the present embodiment, using molded underfill technique in the upper surface shape of the re-wiring layer 2
Into the plastic packaging layer 5, such capsulation material can promptly be filled in the connection soldered ball 3 and first semiconductor with smooth
Gap between chip 4, it can be effectively prevented from interface debonding occur, and molded underfill will not be as hair of the prior art
Thin underfill process is restricted like that, is greatly reduced technology difficulty, be can be used for smaller joint gap, be more suitable for
Stacked structure.
As an example, the material of the plastic packaging layer 5 can be but be not limited only to the plastic packaging layer include polyimide layer, silicon
Glue-line, epoxy resin layer, the curable polymeric substrate bed of material or the curable resin base material bed of material.
In one example, the upper surface prior to the re-wiring layer 2 forms the plastic packaging layer 5, and the plastic packaging layer 5 is by institute
State connection soldered ball 3 and first semiconductor chip 4 encapsulates plastic packaging completely, i.e., the upper surface of described plastic packaging layer 5 is higher than the company
The upper surface of soldered ball 3 and first semiconductor chip 4 is connect, as shown in Figure 7；Then gone again using techniques such as cmps
Except the part plastic packaging layer 5 and part the connection soldered ball 3 so that the upper surface of the plastic packaging layer 5 and the connection retained
The upper surface flush of soldered ball 3, and may insure that there are sufficiently large contact area and other keys in the upper surface of the connection soldered ball 3
It is in contact together in semiconductor structure thereon, as shown in Figure 8.
In another example, the plastic packaging layer 5 can be formed according to the height of the connection soldered ball 3 so that the institute of formation
It is just identical with the height of the connection soldered ball 3 to state the height of plastic packaging layer 5, i.e., upper surface and the connection of described plastic packaging layer 5
The upper surface flush of soldered ball 3.The technique being ground to the plastic packaging layer 5 is so may dispense with, so as to save technique
Step.
In step 6), S6 steps and Fig. 9 in Fig. 1 are referred to, removes the carrier 1.
As an example, grinding technics, reduction process etc. can be used to be removed the carrier 1 and the peel ply
11.Preferably, in the present embodiment, use and tear the mode of the peel ply 11 to remove the carrier 1.
In step 7), S7 steps and Figure 10 in Fig. 1 are referred to, weldering is formed in the lower surface of the re-wiring layer 2
Expect projection 6, the solder projection 6 electrically connects with the re-wiring layer 2,
In one example, solder projection 6 is formed in the lower surface of the re-wiring layer 2 to comprise the following steps：
7-1) metal column 61 is formed in the lower surface of the re-wiring layer 2；
7-2) soldered ball 62 is formed in the lower surface of the metal column 61.
As an example, the material of the metal column 61 can be copper, aluminium, nickel, gold, silver, a kind of material in titanium or two kinds
And two or more combined materials, can by physical gas-phase deposition (PVD), chemical vapor deposition method (CVD), splash
Penetrate, electroplate or any of chemical plating technique forms the metal column 61.The material of the soldered ball 62 can be copper, aluminium, nickel,
A kind of material or two kinds and two or more combined materials in gold, silver, titanium, the weldering can be formed by planting ball reflux technique
Ball 62.
In another example, the solder projection 6 is with soldered ball, can directly form soldered ball by planting ball reflux technique
As the solder projection 6.
As an example, refer to Figure 11, after step 7), also it is included in the upper surface bonding the second half of the plastic packaging layer 5
The step of conductor chip 7, second semiconductor chip 7 electrically connect with the connection soldered ball 3.
As an example, second semiconductor chip 7 can be and the identical semiconductor core of the first semiconductor chip 4
Piece, or any one semiconductor chip different from first semiconductor chip 4.Second semiconductor chip 7
Can use Flip Chip Bond Technique via solder dimpling block be bonded to it is described connection soldered ball 3 on, second semiconductor chip 7 via
The connection soldered ball 3 electrically connects with the re-wiring layer 2.
Embodiment two
Please continue to refer to Figure 10, the present embodiment also provides a kind of fan-out-type laminated packaging structure, the fan-out-type lamination envelope
Assembling structure is prepared via the preparation method described in embodiment one, and the fan-out-type laminated packaging structure includes：Again
Wiring layer 2；Connect soldered ball 3, the connection soldered ball 3 is located at the upper surface of the re-wiring layer 2, and with the re-wiring layer
2 electrical connections；First semiconductor chip 4, first semiconductor chip 4 are located at the upper surface of the re-wiring layer 2, and with institute
Re-wiring layer 2 is stated to electrically connect；Plastic packaging layer 5, the plastic packaging layer 5 fill up the connection soldered ball 3 and first semiconductor chip 4
Between gap, and by it is described connection soldered ball 3 and the plastic packaging of the first semiconductor chip 4, the upper surface of the plastic packaging layer 5 it is not high
In the upper surface of the connection soldered ball 3；Solder projection 6, the solder projection 6 are located at the lower surface of the re-wiring layer 2, and
Electrically connected with the re-wiring layer 2.
In one example, the re-wiring layer 2 includes：Dielectric layer 22；Metal line layer 21, the metal line layer 21
In in the dielectric layer 22, and the upper surface of the metal line layer 21 and the upper surface flush of the dielectric layer 22, institute
State the lower surface of metal line layer 21 and the lower surface flush of the dielectric layer 22.Certainly, in other examples, the metal
Line layer 21 can also be fully located in the dielectric layer 22.
In another example, the re-wiring layer 2 includes：Dielectric layer 22；Metallic stacked structure, it is described metal laminated
Structure is located in the dielectric layer 22；The metallic stacked structure includes the metal line layer 21 of Spaced arrangement and metal is inserted
Metal line layer described in adjacent two layers 21 is electrically connected by plug, the metal plug between metal line layer 21 described in adjacent two layers
Connect.
Addressed on it should be noted that follow-up described " being electrically connected with the re-wiring layer 2 " refer both to it is described again
Metal line layer 21 in wiring layer 2 electrically connects.
As an example, in above-mentioned example, the material of the metal line layer 21 can be but be not limited only to copper, aluminium, nickel, gold,
Silver, a kind of material in titanium or two kinds and two or more combined materials, and PVD, CVD, sputtering, plating or chemical plating can be used
The metal line layer 21 is formed etc. technique.The material of the dielectric layer 22 can be low k dielectric；Specifically, the electricity
Dielectric layer 22 can use a kind of material in epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass
Material, and the techniques such as spin coating, CVD, plasma enhanced CVD can be used to form the dielectric layer 22.
As an example, the material of the plastic packaging layer 5 can be but be not limited only to the plastic packaging layer include polyimide layer, silicon
Glue-line, epoxy resin layer, the curable polymeric substrate bed of material or the curable resin base material bed of material.
As an example, the upper surface of the plastic packaging layer 5 and the upper surface flush of the connection soldered ball 3.
In one example, the soldered ball projection 6 includes：Metal column 61, the metal column 61 are located at the re-wiring layer 2
Lower surface, and electrically connected with the re-wiring layer 2；Soldered ball 62, the soldered ball 62 are located at the lower surface of the metal column 61.
The material of the metal column 61 can be copper, aluminium, nickel, gold, silver, a kind of material in titanium or two kinds and two or more combination materials
Material, can be by physical gas-phase deposition (PVD), chemical vapor deposition method (CVD), sputtering, plating or chemical plating
Any technique forms the metal column 61.The material of the soldered ball 62 can be a kind of material in copper, aluminium, nickel, gold, silver, titanium
Material or two kinds and two or more combined materials, can form the soldered ball 62 by planting ball reflux technique.
In another example, the soldered ball projection 6 is soldered ball.
As an example, please continue to refer to Figure 11, the fan-out-type laminated packaging structure also includes the second semiconductor chip 7,
Second semiconductor chip 7 is located at the upper surface of the plastic packaging layer 5, and is electrically connected with the connection soldered ball 3.
As an example, second semiconductor chip 7 can be and the identical semiconductor core of the first semiconductor chip 4
Piece, or any one semiconductor chip different from first semiconductor chip 4.Second semiconductor chip 7
Can use Flip Chip Bond Technique via solder dimpling block be bonded to it is described connection soldered ball 3 on, second semiconductor chip 7 via
The connection soldered ball 3 electrically connects with the re-wiring layer 2.
In summary, fan-out-type laminated packaging structure of the present utility model, the preparation of the fan-out-type laminated packaging structure
Method comprises the following steps：1) carrier is provided；2) re-wiring layer is formed in the upper surface of the carrier；3) in it is described again
The upper surface of wiring layer forms connection soldered ball, and the connection soldered ball electrically connects with the re-wiring layer；4) in the cloth again
The upper surface of line layer forms the first semiconductor chip, and first semiconductor chip electrically connects with the re-wiring layer；It is described
Upper surface of the upper surface of first semiconductor chip less than the connection soldered ball；5) formed in the upper surface of the re-wiring layer
Plastic packaging layer, the gap that the plastic packaging layer is filled up between the connection soldered ball and first semiconductor chip, and by the connection
Soldered ball and the first semiconductor chip plastic packaging；Upper surface of the upper surface of the plastic packaging layer not higher than the connection soldered ball；6)
Remove the carrier；7) solder projection, the solder projection and the cloth again are formed in the lower surface of the re-wiring layer
Line layer electrically connects.The utility model uses connecting pole of the connection soldered ball as connection re-wiring layer in plastic packaging layer, connects soldered ball
The plant ball technique that technics comparing can be used ripe is directly formed, and technique is simple, cost is relatively low.
Above-described embodiment only illustrative principle of the present utility model and its effect are new not for this practicality is limited
Type.Any person skilled in the art can all be carried out without prejudice under spirit and scope of the present utility model to above-described embodiment
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the essence disclosed in the utility model
God and all equivalent modifications completed under technological thought or change, should be covered by claim of the present utility model.
Claims (8)
1. a kind of fan-out-type laminated packaging structure, it is characterised in that the fan-out-type laminated packaging structure includes：
Re-wiring layer；
Soldered ball is connected, is electrically connected positioned at the upper surface of the re-wiring layer, and with the re-wiring layer；
First semiconductor chip, electrically connected positioned at the upper surface of the re-wiring layer, and with the re-wiring layer；
Plastic packaging layer, fill up it is described connection soldered ball and first semiconductor chip between gap, and by it is described connection soldered ball and
The first semiconductor chip plastic packaging, the upper surface of the plastic packaging layer is not higher than the upper surface for connecting soldered ball；
Solder projection, electrically connected positioned at the lower surface of the re-wiring layer, and with the re-wiring layer.
2. fan-out-type laminated packaging structure according to claim 1, it is characterised in that the re-wiring layer includes：
Dielectric layer；
Metal line layer, in the dielectric layer, and the upper surface of the metal line layer and the upper surface of the dielectric layer
Flush, the lower surface of the metal line layer and the lower surface flush of the dielectric layer.
3. fan-out-type laminated packaging structure according to claim 1, it is characterised in that the re-wiring layer includes：
Dielectric layer；
Metallic stacked structure, in the dielectric layer；The metallic stacked structure includes the metal wire of Spaced arrangement
The adjacent metal line layer is electrically connected by layer and metal plug, the metal plug between the adjacent metal line layer
Connect.
4. fan-out-type laminated packaging structure according to claim 1, it is characterised in that the upper surface of the plastic packaging layer and institute
State the upper surface flush of connection soldered ball.
5. fan-out-type laminated packaging structure according to claim 1, it is characterised in that the plastic packaging layer includes polyimides
Layer, layer of silica gel, epoxy resin layer, the curable polymeric substrate bed of material or the curable resin base material bed of material.
6. fan-out-type laminated packaging structure according to claim 1, it is characterised in that the soldered ball projection includes：
Metal column, electrically connected positioned at the lower surface of the re-wiring layer, and with the re-wiring layer；
Soldered ball, positioned at the lower surface of the metal column.
7. fan-out-type laminated packaging structure according to claim 1, it is characterised in that the solder projection is soldered ball.
8. fan-out-type laminated packaging structure according to any one of claim 1 to 7, it is characterised in that the fan-out-type
Laminated packaging structure also includes the second semiconductor chip, and second semiconductor chip is located at the upper surface of the plastic packaging layer, and
Electrically connected with the connection soldered ball.
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| CN201720806310.1U CN206931596U (en) | 2017-07-05 | 2017-07-05 | Fan-out-type laminated packaging structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107195551A (en) * | 2017-07-05 | 2017-09-22 | 中芯长电半导体（江阴）有限公司 | Fan-out-type laminated packaging structure and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107195551A (en) * | 2017-07-05 | 2017-09-22 | 中芯长电半导体（江阴）有限公司 | Fan-out-type laminated packaging structure and preparation method thereof |
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Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |
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