CN107359144A - System-level fan-out package structures of 3D and preparation method thereof - Google Patents
System-level fan-out package structures of 3D and preparation method thereof Download PDFInfo
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- CN107359144A CN107359144A CN201710651755.1A CN201710651755A CN107359144A CN 107359144 A CN107359144 A CN 107359144A CN 201710651755 A CN201710651755 A CN 201710651755A CN 107359144 A CN107359144 A CN 107359144A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention provides a kind of system-level fan-out package structures of 3D and preparation method thereof, and the system-level fan-out package structures of 3D include：Re-wiring layer；First semiconductor chip, face down back bonding is in the upper surface of re-wiring layer；Second semiconductor chip, face-up it is bonded to the back side of the first semiconductor chip；Capsulation material layer, positioned at the upper surface of re-wiring layer；Solder projection, positioned at the lower surface of re-wiring layer.The present invention the system-level fan-out package structures of 3D be by by the second semiconductor chip back bonding in the back side of the first semiconductor chip, and the structure 3D encapsulating structures of formation are encapsulated together with the first semiconductor chip, the encapsulating structure is due to being packaged with two semiconductor chips, the input/output end port of encapsulating structure is considerably increased, effectively reduces the size of encapsulating structure.
Description
Technical field
The present invention relates to a kind of semiconductor package and method for packing, is sealed more particularly to a kind of system-level fan-out-types of 3D
Assembling structure and preparation method thereof.
Background technology
It is more inexpensive, more reliable, faster and more highdensity circuit be integrated antenna package pursue target.In future,
Integrated antenna package will improve the integration density of various electronic components by constantly reducing minimum feature size.At present, first
The method for packing entered includes：Wafer chip level chip-scale package (Wafer Level Chip Scale Packaging,
WLCSP), fan-out-type wafer-level packaging (Fan-Out Wafer Level Package, FOWLP), flip-chip (Flip
Chip), stacked package (Package on Package, POP) etc..
Fan-out-type wafer-level packaging is a kind of embedded chip method for packing of wafer level processing, be current a kind of input/
One of preferable Advanced Packaging method of more, the integrated flexibility of output port (I/O).Fan-out-type wafer-level packaging is compared to routine
Wafer-level packaging have its it is unique the advantages of：1. I/O spacing is flexible, independent of chip size；2. only use effective nude film
(die), product yield improves；3. there is flexible 3D package paths, you can to form the figure of General Cell at top；4. have
There are preferable electrical property and hot property；5. frequency applications；6. easily realize high-density wiring in re-wiring layer (RDL).Mesh
Before, fan-out-type wafer-level packaging method is generally：Substrate is provided, adhesive layer is formed in substrate surface；Photoetching, electricity on adhesive layer
Plate out re-wiring layer (Redistribution Layers, RDL)；Semiconductor chip is installed to using chip bonding process
On re-wiring layer；Using Shooting Technique by semiconductor chip plastic packaging in capsulation material layer；Remove substrate and adhesive layer；In weight
Photoetching, plating form Underbump metallization layer (UBM) on new route layer；Carry out planting ball backflow on UBM, form solder projection.When
The defects of input/output end port is insufficient and encapsulating structure size is larger be present in above-mentioned fan-out-type wafer level packaging structure.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of system-level fan-out packages of 3D
Structure and preparation method thereof, for solving input/output end port existing for fan-out-type wafer level packaging structure of the prior art
The larger-size problem of insufficient and encapsulating structure.
In order to achieve the above objects and other related objects, the present invention provides a kind of system-level fan-out package structures of 3D, institute
Stating the system-level fan-out package structures of 3D includes：
Re-wiring layer；
First semiconductor chip, face down back bonding in the upper surface of the re-wiring layer, and with it is described again
Wiring layer electrically connects；
Second semiconductor chip, is face-up bonded to the back side of first semiconductor chip, and with the cloth again
Line layer electrically connects；
Capsulation material layer, positioned at the upper surface of the re-wiring layer, and by first semiconductor chip and described
Two semiconductor chips encapsulate plastic packaging；
Solder projection, electrically connected positioned at the lower surface of the re-wiring layer, and with the re-wiring layer.
Preferably, the system-level fan-out package structures of the 3D also include：
First dielectric layer, between the re-wiring layer and the solder projection；
Post is conductively connected, in first dielectric layer, and runs through first dielectric layer up and down；The conduction
The top of connecting pole electrically connects with the re-wiring layer, and the bottom for being conductively connected post electrically connects with the solder projection.
Preferably, the re-wiring layer includes：
Second dielectric layer；
Metal line layer, in second dielectric layer.
Preferably, the re-wiring layer includes：
Second dielectric layer；
Metallic stacked structure, in second dielectric layer；The metallic stacked structure is arranged including Spaced
Metal line layer and metal plug, the metal plug is between the adjacent metal line layer, by the adjacent metal
Line layer electrically connects.
Preferably, the material of second dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorus silicon
One or both of glass, fluorine-containing glass combination of the above, the material of the metal line layer are included in copper, aluminium, nickel, gold, silver, titanium
One or more kinds of combinations.
Preferably, the system-level fan-out package structures of the 3D also include metal connecting line, the second semiconductor chip warp
Electrically connected by the metal connecting line with the re-wiring layer, the capsulation material layer is by first semiconductor chip, described
Second semiconductor chip and metal connecting line enveloping plastic packaging.
Preferably, the capsulation material layer includes polyimide layer, layer of silica gel, epoxy resin layer, curable polymer
Any of based material layer or the curable resin base material bed of material.
Preferably, the solder projection is soldered ball.
The present invention also provides a kind of 3D preparation methods of system-level fan-out package structure, the system-level fan-out-type envelopes of 3D
The preparation method of assembling structure comprises the following steps：
1) substrate is provided；
2) re-wiring layer is formed in the upper surface of the substrate；
3) the first semiconductor chip, the front of first semiconductor chip are bonded in the upper surface of the re-wiring layer
Electrically connected towards the re-wiring layer, and with the re-wiring layer；
4) the second semiconductor chip is bonded in the back side of first semiconductor chip, second semiconductor chip is just
Face deviates from first semiconductor chip, and second semiconductor chip electrically connects with the re-wiring layer；
5) capsulation material layer is formed in the upper surface of the re-wiring layer, the capsulation material layer is led described the first half
Body chip and second semiconductor chip enveloping plastic packaging；
6) substrate is removed；
7) solder projection, the solder projection and re-wiring layer electricity are formed in the lower surface of the re-wiring layer
Connection.
Preferably, also comprise the following steps between step 1) and step 2)：
The first dielectric layer is formed in the upper surface of the substrate；
In the through hole that several up/down perforations are formed in first dielectric layer；
Post is conductively connected in being formed in the through hole.
Preferably, also it is included in the upper of the substrate before the upper surface of the substrate forms first dielectric layer
Surface forms the step of peel ply.
Preferably, step 2) comprises the following steps：
2-1) metal line layer is formed in the upper surface of the substrate；
The second dielectric layer 2-2) is formed in the upper surface of the substrate, second dielectric layer is by the metal line layer
Parcel.
Preferably, step 2) comprises the following steps：
2-1) first layer metal line layer is formed in the upper surface of the substrate；
The second dielectric layer 2-2) is formed in the upper surface of the substrate, second dielectric layer will be golden described in first layer
Belong to the enveloping of line layer, and the upper surface of second dielectric layer is higher than the upper surface of the metal line layer；
2-3) in the interval heap that if formation dried layer electrically connects with metal line layer described in first layer in second dielectric layer
Other metal line layers of arrangement are folded, are electrically connected between the adjacent metal line layer via metal plug.
Preferably, step 4) comprises the following steps：
Second semiconductor chip 4-1) is provided；
Second semiconductor chip 4-2) is face-up bonded to the back side of first semiconductor chip, described
The back side of two semiconductor chips and the back side of first semiconductor chip are bonding face；
Metal connecting line 4-3) is formed, one end of the metal connecting line electrically connects with second semiconductor chip, the other end
Electrically connected with the re-wiring layer.
Preferably, in step 5), using compressing and forming process, Transfer molding technique, fluid-tight moulding process, vacuum layer
Pressure technique or spin coating proceeding form the capsulation material layer in the upper surface of the re-wiring layer；The capsulation material layer includes
In polyimide layer, layer of silica gel, epoxy resin layer, the curable polymeric substrate bed of material or the curable resin base material bed of material
It is any.
As described above, system-level fan-out package structures of 3D of the present invention and preparation method thereof, have the advantages that：
The present invention the system-level fan-out package structures of 3D be by by the second semiconductor chip back bonding in the first semiconductor chip
The back side, and encapsulate together with the first semiconductor chip the structure 3D encapsulating structures of formation, the encapsulating structure is due to being packaged with
Two semiconductor chips, considerably increase the input/output end port of encapsulating structure；Simultaneously as the second semiconductor chip upside-down mounting
It is bonded to the back side of the first semiconductor chip so that do not have spacing between the first semiconductor chip and the second semiconductor chip, have
Effect reduces the size of encapsulating structure；In addition, the second semiconductor chip is electrically connected by metal connecting line with re-wiring layer, do not relate to
And the silicon perforation technique of high cost, greatly reduce technology difficulty and cost.
Brief description of the drawings
Fig. 1 is shown as the flow of the preparation method of the system-level fan-out package structures of 3D provided in the embodiment of the present invention one
Figure.
Fig. 2~Figure 11 is shown as the preparation method of the system-level fan-out package structures of 3D provided in the embodiment of the present invention one
The structural representation that each step is presented, wherein, Figure 11 is shown as the structure of the system-level fan-out package structures of 3D of the present invention
Schematic diagram.
Component label instructions
11 substrates
12 peel plies
13 first dielectric layers
14 are conductively connected post
15 re-wiring layers
151 second dielectric layers
152 metal line layers
16 first semiconductor chips
161 contact pads
17 solder dimpling blocks
18 second semiconductor chips
181 contact pads
19 bonded layers
20 capsulation material layers
21 metal connecting lines
22 solder projections
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Refer to Fig. 1~Figure 11.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only showing the component relevant with the present invention in diagram rather than according to package count during actual implement
Mesh, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout form may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the present invention provides a kind of preparation method of the system-level fan-out package structures of 3D, the 3D is system-level
The preparation method of fan-out package structure comprises the following steps：
1) substrate is provided；
2) re-wiring layer is formed in the upper surface of the substrate；
3) the first semiconductor chip, the front of first semiconductor chip are bonded in the upper surface of the re-wiring layer
Electrically connected towards the re-wiring layer, and with the re-wiring layer；
4) the second semiconductor chip is bonded in the back side of first semiconductor chip, second semiconductor chip is just
Face deviates from first semiconductor chip, and second semiconductor chip electrically connects with the re-wiring layer；
5) capsulation material layer is formed in the upper surface of the re-wiring layer, the capsulation material layer is led described the first half
Body chip and second semiconductor chip enveloping plastic packaging；
6) substrate is removed；
7) solder projection, the solder projection and re-wiring layer electricity are formed in the lower surface of the re-wiring layer
Connection.
In step 1), S1 steps and Fig. 2 in Fig. 1 are referred to, there is provided a substrate 11.
As an example, the material of the substrate 11 can include in silicon, glass, silica, ceramics, polymer and metal
One or more kinds of composites, its shape can be wafer shape, it is square or it is other it is any needed for shape；The present embodiment
The problems such as rupture, warpage, fracture occur for semiconductor chip in subsequent preparation process is prevented by the substrate 11.
As an example, as shown in Figure 3, there is provided after the substrate 11, the upper surface for being also included in the substrate 11 is formed
The step of peel ply 12.
As an example, the peel ply 12 in subsequent technique as the first dielectric layer 13 being subsequently formed and positioned at institute
The separating layer between other structures and the substrate 11 on the first dielectric layer 13 is stated, it is preferably selected with smooth finish surface
Jointing material is made, and it must have certain adhesion with the first dielectric layer 13, to ensure the first dielectric layer 13 rear
Situations such as mobile will not be produced in continuous technique, in addition, it also has stronger adhesion with the substrate 11, in general, its
Need to be more than the adhesion with first dielectric layer 13 with the adhesion of the substrate 11.As an example, the peel ply
12 material is selected from the two-sided adhesive tape for being respectively provided with viscosity or the adhesive glue made by spin coating proceeding etc..Adhesive tape preferably uses UV glue
Band, it is easy to pull off after UV light irradiations.In other embodiments, the peel ply 12 also can be selected physical vapor and sink
The other materials layer that area method or chemical vapour deposition technique are formed, such as epoxy resin (Epoxy), silicon rubber (silicone
Rubber), polyimides (PI), polybenzoxazoles (PBO), benzocyclobutene (BCB) etc..In substrate 11 described in later separation
When, wet etching, cmp, the methods of removing can be used to remove the peel ply 12.
As an example, as shown in figure 4, after forming the peel ply 12 in the surface of the substrate 11, in addition to it is as follows
Step：
The first dielectric layer 13 is formed in the upper surface of the substrate 11；
(do not shown in the through hole that several up/down perforations are formed in first dielectric layer 13 using lithographic etch process
Go out)；
Post 14 is conductively connected in being formed in the through hole.
As an example, it can use but be not limited only to physical gas-phase deposition or chemical vapor deposition method is in the lining
The upper surface at bottom 11 forms first dielectric layer 13, and the material of first dielectric layer 13 can be but be not limited only to oxygen
One or both of resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, fluorine-containing glass combination of the above.
As an example, the post 14 that is conductively connected can be that any one conductive material being filled in the through hole is formed
Structure, the material for being conductively connected post 14 can be conducting resinl, or one kind in copper, aluminium, nickel, gold, silver, titanium or
Two or more combinations.
S2 steps and Fig. 5 in Fig. 1 are referred to, re-wiring layer 15 is formed in the upper surface of the substrate 11.
In one example, as shown in figure 5, the re-wiring layer 1 includes one layer of second dielectric layer 151 and layer of metal
Line layer 152, form the re-wiring layer 15 in the upper surface of the substrate 11 and comprise the following steps：
2-1) metal line layer 15 is formed in the upper surface of the substrate 11；
The second dielectric layer 151 2-2) is formed in the upper surface of the substrate 11, second dielectric layer 151 is by described in
Metal line layer 152 wraps up.
In another example, the re-wiring layer 1 includes one layer of second dielectric layer 151 and layer of metal line layer 152,
Re-wiring layer 15 is formed in the upper surface of the substrate 11 to comprise the following steps：
2-1) form second dielectric layer 151 in the upper surface of the substrate 11, by photoetching and etching technics in
Groove is formed in second dielectric layer 151, the groove defines the shape of the metal line layer 152；
2-2) in forming the metal line layer 152 in the groove.
Include at least double layer of metal line layer 152 and at least one layer second in another example, in the re-wiring layer 15
Dielectric layer 151, form re-wiring layer 15 in the upper surface of the substrate 11 and comprise the following steps：
2-1) first layer metal line layer 152 is formed in the upper surface of the substrate 11；
The second dielectric layer 151 2-2) is formed in the upper surface of the substrate 11, second dielectric layer 151 is by first
The layer metal line layer 152 encapsulates, and the upper surface of second dielectric layer 151 is higher than the upper table of the metal line layer 152
Face；
If 2-3) electrically connected in formation dried layer in second dielectric layer 151 with metal line layer described in first layer 152
Other metal line layers 152 of stacked spaced apart arrangement, are electrically connected via metal plug between the adjacent metal line layer 152.
First dielectric layer is provided between the re-wiring layer 15 and the substrate 11 it should be noted that working as
13 and it is described the re-wiring layer 15 is located at the upper surface of first dielectric layer 13 when being conductively connected post 14, i.e., it is described
First dielectric layer 13 and the post 14 that is conductively connected are between the re-wiring layer 15 and the substrate 11.
As an example, in above-mentioned example, the material of the metal line layer 152 can be but be not limited only to copper, aluminium, nickel, gold,
Silver, a kind of material in titanium or two kinds and two or more combined materials, and PVD, CVD, sputtering, plating or chemical plating can be used
The metal line layer 152 is formed etc. technique.The material of second dielectric layer 151 can be low k dielectric；Specifically,
Second dielectric layer 151 can use epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass
In a kind of material, and the technique such as spin coating, CVD, plasma enhanced CVD can be used to form second dielectric layer
151。
As an example, in above-mentioned example, described the can be exposed to positioned at the upper surface of the metal line layer 152 of top layer
, i.e., can be with the described second electricity positioned at the upper surface of the metal line layer 152 of top layer outside the upper surface of two dielectric layers 151
The upper surface flush of dielectric layer 151, the top of the upper surface of second dielectric layer 151 can also be protruded from.Certainly, exist
In other examples, the upper of second dielectric layer 151 can also be less than positioned at the upper surface of the metal line layer 152 of top layer
Surface, the i.e. metal line layer 152 positioned at top layer are located at the inside of second dielectric layer 151.
As an example, in above-mentioned example, described the can be exposed to positioned at the lower surface of the metal line layer 152 of bottom
, i.e., can be with the described second electricity positioned at the lower surface of the metal line layer 152 of bottom outside the lower surface of two dielectric layers 151
The lower surface flush of dielectric layer 151, the lower section of the lower surface of second dielectric layer 151 can also be protruded from.Certainly, exist
In other examples, it can also be higher than positioned at the lower surface of the metal line layer 152 of bottom under second dielectric layer 151
Surface, the i.e. metal line layer 152 positioned at bottom are located at the inside of second dielectric layer 151.
In step 3), S3 steps and Fig. 6 in Fig. 1 are referred to, in the rewiring, 15 upper surface bonding first
Semiconductor chip 16, first semiconductor chip 16 just facing to the re-wiring layer 15, and with the rewiring
Layer 15 electrically connects.
As an example, bonding back tracking method (bond-on-trace) can be used to be bonded first semiconductor chip 16
In the upper surface of the re-wiring layer 15；The bonding back tracking method is known to those skilled in the art, is not repeated herein.When
So, first semiconductor chip 16 can also be bonded to using other any one bonding methods in the present embodiment described heavy
The upper surface of new route layer 15.
As an example, the front of first semiconductor chip 16 is formed with the contact for drawing its inside function device electricity
Weld pad 161, the back bonding of the first semiconductor chip 16 is in the upper surface of the re-wiring layer 15, and described the first half lead
The contact pad 161 of body chip 16 electrically connects with the re-wiring layer 15.Specifically, first semiconductor chip 16 can be with
The upper surface of the re-wiring layer 15 is bonded to via solder dimpling block 17；The material of the solder dimpling block 17 can be
At least one of copper, nickel, tin and silver.
Addressed on it should be noted that follow-up described " being electrically connected with the re-wiring layer 15 " refer both to it is described again
Metal line layer 152 in wiring layer 15 electrically connects.
In step 4), Fig. 1 S4 steps and Fig. 7 to Fig. 8 are referred to, in the back side key of first semiconductor chip 16
The second semiconductor chip 18 is closed, the front of second semiconductor chip 18 deviates from first semiconductor chip 16, and described
Second semiconductor chip 18 electrically connects with the re-wiring layer 15.
As an example, being bonded the second semiconductor chip 18 in the back side of first semiconductor chip 16 includes following step
Suddenly：
Second semiconductor chip 18 4-1) is provided；
Second semiconductor chip 18 4-2) is face-up bonded to the back side of first semiconductor chip 16, institute
It is bonding face that the back side of the second semiconductor chip 18, which is stated, with the back side of first semiconductor chip 16；Specifically, it can pass through
Second semiconductor chip 18 is bonded to the back side of first semiconductor chip 16, the bonded layer 19 by one bonded layer 19
Can be adhesion layer, glue-line or solder layer etc.；
Metal connecting line 21 4-3) is formed, one end of the metal connecting line 21 electrically connects with second semiconductor chip 18,
The other end electrically connects with the re-wiring layer 15, as shown in Figure 8.
As an example, the front of second semiconductor chip 18 is formed with the contact for drawing its inside function device electricity
Weld pad 181, one end of the metal connecting line 21 electrically connect with the contact pad 181 of second semiconductor chip 18.
As an example, second semiconductor chip 18 can be and the function identical core of the first semiconductor chip 16
Piece, or the chip different from the function of the first semiconductor chip 16, do not limit herein.
As an example, the metal connecting line 21 can be the metal connecting line of any one metal material, it is preferable that this implementation
In example, the material of the metal connecting line 21 can be copper, silver, nickel, aluminium or tin etc..
In step 5), Fig. 1 S5 steps and Fig. 9 are referred to, plastic packaging is formed in the upper surface of the re-wiring layer 15
First semiconductor chip 16 and second semiconductor chip 18 are encapsulated plastic packaging by material layer 20, the capsulation material layer 20
As an example, compressing and forming process, transfer shaping technology, hydraulic seal moulding process, molding bottom can be used
Fill process, capillary underfill technique, vacuum lamination process or spin coating proceeding are in the upper surface shape of the re-wiring layer 15
Into the capsulation material layer 20.Preferably, in the present embodiment, using molded underfill technique in the re-wiring layer 15
Upper surface forms the capsulation material layer 20, and such capsulation material can promptly be filled in first semiconductor core with smooth
Gap between piece 16, second semiconductor chip 18 and the metal connecting line 21, it can be effectively prevented from interface point occur
Layer, and molded underfill will not be restricted as capillary underfill technique of the prior art, greatly reduce work
Skill difficulty, it can be used for smaller joint gap, be more suitable for stacked structure.
As an example, the material of the capsulation material layer 20 can be but be not limited only to polyimide layer, layer of silica gel, epoxy
Resin bed, the curable polymeric substrate bed of material or the curable resin base material bed of material.
In one example, the height of the capsulation material layer 20 is higher than the height of the metal connecting line 21, i.e., described plastic packaging
Material layer 20 moulds the enveloping completely of the metal connecting line 21, first semiconductor chip 16 and second semiconductor chip 18
Envelope；Then, then using techniques such as cmps remove the part capsulation material layer 20 so that the capsulation material layer 20
Upper surface and the metal connecting line 21 top flush.
Can be that foundation forms the capsulation material layer 20 according to the top of the metal connecting line 21 in another example,
So that the height of the capsulation material layer 20 formed is just identical with the height of the metal connecting line 21.It can so save pair
The technique that the capsulation material layer 20 is ground, so as to reduce processing step, has saved cost.
In step 6), S6 steps and Figure 10 in Fig. 1 are referred to, removes the substrate 11.
As an example, grinding technics, reduction process etc. can be used to be removed the substrate 11 and the peel ply 12.
Preferably, in the present embodiment, the peel ply 12 is UV adhesive tapes, can use the mode for tearing the peel ply 12 to remove
State substrate 11.
In step 7), S7 steps and Figure 11 in Fig. 1 are referred to, weldering is formed in the lower surface of the re-wiring layer 15
Expect projection 22, the solder projection 22 electrically connects with the re-wiring layer 15.
In one example, solder projection 22 is formed in the lower surface of the re-wiring layer 15 to comprise the following steps：
7-1) metal column is formed in the lower surface of the re-wiring layer 15；
7-2) soldered ball is formed in the lower surface of the metal column.
As an example, the material of the metal column can be copper, aluminium, nickel, gold, silver, a kind of material in titanium or two kinds and
Two or more combined materials, can by physical gas-phase deposition (PVD), chemical vapor deposition method (CVD), sputtering,
Any of plating or chemical plating technique form the metal column.The material of the soldered ball can be copper, aluminium, nickel, gold, silver,
A kind of material or two kinds and two or more combined materials in titanium, the soldered ball can be formed by planting ball reflux technique.
In another example, the solder projection 22 is a soldered ball, can directly form weldering by planting ball reflux technique
Ball is as the solder projection 22.
It should be noted that when the lower surface of the re-wiring layer 15 is formed with first dielectric layer 13 and described
When being conductively connected post 14, the solder projection 22 is located at first dielectric layer 13 and the following table for being conductively connected post 14
Face, and the solder projection 22 electrically connects via the post 14 that is conductively connected with the re-wiring layer 15.
Embodiment two
Please continue to refer to Figure 11, the present embodiment also provides a kind of system-level fan-out package structures of 3D, and the 3D is system-level
Fan-out package structure is prepared by the preparation method described in embodiment one, the system-level fan-out package structures of 3D
Including：Re-wiring layer 15；First semiconductor chip 16, the face down back bonding of the first semiconductor chip 16 is in described
The upper surface of re-wiring layer 15, and electrically connected with the re-wiring layer 15；Second semiconductor chip 18, described the second half lead
Body chip 18 is face-up bonded to the back side of first semiconductor chip 16, and is electrically connected with the re-wiring layer 15；
Capsulation material layer 20, the capsulation material layer 20 are located at the upper surface of the re-wiring layer 15, and by first semiconductor
Chip 16 and second semiconductor chip 18 enveloping plastic packaging；Solder projection 22, the solder projection 22 is positioned at the cloth again
The lower surface of line layer 15, and electrically connected with the re-wiring layer 15.
As an example, the system-level fan-out package structures of 3D also include：First dielectric layer 13, first electricity are situated between
Matter layer 13 is between the re-wiring layer 15 and the solder projection 22；Post 14 is conductively connected, it is described to be conductively connected post 14
In first dielectric layer 13, and run through first dielectric layer 13 up and down；The top for being conductively connected post 14
Electrically connected with the re-wiring layer 15, the bottom for being conductively connected post 14 electrically connects with the solder projection 22.
As an example, it can use but be not limited only to physical gas-phase deposition or chemical vapor deposition method is in the lining
The upper surface at bottom 11 forms first dielectric layer 13, and the material of first dielectric layer 13 can be but be not limited only to oxygen
One or both of resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, fluorine-containing glass combination of the above.
As an example, the post 14 that is conductively connected can be that any one conductive material being filled in the through hole is formed
Structure, the material for being conductively connected post 14 can be conducting resinl, or one kind in copper, aluminium, nickel, gold, silver, titanium or
Two or more combinations.
In one example, the re-wiring layer 15 includes：Second dielectric layer 151；Metal line layer 152, the metal
Line layer 152 is located in second dielectric layer 151.
In another example, the re-wiring layer 15 includes：Second dielectric layer 151；Metallic stacked structure, the gold
Category laminated construction is located in second dielectric layer 151；The metallic stacked structure includes the metal wire of Spaced arrangement
Layer 152 and metal plug, the metal plug is between the adjacent metal line layer 152, by the adjacent metal wire
Layer 152 electrically connects.
Addressed on it should be noted that follow-up described " being electrically connected with the re-wiring layer 15 " refer both to it is described again
Metal line layer 152 in wiring layer 15 electrically connects.
As an example, the material of second dielectric layer 151 includes epoxy resin, silica gel, PI, PBO, BCB, oxidation
One or both of silicon, phosphorosilicate glass, fluorine-containing glass combination of the above, the material of the metal line layer 152 include copper, aluminium, nickel,
One or both of gold, silver, titanium combination of the above.
As an example, the front of first semiconductor chip 16 is formed with the contact for drawing its inside function device electricity
Weld pad 161, the back bonding of the first semiconductor chip 16 is in the upper surface of the re-wiring layer 15, and described the first half lead
The contact pad 161 of body chip 16 electrically connects with the re-wiring layer 15.Specifically, first semiconductor chip 16 can be with
The upper surface of the re-wiring layer 15 is bonded to via solder dimpling block 17；The material of the solder dimpling block 17 can be
At least one of copper, nickel, tin and silver.
As an example, the system-level fan-out package structures of 3D also include bonded layer 19, the bonded layer 19 is located at institute
State between the first semiconductor chip 16 and second semiconductor chip 18, by first semiconductor chip 16 and described the
Two semiconductor chips 18 are bonded.
As an example, the system-level fan-out package structures of 3D also include metal connecting line 1, second semiconductor chip
18 electrically connect via the metal connecting line 21 with the re-wiring layer 15, and the capsulation material layer 20 is by first semiconductor
Chip 16, second semiconductor chip 18 and the metal connecting line 21 encapsulate plastic packaging.
As an example, the metal connecting line 21 can be the metal connecting line of any one metal material, it is preferable that this implementation
In example, the material of the metal connecting line 21 can be copper, silver, nickel, aluminium or tin etc..
As an example, the front of second semiconductor chip 18 is formed with the contact for drawing its inside function device electricity
Weld pad 181, one end of the metal connecting line 21 electrically connect with the contact pad 181 of second semiconductor chip 18.
As an example, second semiconductor chip 18 can be and the function identical core of the first semiconductor chip 16
Piece, or the chip different from the function of the first semiconductor chip 16, do not limit herein.
As an example, the capsulation material layer 20 includes polyimide layer, layer of silica gel, epoxy resin layer, curable poly-
Any of compound based material layer or the curable resin base material bed of material.
In one example, the solder projection 22 includes：Metal column, the metal column are located at the re-wiring layer 15
Lower surface, and electrically connected with the re-wiring layer 15；Soldered ball, the soldered ball are located at the lower surface of the metal column.The gold
The material for belonging to post can be copper, aluminium, nickel, gold, silver, a kind of material in titanium or two kinds and two or more combined materials, can be with
Pass through any of physical gas-phase deposition (PVD), chemical vapor deposition method (CVD), sputtering, plating or chemical plating work
Skill forms the metal column.The material of the soldered ball can be copper, aluminium, nickel, gold, silver, a kind of material in titanium or two kinds and two
The combined material of the kind above, can form the soldered ball by planting ball reflux technique.
In another example, the solder projection 22 is soldered ball.
In summary, system-level fan-out package structure of 3D of the invention and preparation method thereof, the 3D is system-level to be fanned out to
Type encapsulating structure includes：Re-wiring layer；First semiconductor chip, face down back bonding are upper in the re-wiring layer
Surface, and electrically connected with the re-wiring layer；Second semiconductor chip, face-up it is bonded to first semiconductor chip
The back side, and electrically connected with the re-wiring layer；Capsulation material layer, positioned at the upper surface of the re-wiring layer, and by institute
State the first semiconductor chip and second semiconductor chip enveloping plastic packaging；Solder projection, under the re-wiring layer
Surface, and electrically connected with the re-wiring layer.The system-level fan-out package structures of 3D of the present invention are by the way that the second half are led
Body flip-chip is bonded to the back side of the first semiconductor chip, and the structure 3D envelopes of formation are encapsulated together with the first semiconductor chip
Assembling structure, the encapsulating structure considerably increase the input/output terminal of encapsulating structure due to being packaged with two semiconductor chips
Mouthful；Simultaneously as the second semiconductor chip back bonding is in the back side of the first semiconductor chip so that the first semiconductor chip with
There is no spacing between second semiconductor chip, effectively reduce the size of encapsulating structure；In addition, the second semiconductor chip passes through gold
Category line electrically connects with re-wiring layer, is not related to the silicon perforation technique of high cost, greatly reduces technology difficulty and cost.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (15)
1. a kind of system-level fan-out package structures of 3D, it is characterised in that the system-level fan-out package structures of 3D include：
Re-wiring layer；
First semiconductor chip, face down back bonding in the upper surface of the re-wiring layer, and with the rewiring
Layer electrical connection；
Second semiconductor chip, is face-up bonded to the back side of first semiconductor chip, and with the re-wiring layer
Electrical connection；
Capsulation material layer, positioned at the upper surface of the re-wiring layer, and by first semiconductor chip and described the second half
Conductor chip encapsulates plastic packaging；
Solder projection, electrically connected positioned at the lower surface of the re-wiring layer, and with the re-wiring layer.
2. the system-level fan-out package structures of 3D according to claim 1, it is characterised in that：The system-level fan-out-types of 3D
Encapsulating structure also includes：
First dielectric layer, between the re-wiring layer and the solder projection；
Post is conductively connected, in first dielectric layer, and runs through first dielectric layer up and down；It is described to be conductively connected
The top of post electrically connects with the re-wiring layer, and the bottom for being conductively connected post electrically connects with the solder projection.
3. the system-level fan-out package structures of 3D according to claim 1, it is characterised in that：The re-wiring layer bag
Include：
Second dielectric layer；
Metal line layer, in second dielectric layer.
4. the system-level fan-out package structures of 3D according to claim 1, it is characterised in that：The re-wiring layer bag
Include：
Second dielectric layer；
Metallic stacked structure, in second dielectric layer；The metallic stacked structure includes the gold of Spaced arrangement
Belong to line layer and metal plug, the metal plug is between the adjacent metal line layer, by the adjacent metal line layer
Electrical connection.
5. the preparation method of the system-level fan-out package structures of 3D according to claim 3 or 4, it is characterised in that：It is described
The material of second dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, and one in fluorine-containing glass
Kind or two or more combinations, the material of the metal line layer include one or both of copper, aluminium, nickel, gold, silver, titanium above group
Close.
6. the system-level fan-out package structures of 3D according to claim 1, it is characterised in that：The system-level fan-out-types of 3D
Encapsulating structure also includes metal connecting line, and second semiconductor chip is electrically connected via the metal connecting line and the re-wiring layer
Connect, first semiconductor chip, second semiconductor chip and the metal connecting line are encapsulated and moulded by the capsulation material layer
Envelope.
7. the system-level fan-out package structures of 3D according to claim 1, it is characterised in that：The capsulation material layer includes
In polyimide layer, layer of silica gel, epoxy resin layer, the curable polymeric substrate bed of material or the curable resin base material bed of material
It is any.
8. the system-level fan-out package structures of 3D according to claim 1, it is characterised in that：The solder projection is weldering
Ball.
A kind of 9. preparation method of the system-level fan-out package structures of 3D, it is characterised in that the system-level fan-out packages of 3D
The preparation method of structure comprises the following steps：
1) substrate is provided；
2) re-wiring layer is formed in the upper surface of the substrate；
3) in the re-wiring layer upper surface be bonded the first semiconductor chip, first semiconductor chip just facing to
The re-wiring layer, and electrically connected with the re-wiring layer；
4) the second semiconductor chip, the front back of the body of second semiconductor chip are bonded in the back side of first semiconductor chip
From first semiconductor chip, and second semiconductor chip electrically connects with the re-wiring layer；
5) capsulation material layer is formed in the upper surface of the re-wiring layer, the capsulation material layer is by first semiconductor core
Piece and second semiconductor chip enveloping plastic packaging；
6) substrate is removed；
7) solder projection is formed in the lower surface of the re-wiring layer, the solder projection is electrically connected with the re-wiring layer
Connect.
10. the preparation method of the system-level fan-out package structures of 3D according to claim 9, it is characterised in that：Step 1)
With also comprising the following steps between step 2)：
The first dielectric layer is formed in the upper surface of the substrate；
In the through hole that several up/down perforations are formed in first dielectric layer；
Post is conductively connected in being formed in the through hole.
11. the preparation method of the system-level fan-out package structures of 3D according to claim 10, it is characterised in that：In described
The step of upper surface of substrate is also included in substrate upper surface before forming first dielectric layer forms peel ply.
12. the preparation method of the system-level fan-out package structures of 3D according to claim 10, it is characterised in that：Step 2)
Comprise the following steps：
2-1) metal line layer is formed in the upper surface of the substrate；
The second dielectric layer 2-2) is formed in the upper surface of the substrate, second dielectric layer is by the metal line layer bag
Wrap up in.
13. the preparation method of the system-level fan-out package structures of 3D according to claim 10, it is characterised in that：Step 2)
Comprise the following steps：
2-1) first layer metal line layer is formed in the upper surface of the substrate；
The second dielectric layer 2-2) is formed in the upper surface of the substrate, second dielectric layer is by metal wire described in first layer
Layer enveloping, and the upper surface of second dielectric layer is higher than the upper surface of the metal line layer；
If 2-3) the stacked spaced apart row electrically connected in formation dried layer in second dielectric layer with metal line layer described in first layer
Other metal line layers of cloth, electrically connected via metal plug between the adjacent metal line layer.
14. the preparation method of the system-level fan-out package structures of 3D according to claim 10, it is characterised in that：Step 4)
Comprise the following steps：
Second semiconductor chip 4-1) is provided；
Second semiconductor chip 4-2) is face-up bonded to the back side of first semiconductor chip, described the second half
The back side of conductor chip and the back side of first semiconductor chip are bonding face；
Metal connecting line 4-3) is formed, one end of the metal connecting line electrically connects with second semiconductor chip, the other end and institute
State re-wiring layer electrical connection.
15. the preparation method of the system-level fan-out package structures of 3D according to claim 10, it is characterised in that：Step 5)
In, using compressing and forming process, Transfer molding technique, fluid-tight moulding process, vacuum lamination process or spin coating proceeding in institute
The upper surface for stating re-wiring layer forms the capsulation material layer；The capsulation material layer includes polyimide layer, layer of silica gel, ring
Any of oxygen tree lipid layer, the curable polymeric substrate bed of material or curable resin base material bed of material.
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| CN207116414U (en) * | 2017-08-02 | 2018-03-16 | 中芯长电半导体（江阴）有限公司 | The system-level fan-out package structures of 3D |
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