CN107301984A - Semiconductor structure, fan-out package structure and preparation method thereof - Google Patents
Semiconductor structure, fan-out package structure and preparation method thereof Download PDFInfo
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- CN107301984A CN107301984A CN201710652838.2A CN201710652838A CN107301984A CN 107301984 A CN107301984 A CN 107301984A CN 201710652838 A CN201710652838 A CN 201710652838A CN 107301984 A CN107301984 A CN 107301984A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L2924/30—Technical effects
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- H01L2924/351—Thermal stress
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention provides a kind of semiconductor structure, fan-out package structure and preparation method thereof, and the semiconductor structure includes：Substrate；Glue-line is peeled off, positioned at the upper surface of the substrate；Capsulation material layer, positioned at the upper surface of the stripping glue-line；Semiconductor chip, plastic packaging is interior in capsulation material layer, and just facing to back bonding in the upper surface of the stripping glue-line；Epoxy resin layer, plastic packaging is in capsulation material layer.The semiconductor structure of the present invention sets epoxy resin layer between stripping glue-line and semiconductor chip, when semiconductor structure will be changed for encapsulating structure, after removal substrate and stripping glue-line, epoxy resin layer is peeled off again, the front of semiconductor chip can be caused without any glue residua, it is easy to the electrical connection of semiconductor structure and re-wiring layer, it can be ensured that the performance of the encapsulating structure of formation.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, more particularly to a kind of semiconductor structure, fan-out package structure
And preparation method thereof.
Background technology
It is more inexpensive, more reliable, faster and more highdensity circuit be integrated antenna package pursue target.In future,
Integrated antenna package will improve the integration density of various electronic components by constantly reducing minimum feature size.At present, first
The method for packing entered includes：Wafer chip level chip-scale package (Wafer Level Chip Scale Packaging,
WLCSP), fan-out-type wafer-level packaging (Fan-Out Wafer Level Package, FOWLP), flip-chip (Flip
Chip), stacked package (Packageon Package, POP) etc..
Fan-out-type wafer-level packaging is a kind of embedded chip method for packing of wafer level processing, be current a kind of input/
Output port (I/O) is more, one of the integrated preferable Advanced Packaging method of flexibility.Fan-out-type wafer-level packaging is compared to routine
Wafer-level packaging have the advantages that its is unique：1. I/O spacing is flexible, independent of chip size；2. effective nude film is only used
(die), product yield is improved；3. there is flexible 3D package paths, you can to form the figure of General Cell at top；4. have
There are preferable electrical property and hot property；5. frequency applications；6. easily high-density wiring is realized in re-wiring layer (RDL).Mesh
Before, fan-out-type wafer-level packaging method is generally：Substrate is provided, glue-line is peeled off in substrate surface formation；Using chip bonding work
Semiconductor chip face down is flip-chip bonded on the stripping glue-line by skill；Using Shooting Technique by semiconductor chip plastic packaging in
In capsulation material layer；Remove substrate and peel off glue-line；Capsulation material layer on photoetching, electroplate out re-wiring layer
(RedistributionLayers, RDL)；Photoetching, plating form Underbump metallization layer (UBM) on re-wiring layer；In UBM
It is upper to carry out planting ball backflow, form solder projection.However, the stripping glue-line used in the preparation technology of above-mentioned encapsulating structure is generally
Pressure-sensitive adhesive belt or pressure-sensitive gel coating, after removing substrate and peeling off glue-line, pressure-sensitive can be remained in the front of semiconductor chip
Glue, the residual of pressure-sensing glue can influence the electrical connection of re-wiring layer and semiconductor chip, so as to influence the performance of encapsulating structure.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of semiconductor structure, fan-out-type
Encapsulating structure and preparation method thereof, substrate and stripping are being removed for solving fan-out-type wafer level packaging structure of the prior art
Pressure-sensitive glue residua is had after glue-line in the front of semiconductor chip, and then the problem of the performance of influence encapsulating structure.
In order to achieve the above objects and other related objects, the present invention provides a kind of semiconductor structure, the semiconductor structure
Including：
Substrate；
Glue-line is peeled off, positioned at the upper surface of the substrate；
Capsulation material layer, positioned at the upper surface of the stripping glue-line；The capsulation material layer includes relative first surface
And second surface, the first surface of capsulation material layer is in contact with the upper surface for peeling off glue-line；
Semiconductor chip, plastic packaging is interior in capsulation material layer, and just facing to back bonding in the stripping glue-line
Upper surface；
Epoxy resin layer, plastic packaging is interior in capsulation material layer, and positioned at the semiconductor chip and the stripping glue-line
Between, to cause first surface indent predetermined depth of the front compared to capsulation material layer of the semiconductor chip.
Preferably, the stripping glue-line includes pressure-sensitive adhesive belt or pressure-sensitive gel coating.
The present invention also provides a kind of fan-out package structure, and the fan-out package structure includes：
Capsulation material layer, the capsulation material layer includes relative first surface and second surface；
Semiconductor chip, plastic packaging in the capsulation material layer in, and the semiconductor chip front compared to the modeling
The first surface indent predetermined depth of closure material layer；
Re-wiring layer, positioned at the first surface of capsulation material layer, and is electrically connected with the semiconductor chip；
Solder projection, positioned at surface of the re-wiring layer away from the semiconductor chip, and with the rewiring
Layer electrical connection.
Preferably, the re-wiring layer includes：
Dielectric layer；
Metal line layer, in the dielectric layer.
Preferably, the re-wiring layer includes：
Dielectric layer；
Metallic stacked structure, in the dielectric layer；The metallic stacked structure includes the gold that Spaced is arranged
Belong to line layer and metal plug, the metal plug is located between the adjacent metal line layer, by the adjacent metal line layer
Electrical connection.
Preferably, the capsulation material layer includes polyimide layer, layer of silica gel, epoxy resin layer, curable polymer
Based material layer or the curable resin base material bed of material.
Preferably, the soldered ball projection includes：
Metal column, is electrically connected positioned at the second surface of the re-wiring layer, and with the re-wiring layer；
Soldered ball, positioned at the surface of the remote semiconductor chip of the metal column.
Preferably, the solder projection is soldered ball.
The present invention also provides a kind of preparation method of fan-out package structure, the preparation method of the fan-out package structure
Comprise the following steps：
1) substrate is provided；
2) formed in the upper surface of the substrate and peel off glue-line；
3) provide semiconductor chip, and by the semiconductor chip by epoxy resin layer back bonding in the stripping glue
The upper surface of layer；
4) capsulation material layer is formed in the upper surface of the stripping glue-line, the capsulation material layer fills up the semiconductor core
Gap between piece and between the epoxy resin layer, and the semiconductor chip and the epoxy resin layer are encapsulated into plastic packaging；
The capsulation material layer includes relative first surface and second surface, and the first surface of the capsulation material layer is peeled off with described
The upper surface of glue-line is in contact；
5) substrate, the stripping glue-line and the epoxy resin layer are removed；
6) in the first surface formation re-wiring layer of capsulation material layer, the re-wiring layer and the semiconductor
Chip is electrically connected；
7) solder projection is formed in surface of the re-wiring layer away from the semiconductor chip.
Preferably, step 2) in, the stripping glue-line formed in the upper surface of the substrate includes pressure-sensitive adhesive belt or pressure-sensitive gel coating.
Preferably, step 4) in, using using compressing and forming process, Transfer molding technique, fluid-tight moulding process, true
Empty laminating technology or spin coating proceeding form the capsulation material layer in the upper surface of the stripping glue-line.
Preferably, step 6) comprise the following steps：
6-1) in the first surface formation metal line layer of capsulation material layer；
6-2) in the first surface formation dielectric layer of capsulation material layer, the dielectric layer is by the metal line layer
Parcel.
Preferably, step 6) comprise the following steps：
6-1) in the first surface formation first layer metal line layer of capsulation material layer；
6-2) in the first surface formation dielectric layer of capsulation material layer, the dielectric layer will be golden described in first layer
Belong to line layer enveloping, and upper surface of the upper surface higher than the metal line layer of the dielectric layer；
If 6-3) the stacked spaced apart row electrically connected in formation dried layer in the dielectric layer with metal line layer described in first layer
Electrically connected between other metal line layers of cloth, the adjacent metal line layer via metal plug.
Preferably, step 7) in, form solder projection in the surface of the re-wiring layer and comprise the following steps：
7-1) metal column is formed in the surface of the re-wiring layer；
7-2) soldered ball is formed in the surface of the metal column.
As described above, the semiconductor structure of the present invention, fan-out package structure and preparation method thereof, with following beneficial effect
Really：The semiconductor structure of the present invention sets epoxy resin layer between stripping glue-line and semiconductor chip, will change semiconductor junction
When structure is used for encapsulating structure, after removing substrate and peeling off glue-line, then epoxy resin layer is peeled off, semiconductor chip can be caused
Front without any glue residua, be easy to the electrical connection of semiconductor structure and re-wiring layer, it can be ensured that the encapsulating structure of formation
Performance；The front of semiconductor structure in the fan-out package structure of the present invention without any glue residua, semiconductor structure with again
New route layer realizes preferably electrical connection, so that it is guaranteed that the performance of the fan-out package structure.
Brief description of the drawings
Fig. 1 is shown as the flow chart of the preparation method of the fan-out package structure provided in the embodiment of the present invention one.
Fig. 2~Fig. 9 is shown as each step institute of preparation method of the fan-out package structure provided in the embodiment of the present invention one
The structural representation of presentation, wherein, Fig. 5 is shown as the structural representation of the semiconductor structure of the present invention, and Fig. 9 is shown as the present invention
Fan-out package structure structural representation.
Component label instructions
11 substrates
12 peel off glue-line
13 semiconductor chips
131 contact pads
14 epoxy resin layers
15 capsulation materials layer
16 re-wiring layers
161 dielectric layers
162 metal line layers
17 solder projections
171 metal columns
172 soldered balls
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Refer to Fig. 1~Fig. 9.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only display is with relevant component in the present invention rather than according to package count during actual implement in diagram
Mesh, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout form may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the present embodiment provides a kind of preparation method of fan-out package structure, the fan-out package structure
Preparation method comprise the following steps：
1) substrate is provided；
2) formed in the upper surface of the substrate and peel off glue-line；
3) provide semiconductor chip, and by the semiconductor chip by epoxy resin layer back bonding in the stripping glue
The upper surface of layer；
4) capsulation material layer is formed in the upper surface of the stripping glue-line, the capsulation material layer fills up the semiconductor core
Gap between piece and between the epoxy resin layer, and the semiconductor chip and the epoxy resin layer are encapsulated into plastic packaging；
The capsulation material layer includes relative first surface and second surface, and the first surface of the capsulation material layer is peeled off with described
The upper surface of glue-line is in contact；
5) substrate, the stripping glue-line and the epoxy resin layer are removed；
6) in the first surface formation re-wiring layer of capsulation material layer, the re-wiring layer and the semiconductor
Chip is electrically connected；
7) solder projection is formed in surface of the re-wiring layer away from the semiconductor chip.
In step 1) in, there is provided substrate 11 for the S1 steps and Fig. 2 for referring in Fig. 1.
As an example, the material of the substrate 11 can include in silicon, glass, silica, ceramics, polymer and metal
One or more kinds of composites, its shape can for wafer shape, it is square or it is other it is any needed for shape；The present embodiment
Prevent that the problems such as rupture, warpage, fracture occurs for semiconductor chip in subsequent preparation process by the substrate 11.
In step 2) in, S2 steps and Fig. 3 in Fig. 1 are referred to, is formed in the upper surface of the substrate 11 and peels off glue-line
12。
As an example, the stripping glue-line 12 is used as substrate described in the semiconductor chip 13 being subsequently formed in subsequent technique
Separating layer between 11, it is preferably made from the jointing material with smooth finish surface, and it must be with the semiconductor chip 13
With certain adhesion, to ensure situations such as semiconductor chip 13 will not produce mobile in subsequent technique, in addition, its
Also there is stronger adhesion with the substrate 11, in general, the adhesion of itself and the substrate 11 need to be more than with it is described
The adhesion of semiconductor chip 13.As an example, the stripping glue-line 12 can be but be not limited only to pressure-sensitive adhesive belt or pressure-sensing glue
Coating.In substrate 11 described in later separation, can using wet etching, cmp, the method such as remove and remove the stripping
From glue-line 12.
In step 3) in, the S3 steps and Fig. 4 in Fig. 1 are referred to there is provided semiconductor chip 13, and by the semiconductor core
Piece 13 is by the back bonding of epoxy resin layer 14 in the upper surface of the stripping glue-line 12.
In one example, first it can set described in the follow-up position for wanting bonding semiconductor chip 13 of the stripping glue-line 12
The semiconductor chip 13, is then bonded to the upper surface of the epoxy resin layer 14 by epoxy resin layer 14 again.
In another example, the epoxy resin layer 14 first can be formed in the front of the semiconductor chip 13, then
The semiconductor chip 13 is bonded to the upper surface of the stripping glue-line 12, the epoxy resin layer 14 and the stripping glue again
Layer 12 is in contact.
As an example, the front of the semiconductor chip 13 is formed with the contact pad for drawing its inside function device electricity
131, the back bonding of semiconductor chip 13 is in the upper surface of the epoxy resin layer 14, and the semiconductor chip 13 connects
Weld pad 131 is touched to be in contact with the upper surface of the epoxy resin layer 14.
Positive in the semiconductor chip 13 sets the epoxy resin layer 14 between the stripping glue-line 12, described
The front of semiconductor chip 13 is not contacted directly with the stripping glue-line 12, is subsequently removing the substrate 11, the stripping glue
After layer 12 and the epoxy resin layer 14, the epoxy resin layer 14 can be entirely removed, the semiconductor chip 13
Front does not have any glue residua.
In step 4) in, S4 steps and Fig. 5 in Fig. 1 are referred to, plastic packaging is formed in the upper surface of the stripping glue-line 12
Material layer 15, between the capsulation material layer 15 is filled up between the semiconductor chip 13 and between the epoxy resin layer 14
Gap, and the semiconductor chip 13 and the epoxy resin layer 14 are encapsulated into plastic packaging；The capsulation material layer 15 includes relative
First surface and second surface, the first surface of the capsulation material layer 15 are in contact with the upper surface of the stripping glue-line 12.
As an example, can be using compressing and forming process, transfer shaping technology, hydraulic seal moulding process, molding bottom
Fill process, capillary underfill technique, vacuum lamination process or spin coating proceeding are formed in the upper surface of the stripping glue-line 12
The capsulation material layer 15.Preferably, in the present embodiment, using molded underfill technique in the upper table of the stripping glue-line 12
Face forms the capsulation material layer 15, and such capsulation material can be promptly filled between the semiconductor chip 13 with smooth
Gap and the epoxy resin layer 14 between gap, can be effectively prevented from interface debonding, and molded underfill occur
It will not be restricted as capillary underfill technique of the prior art, greatly reduce technology difficulty, can be used for more
Small joint gap, is more suitable for stacked structure.
As an example, the material of capsulation material layer 15 can be but be not limited only to polyimide layer, layer of silica gel, epoxy
Resin bed, the curable polymeric substrate bed of material or the curable resin base material bed of material.
In step 5) in, the S5 steps and Fig. 6 to Fig. 7 in Fig. 1 are referred to, the substrate 11, the stripping glue-line is removed
12 and the epoxy resin layer 14.
As an example, the substrate 11 and the stripping glue-line can be removed using grinding technics, reduction process etc.
12, as shown in Figure 6.Preferably, in the present embodiment, it can use and tear the mode of the stripping glue-line 12 to remove the substrate
11.Epoxy resin can be used to remove solvent and remove the epoxy resin layer 14, for example, the organic solvents such as alcohol can be used to go
Except the epoxy resin layer 14, any one existing epoxy resin diluent can also be removed and remove the epoxy resin layer
14, as shown in Figure 7.Remove after the epoxy resin layer 14, the front of the semiconductor chip 13 is less than the capsulation material
The first surface of layer 15, i.e., the front of described semiconductor chip 13 is default compared to the positive indent of capsulation material layer 15 deep
Degree.
In step 6) in, S6 steps and Fig. 8 in Fig. 1 are referred to, is formed in the first surface of capsulation material layer 15
Re-wiring layer 16, the re-wiring layer 16 is electrically connected with the semiconductor chip 13.
In one example, the re-wiring layer 16 includes one layer of dielectric layer 161 and layer of metal line layer 162, in institute
The surface formation re-wiring layer 16 for stating capsulation material layer 15 comprises the following steps：
6-1) in the first surface formation metal line layer 162 of capsulation material layer 15；
6-2) in the first surface formation dielectric layer 161 of capsulation material layer 15, the dielectric layer 161 will be described
Metal line layer 162 is wrapped up.
In another example, the re-wiring layer 16 includes one layer of dielectric layer 161 and layer of metal line layer 162, in
The surface of the capsulation material layer 15 forms re-wiring layer 16 and comprised the following steps：
6-1) in the first surface formation dielectric layer 161 of capsulation material layer 15, by lithographic etch process in institute
State and groove is formed in dielectric layer 161, the groove defines the shape of the metal line layer 162；
6-2) in forming the metal line layer 162 in the groove.
In another example, as shown in figure 8, the re-wiring layer 16 include at least described in two layers metal line layer 162 and
At least one layer of dielectric layer 161, forms re-wiring layer 16 in the surface of capsulation material layer 15 and comprises the following steps：
6-1) in the first surface formation first layer metal line layer 162 of capsulation material layer 15；
6-2) in the first surface formation dielectric layer 161 of capsulation material layer 15, the dielectric layer 161 is by first
The layer metal line layer 162 is encapsulated, and upper surface of the upper surface higher than the metal line layer 162 of the dielectric layer 161；
If 6-3) in the interval that formation dried layer is electrically connected with metal line layer described in first layer 162 in the dielectric layer 161
Stack between other metal line layers 162 of arrangement, the adjacent metal line layer 162 via the electrical connection of metal plug (not shown).
As an example, in above-mentioned example, the material of the metal line layer 162 can be but be not limited only to copper, aluminium, nickel, gold,
Silver, a kind of material in titanium or two kinds and two or more combined materials, and PVD, CVD, sputtering, plating or chemical plating can be used
The metal line layer 162 is formed etc. technique.The material of the dielectric layer 161 can be low k dielectric；Specifically, described
Dielectric layer 161 can use one kind in epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass
Material, it is possible to which the dielectric layer 161 is formed using techniques such as spin coating, CVD, plasma enhanced CVDs.
As an example, in above-mentioned example, the upper surface positioned at the metal line layer 162 of top layer can be exposed to the electricity
Outside the upper surface of dielectric layer 161, i.e., the upper surface positioned at the metal line layer 162 of top layer can be with the dielectric layer
161 upper surface flush, can also protrude from the top of the upper surface of the dielectric layer 161.Certainly, in other examples
In, the upper surface positioned at the metal line layer 162 of top layer can also be less than the upper surface of the dielectric layer 161, that is, be located at
The metal line layer 162 of top layer is located at the inside of the dielectric layer 161.
As an example, in above-mentioned example, the lower surface positioned at the metal line layer 162 of bottom can be exposed to the electricity
Outside the lower surface of dielectric layer 161, i.e., the lower surface positioned at the metal line layer 162 of bottom can be with the dielectric layer
161 lower surface flush, can also protrude from the lower section of the lower surface of the dielectric layer 161.Certainly, in other examples
In, the lower surface positioned at the metal line layer 162 of bottom can also be higher than the lower surface of the dielectric layer 161, that is, be located at
The metal line layer 162 of bottom is located at the inside of the dielectric layer 161.
It should be noted that the metal line layer 162 in the re-wiring layer 16 with the semiconductor chip 13
The contact pad 131 electrically connect.
In step 7) in, S7 steps and Fig. 9 in Fig. 1 are referred to, in the re-wiring layer 16 away from the semiconductor
The surface of chip 13 forms solder projection 17.
In one example, solder projection is formed in the surface of the remote semiconductor chip 13 of the re-wiring layer 16
17 comprise the following steps：
7-1) metal column 171 is formed in the surface of the remote semiconductor chip 13 of the re-wiring layer 16；
7-2) soldered ball 172 is formed in the surface of the remote semiconductor chip 13 of the metal column 171.
As an example, the material of the metal column 171 can be a kind of material in copper, aluminium, nickel, gold, silver, titanium or two kinds
And two or more combined materials, can by physical gas-phase deposition (PVD), chemical vapor deposition method (CVD), splash
Penetrate, electroplate or any of chemical plating technique forms the metal column 171.The material of the soldered ball 172 can for copper, aluminium,
A kind of material or two kinds and two or more combined materials in nickel, gold, silver, titanium, can be by planting ball reflux technique formation institute
State soldered ball 172.
In another example, the solder projection 17 is a soldered ball, can directly form weldering by planting ball reflux technique
Ball is used as the solder projection 17.
Embodiment two
Please continue to refer to Fig. 5, the present embodiment also provides a kind of semiconductor structure, and the semiconductor structure includes：Substrate 11；
Glue-line 12 is peeled off, the peel ply 12 is located at the upper surface of the substrate 11；Capsulation material layer 15,15, the capsulation material layer
In the upper surface of the stripping glue-line 12；The capsulation material layer 15 includes relative first surface and second surface, the modeling
The first surface of closure material layer 15 is in contact with the upper surface of the stripping glue-line 12；Semiconductor chip 13, the semiconductor core
The plastic packaging of piece 13 in the capsulation material layer 15 in, and just facing to back bonding in it is described stripping glue-line 12 upper surface；Epoxy
Resin bed 14, the plastic packaging of epoxy resin layer 14 is in capsulation material layer 1513, and positioned at the semiconductor chip and institute
State stripping glue-line 12 between, with cause the semiconductor chip 13 front compared to the capsulation material layer 15 first surface
Indent predetermined depth.
As an example, the material of the substrate 11 can include in silicon, glass, silica, ceramics, polymer and metal
One or more kinds of composites, its shape can for wafer shape, it is square or it is other it is any needed for shape；The present embodiment
Prevent that the problems such as rupture, warpage, fracture occurs for semiconductor chip in subsequent preparation process by the substrate 11.
As an example, the stripping glue-line 12 can include but are not limited to pressure-sensitive adhesive belt or pressure-sensitive gel coating.
As an example, can be using compressing and forming process, transfer shaping technology, hydraulic seal moulding process, molding bottom
Fill process, capillary underfill technique, vacuum lamination process or spin coating proceeding are formed in the upper surface of the stripping glue-line 12
The capsulation material layer 15.Preferably, in the present embodiment, using molded underfill technique in the upper table of the stripping glue-line 12
Face forms the capsulation material layer 15, and such capsulation material can be promptly filled between the semiconductor chip 13 with smooth
Gap and the epoxy resin layer 14 between gap, can be effectively prevented from interface debonding, and molded underfill occur
It will not be restricted as capillary underfill technique of the prior art, greatly reduce technology difficulty, can be used for more
Small joint gap, is more suitable for stacked structure.
As an example, the material of capsulation material layer 15 can be but be not limited only to polyimide layer, layer of silica gel, epoxy
Resin bed, the curable polymeric substrate bed of material or the curable resin base material bed of material.
As an example, the front of the semiconductor chip 13 is formed with the contact pad for drawing its inside function device electricity
131, the back bonding of semiconductor chip 13 is in the upper surface of the epoxy resin layer 14, and the semiconductor chip 13 connects
Weld pad 131 is touched to be in contact with the upper surface of the epoxy resin layer 14.
Positive in the semiconductor chip 13 sets the epoxy resin layer 14 between the stripping glue-line 12, described
The front of semiconductor chip 13 is not contacted directly with the stripping glue-line 12, is subsequently removing the substrate 11, the stripping glue
After layer 12 and the epoxy resin layer 14, the epoxy resin layer 14 can be entirely removed, the semiconductor chip 13
Front does not have any glue residua.
Embodiment three
Please continue to refer to Fig. 9, the present embodiment also provides a kind of fan-out package structure, the fan-out package structure bag
Include：Capsulation material layer 15, the capsulation material layer 15 includes relative first surface and second surface；Semiconductor chip 13, institute
State the plastic packaging of semiconductor chip 13 in the capsulation material layer 15 in, and the semiconductor chip 13 front compared to the plastic packaging
The first surface indent predetermined depth of material layer 15, i.e., the front of described semiconductor chip 13 is less than capsulation material layer 15
First surface；Re-wiring layer 16, the re-wiring layer 16 be located at the capsulation material layer 15 first surface, and with it is described
Semiconductor chip 13 is electrically connected；Solder projection 17, the solder projection 17 is partly led positioned at the re-wiring layer 16 away from described
The surface of body chip 13, and electrically connected with the re-wiring layer 16.
In one example, the re-wiring layer 16 includes：Dielectric layer 161；Metal line layer 162, the metal line layer
162 are located in the dielectric layer 161.
In another example, the re-wiring layer 16 includes：Dielectric layer 161；Metallic stacked structure, the metal is folded
Rotating fields are located in the dielectric layer 161；The metallic stacked structure includes the metal line layer 162 and gold that Spaced is arranged
Belong to connector, the metal plug is located between the adjacent metal line layer 162, the adjacent metal line layer 161 is electrically connected
Connect.
It should be noted that on address follow-up described " being electrically connected with the re-wiring layer 16 " refer both to it is described again
Metal line layer 162 in wiring layer 16 is electrically connected.
As an example, the front of the semiconductor chip 13 is formed with the contact pad for drawing its inside function device electricity
131, the back bonding of semiconductor chip 13 is in the upper surface of the substrate 11, and the contact pad of the semiconductor chip 13
131 are in contact with the upper surface of the substrate 11.
As an example, the material of capsulation material layer 15 can be but be not limited only to polyimide layer, layer of silica gel, epoxy
Resin bed, the curable polymeric substrate bed of material or the curable resin base material bed of material.
In one example, the solder projection 17 includes：Metal column 171, the metal column 171 is located at the rewiring
16 surface away from the semiconductor chip 13 of layer, and electrically connected with the re-wiring layer 16；Soldered ball 172, the soldered ball 172
Positioned at the surface of the remote semiconductor chip 13 of the metal column 171.The material of the metal column 171 can for copper, aluminium,
A kind of material or two kinds and two or more combined materials in nickel, gold, silver, titanium, can pass through physical gas-phase deposition
(PVD), any of chemical vapor deposition method (CVD), sputtering, plating or chemical plating technique form the metal column 171.
The material of the soldered ball 172 can be a kind of material or two kinds and two or more combination materials in copper, aluminium, nickel, gold, silver, titanium
Material, can form the soldered ball 172 by planting ball reflux technique.
In another example, the solder projection 17 is soldered ball.
In summary, semiconductor structure of the invention, fan-out package structure and preparation method thereof, the semiconductor structure
Including：Substrate；Glue-line is peeled off, positioned at the upper surface of the substrate；Capsulation material layer, positioned at the upper surface of the stripping glue-line；
The capsulation material layer includes relative first surface and second surface, and the first surface of the capsulation material layer is peeled off with described
The upper surface of glue-line is in contact；Semiconductor chip, plastic packaging is interior in capsulation material layer, and just facing to back bonding in described
Peel off the upper surface of glue-line；Epoxy resin layer, plastic packaging in the capsulation material layer in, and positioned at the semiconductor chip with it is described
Between stripping glue-line, to cause the front of the semiconductor chip to be preset compared to the first surface indent of capsulation material layer
Depth.The semiconductor structure of the present invention sets epoxy resin layer between stripping glue-line and semiconductor chip, will change semiconductor
When structure is used for encapsulating structure, after removing substrate and peeling off glue-line, then epoxy resin layer is peeled off, semiconductor core can be caused
It is easy to the electrical connection of semiconductor structure and re-wiring layer, it can be ensured that the encapsulation knot of formation without any glue residua in the front of piece
The performance of structure；The front of semiconductor structure in the fan-out package structure of the present invention without any glue residua, semiconductor structure with
Re-wiring layer realizes preferable electrical connection, so that it is guaranteed that the performance of the fan-out package structure.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (14)
1. a kind of semiconductor structure, it is characterised in that the semiconductor structure includes：
Substrate；
Glue-line is peeled off, positioned at the upper surface of the substrate；
Capsulation material layer, positioned at the upper surface of the stripping glue-line；Capsulation material layer includes relative first surface and the
Two surfaces, the first surface of the capsulation material layer is in contact with the upper surface of the stripping glue-line；
Semiconductor chip, plastic packaging is interior in capsulation material layer, and just facing to back bonding in the upper table of the stripping glue-line
Face；
Epoxy resin layer, plastic packaging is interior in capsulation material layer, and is located between the semiconductor chip and the stripping glue-line,
To cause first surface indent predetermined depth of the front compared to capsulation material layer of the semiconductor chip.
2. semiconductor structure according to claim 1, it is characterised in that the stripping glue-line includes pressure-sensitive adhesive belt or pressure-sensitive
Gel coating.
3. a kind of fan-out package structure, it is characterised in that the fan-out package structure includes：
Capsulation material layer, the capsulation material layer includes relative first surface and second surface；
Semiconductor chip, plastic packaging in the capsulation material layer in, and the semiconductor chip front compared to the plastic packaging material
The first surface indent predetermined depth of the bed of material；
Re-wiring layer, positioned at the first surface of capsulation material layer, and is electrically connected with the semiconductor chip；
Solder projection, positioned at surface of the re-wiring layer away from the semiconductor chip, and it is electric with the re-wiring layer
Connection.
4. fan-out package structure according to claim 3, it is characterised in that the re-wiring layer includes：
Dielectric layer；
Metal line layer, in the dielectric layer.
5. fan-out package structure according to claim 3, it is characterised in that the re-wiring layer includes：
Dielectric layer；
Metallic stacked structure, in the dielectric layer；The metallic stacked structure includes the metal wire that Spaced is arranged
Layer and metal plug, the metal plug are located between the adjacent metal line layer, and the adjacent metal line layer is electrically connected
Connect.
6. fan-out package structure according to claim 3, it is characterised in that the capsulation material layer includes polyimides
Layer, layer of silica gel, epoxy resin layer, the curable polymeric substrate bed of material or the curable resin base material bed of material.
7. fan-out package structure according to claim 3, it is characterised in that the soldered ball projection includes：
Metal column, is electrically connected positioned at the second surface of the re-wiring layer, and with the re-wiring layer；
Soldered ball, positioned at the surface of the remote semiconductor chip of the metal column.
8. fan-out package structure according to claim 3, it is characterised in that the solder projection is soldered ball.
9. a kind of preparation method of fan-out package structure, it is characterised in that the preparation method bag of the fan-out package structure
Include following steps：
1) substrate is provided；
2) formed in the upper surface of the substrate and peel off glue-line；
3) semiconductor chip is provided, and by the semiconductor chip by epoxy resin layer back bonding in the stripping glue-line
Upper surface；
4) form capsulation material layer in the upper surface of the stripping glue-line, capsulation material layer fill up the semiconductor chip it
Between and the epoxy resin layer between gap, and the semiconductor chip and the epoxy resin layer are encapsulated into plastic packaging；It is described
Capsulation material layer includes relative first surface and second surface, the first surface and the stripping glue-line of the capsulation material layer
Upper surface be in contact；
5) substrate, the stripping glue-line and the epoxy resin layer are removed；
6) in the first surface formation re-wiring layer of capsulation material layer, the re-wiring layer and the semiconductor chip
Electrical connection；
7) solder projection is formed in surface of the re-wiring layer away from the semiconductor chip.
10. the preparation method of fan-out package structure according to claim 9, it is characterised in that step 2) in, in described
The stripping glue-line that the upper surface of substrate is formed includes pressure-sensitive adhesive belt or pressure-sensitive gel coating.
11. the preparation method of fan-out package structure according to claim 9, it is characterised in that step 4) in, using adopting
Peeled off with compressing and forming process, Transfer molding technique, fluid-tight moulding process, vacuum lamination process or spin coating proceeding in described
The upper surface of glue-line forms the capsulation material layer.
12. the preparation method of fan-out package structure according to claim 9, it is characterised in that step 6) including as follows
Step：
6-1) in the first surface formation metal line layer of capsulation material layer；
6-2) in the first surface formation dielectric layer of capsulation material layer, the dielectric layer is by the metal line layer bag
Wrap up in.
13. the preparation method of fan-out package structure according to claim 9, it is characterised in that step 6) including as follows
Step：
6-1) in the first surface formation first layer metal line layer of capsulation material layer；
6-2) in the first surface formation dielectric layer of capsulation material layer, the dielectric layer is by metal wire described in first layer
Layer enveloping, and upper surface of the upper surface higher than the metal line layer of the dielectric layer；
If 6-3) being arranged in the stacked spaced apart that formation dried layer is electrically connected with metal line layer described in first layer in the dielectric layer
Electrically connected between other metal line layers, the adjacent metal line layer via metal plug.
14. the preparation method of fan-out package structure according to claim 9, it is characterised in that step 7) in, in described
The surface of re-wiring layer forms solder projection and comprised the following steps：
7-1) metal column is formed in the surface of the re-wiring layer；
7-2) soldered ball is formed in the surface of the metal column.
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| CN109872979A (en) * | 2019-02-14 | 2019-06-11 | 南通通富微电子有限公司 | A kind of fan-out package device |
| CN110379721A (en) * | 2019-07-30 | 2019-10-25 | 中芯集成电路（宁波）有限公司 | Fan-out package method and encapsulating structure |
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