CN107785339A - 3D chip-packaging structures and preparation method thereof - Google Patents
3D chip-packaging structures and preparation method thereof Download PDFInfo
- Publication number
- CN107785339A CN107785339A CN201710954752.5A CN201710954752A CN107785339A CN 107785339 A CN107785339 A CN 107785339A CN 201710954752 A CN201710954752 A CN 201710954752A CN 107785339 A CN107785339 A CN 107785339A
- Authority
- CN
- China
- Prior art keywords
- chip
- wiring layer
- circuit substrate
- semiconductor chip
- weld pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of 3D chip-packaging structures and preparation method thereof, and 3D chip-packaging structures include：Circuit substrate, the upper surface of circuit substrate are provided with the first connection weld pad, and lower surface is provided with the second connection weld pad, and the first connection weld pad is connected weld pad electrical connection with second；Re-wiring layer, re-wiring layer is installed in the upper surface of circuit substrate via first surface, and is connected weld pad electrical connection with first；Semiconductor chip, face down upside-down mounting is in the second surface of re-wiring layer；Capsulation material layer, plastic packaging is in the periphery of semiconductor chip；Solder projection, positioned at the lower surface of circuit substrate, and it is connected weld pad with second and is connected.Re-wiring layer in the 3D chip-packaging structures of the present invention directly electrically connects with circuit substrate, it is not necessary to which intermediary layer and silicon hole, whole encapsulating structure is fairly simple, and packaging cost is cheap；The line width and line spacing of metal connecting line in re-wiring layer can reach less than 1 μm, so as to meet the needs of device performance raising.
Description
Technical field
The present invention relates to a kind of semiconductor package and method for packing, more particularly to a kind of 3D chip-packaging structures and
Its preparation method.
Background technology
With the increasing functional requirement of network application electronic equipment, the raising of performance and lower production cost and
Smaller desktop, laptop, fan-out wafer level chip package (Fan out wafer level) technology and 3D chip encapsulation technologies are
Through as one of technology of most prospect for meeting mobile and network application electronic equipment demand, but mesh first two technology respectively have it is excellent
Shortcoming：For example, the line width of current fan-out wafer level chip encapsulation technology and line spacing can only accomplish, however, with device
Performance increase, I/O (input/output) increase, and this certainly will need smaller line width and line spacing to meet, however, working as line width and line
After spacing reaches 2 μm, if very big challenge will be caused again by reducing；Again for example, current 3D chip encapsulation technologies, are both needed to
Using silicon hole technology (TSV), and needing to use intermediary layer (interposer) so that encapsulating structure is more complicated, and
Packaging cost is higher.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of 3D chip-packaging structures and its
Preparation method, for solving line width existing for encapsulating structure of the prior art and line spacing can not be contracted to less than 2 μm, and
Complicated, the problems such as packaging cost is higher.
In order to achieve the above objects and other related objects, the present invention provides a kind of 3D chip-packaging structures, the 3D chips
Encapsulating structure includes：
Circuit substrate, the upper surface of the circuit substrate are provided with the first connection weld pad, and lower surface is provided with the second connection weld pad,
The first connection weld pad is connected weld pad electrical connection with described second；
Re-wiring layer, including relative first surface and second surface, the re-wiring layer fill via first surface
Weld pad electrical connection is connected located at the upper surface of the circuit substrate, and with described first；
Semiconductor chip, face down upside-down mounting in the second surface of the re-wiring layer, and with the re-wiring layer
Electrical connection；
Capsulation material layer, plastic packaging is in the periphery of the semiconductor chip, and the capsulation material layer is away from the cloth again
The surface of line layer and the back side flush of the semiconductor chip；
Solder projection, positioned at the lower surface of the circuit substrate, and it is connected weld pad with described second and is connected.
Preferably, the re-wiring layer includes：
Dielectric layer；
Metal connecting line, in the dielectric layer, between the line width of the metal connecting line and the adjacent metal connecting line
Spacing is respectively less than 1 μm.
Preferably, the 3D chip-packaging structures also include point glue-line, and described glue-line is filled in the re-wiring layer
Between the circuit substrate.
Preferably, the 3D chip-packaging structures also include fin, and the fin adheres on the semiconductor chip
The back side.
Preferably, the 3D chip-packaging structures also include fin, and the fin is buckled as the circuit substrate
Upper surface, to form sealing cavity between the fin and the circuit substrate；The re-wiring layer, the semiconductor
Chip and the capsulation material layer are respectively positioned in the sealing cavity, and the back side of the semiconductor chip and the fin phase
Contact.
Preferably, the quantity of the semiconductor chip is one in the 3D chip-packaging structures.
Preferably, the quantity of the semiconductor chip is at least two in the 3D chip-packaging structures, adjacent described half
There is spacing between conductor chip.
The present invention also provides a kind of preparation method of 3D chip-packaging structures, the preparation method of the 3D chip-packaging structures
Comprise the following steps：
1) semi-conductive substrate is provided, re-wiring layer, the cloth again are formed in the upper surface of the Semiconductor substrate
Line layer includes relative first surface and second surface, wherein, the first surface of the re-wiring layer serves as a contrast with the semiconductor
The upper surface at bottom is in contact；
2) semiconductor chip is provided, the semiconductor chip face down is installed in the second table of the re-wiring layer
Face；
3) capsulation material layer is formed in the second surface of the re-wiring layer, the capsulation material layer, which fills up, described partly leads
The gap between gap and the semiconductor chip and the re-wiring layer between body chip, and by the semiconductor chip
Plastic packaging；
4) Semiconductor substrate is removed；
5) circuit substrate is provided, the upper surface of the circuit substrate is provided with the first connection weld pad, and lower surface is provided with second
Weld pad is connected, the first connection weld pad is connected weld pad electrical connection with described second；The semiconductor chip after plastic packaging is passed through
The upper surface of the circuit substrate is installed in by the re-wiring layer, the re-wiring layer is connected weld pad electricity with described first
Connection.
Preferably, in step 1), form re-wiring layer in the upper surface of the Semiconductor substrate and comprise the following steps：
1-1) dielectric layer is formed in the upper surface of the Semiconductor substrate；
1-2) it is less than 1 μm, and adjacent trenches in the groove that up/down perforation is formed in the dielectric layer, the width of the groove
Be smaller than 1 μm；
1-3) in forming metal connecting line in the groove.
Preferably, in step 3), in the upper table for the capsulation material layer that the second surface of the re-wiring layer is formed
Face is higher than the back side of the semiconductor chip；The semiconductor chip after plastic packaging is installed in institute via the re-wiring layer
Before the upper surface for stating circuit substrate, in addition to the step of remove the part capsulation material layer, to cause the modeling retained
The upper surface of closure material layer and the back side flush of the semiconductor chip.
Preferably, after step 4) removes the Semiconductor substrate, also it is included in the first surface of the re-wiring layer
The step of forming connection soldered ball, the connection soldered ball electrically connect with the re-wiring layer；In step 5), the re-wiring layer
Via the connection soldered ball weld pad electrical connection is connected with described first.
Preferably, multiple semiconductor chips, multiple semiconductor chip equal face down dresses are provided in step 2)
There is spacing between the second surface of the re-wiring layer, adjacent semiconductor chips；Between step 4) and step 5) also
The step of structure including step 4) is obtained is cut, to obtain several structures to be packaged, each structure to be packaged
Inside include at least one semiconductor chip；In step 5), described after the plastic packaging in the structure to be packaged is partly led
Body chip is installed in the upper surface of the circuit substrate via the re-wiring layer.
Preferably, after step 5), also it is included in filling point glue-line between the re-wiring layer and the circuit substrate
The step of, gap that described glue-line is filled up between the re-wiring layer and the circuit substrate.
Preferably, between the re-wiring layer and the circuit substrate after filling point glue-line, also it is included in described
The upper surface of circuit substrate forms the step of fin, and the fin buckles the upper surface as the circuit substrate, with institute
State and form sealing cavity between fin and the circuit substrate；The re-wiring layer, the semiconductor chip and the modeling
Closure material layer is respectively positioned in the sealing cavity, and the back side of the semiconductor chip is in contact with the fin.
Preferably, after forming fin in the upper surface of the circuit substrate, also it is included under the circuit substrate
Surface forms the structure of solder projection, and the solder projection is connected weld pad electrical connection with described second.
As described above, 3D chip-packaging structures of the present invention and preparation method thereof, have the advantages that：
Re-wiring layer in the 3D chip-packaging structures of the present invention directly electrically connects with circuit substrate, it is not necessary to intermediary layer
And silicon hole, whole encapsulating structure is fairly simple, and packaging cost is cheap；The line width and line of metal connecting line in re-wiring layer
Spacing can reach less than 1 μm, so as to meet the needs of device performance raising.
Brief description of the drawings
Fig. 1 is shown as the flow chart of the preparation method of the 3D chip-packaging structures provided in the embodiment of the present invention one.
Fig. 2~Figure 11 is shown as each step institute of preparation method of the 3D chip-packaging structures provided in the embodiment of the present invention one
The structural representation of presentation, wherein, Figure 11 is shown as the structural representation of the 3D chip-packaging structures of the present invention.
Component label instructions
10 Semiconductor substrates
11 re-wiring layers
111 dielectric layers
112 metal connecting lines
12 semiconductor chips
121 connection weld pads
13 solder-connected structures
131 metal columns
132 soldered balls
14 capsulation material layers
15 connection soldered balls
The 16 blue films of cutting
17 annular iron rings
18 circuit substrates
181 first connection weld pads
182 second connection weld pads
19 glue-lines
20 fin
21 sealing cavities
22 solder projections
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Refer to Fig. 1~Figure 11.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only showing the component relevant with the present invention in diagram rather than according to package count during actual implement
Mesh, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout form may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the present invention provides a kind of preparation method of 3D chip-packaging structures, the 3D chip-packaging structures
Preparation method comprises the following steps：
1) semi-conductive substrate is provided, re-wiring layer, the cloth again are formed in the upper surface of the Semiconductor substrate
Line layer includes relative first surface and second surface, wherein, the first surface of the re-wiring layer serves as a contrast with the semiconductor
The upper surface at bottom is in contact；
2) semiconductor chip is provided, the semiconductor chip face down is installed in the second table of the re-wiring layer
Face；
3) capsulation material layer is formed in the second surface of the re-wiring layer, the capsulation material layer, which fills up, described partly leads
The gap between gap and the semiconductor chip and the re-wiring layer between body chip, and by the semiconductor chip
Plastic packaging；
4) Semiconductor substrate is removed；
5) circuit substrate is provided, the upper surface of the circuit substrate is provided with the first connection weld pad, and lower surface is provided with second
Weld pad is connected, the first connection weld pad is connected weld pad electrical connection with described second；The semiconductor chip after plastic packaging is passed through
The upper surface of the circuit substrate is installed in by the re-wiring layer, the re-wiring layer is connected weld pad electricity with described first
Connection.
In step 1), S1 steps and Fig. 2 to Fig. 3 in Fig. 1 are referred to, there is provided semi-conductive substrate 10, in described half
The upper surface of conductor substrate 10 forms re-wiring layer 11, and the re-wiring layer 11 includes relative first surface and the second table
Face, wherein, the first surface of the re-wiring layer 11 is in contact with the upper surface of the Semiconductor substrate 10.
As an example, the Semiconductor substrate 10 can be silicon substrate, Sapphire Substrate or gallium nitride substrate etc.；It is preferred that
Ground, in the present embodiment, the Semiconductor substrate 10 is Silicon Wafer.
Comprise the following steps as an example, forming re-wiring layer 11 in the upper surface of the Semiconductor substrate 10：
1-1) dielectric layer 111 is formed in the upper surface of the Semiconductor substrate 10；Specifically, the dielectric layer 111 can be with
For but be not limited only to low-k dielectric layer, the techniques such as physical vaporous deposition or chemical vapour deposition technique can be used partly to be led in described
The upper surface of body substrate 10 forms the dielectric layer 111；
1-2) it is less than 1 μ in the groove (not shown) that up/down perforation is formed in the dielectric layer 111, the width of the groove
M, and adjacent trenches are smaller than 1 μm；Specifically, it can use but be not limited only to dry etch process in the dielectric layer
The groove is formed in 111；
1-3) in formation metal connecting line 112 in the groove；Specifically, the material of the metal connecting line 112 can be copper,
A kind of material or two or more combined materials in aluminium, nickel, gold, silver, titanium, can by physical gas-phase deposition (PVD),
Chemical vapor deposition method (CVD), sputtering, plating or any of chemical plating technique are in forming the metal in the groove
Line 112.
In the present embodiment, the rewiring is formed in the upper surface of the Semiconductor substrate 10 using dry etch process
Layer 11, can be by the line width of the encapsulating structure ultimately formed and the control of line spacing below 1 μm.
Refer to S2 steps and Fig. 4 in Fig. 1, there is provided semiconductor chip 12, by the face down of semiconductor chip 12
It is installed in the second surface of the re-wiring layer 11.
As an example, the semiconductor chip 12 can be any one semiconductor functional chip, the semiconductor chip
12 front is formed with the connection weld pad 121 for drawing its inside function device electricity, a surface exposure of the connection weld pad 121
In the front of the semiconductor chip 12, i.e., a surface of described connection weld pad 121 and the positive phase of the semiconductor chip 12
Flush with or slightly higher than the front of the semiconductor chip 12.
As an example, the quantity of the semiconductor chip 12 provided can be set according to being actually needed, the semiconductor
The quantity of chip 12 can be one, two, three, four, it is even more.
As an example, the face down of semiconductor chip 12 can be installed in by solder-connected structure 13
The second surface of (attach on) described re-wiring layer 11.
As an example, the solder-connected structure 13 can be the structure for including metal column 131 and soldered ball 132, wherein, institute
State the one end of metal column 131 and connection, the other end and the soldered ball are contacted with the connection weld pad 121 in the semiconductor chip 12
132 contact connections.Certainly, in other examples, the solder-connected structure 13 can also be the structure for only including a soldered ball.
As an example, the solder-connected structure 13 contacts connection with the metal connecting line 112 in the re-wiring layer 11,
To ensure the semiconductor chip 12 via the metal connecting line 112 in the solder-connected structure 13 and the re-wiring layer 11
Electrical connection.
In step 3), S3 steps and Fig. 5 to Fig. 6 in Fig. 1 are referred to, in the second surface of the re-wiring layer 11
Form capsulation material layer 14, the gap and the semiconductor core that the capsulation material layer 14 is filled up between the semiconductor chip 12
Gap between piece 12 and the re-wiring layer 11, and by the plastic packaging of semiconductor chip 12.
As an example, compressing and forming process, transfer shaping technology, hydraulic seal moulding process, molding bottom can be used
Fill process, capillary underfill technique, vacuum lamination process or spin coating proceeding are in the second surface of the re-wiring layer 11
Form the capsulation material layer 14.Preferably, in the present embodiment, using molded underfill technique in the re-wiring layer 11
Second surface form the capsulation material layer 14, such capsulation material can promptly be filled in institute's semiconductor with smooth
The gap between gap and the semiconductor chip 12 and the re-wiring layer 11 between chip 12, can be effectively prevented from
There is interface debonding, and molded underfill will not be restricted as capillary underfill technique of the prior art, greatly
Technology difficulty is reduced greatly, can be used for smaller joint gap, be more suitable for stacked structure.
As an example, the material of the capsulation material layer 14 can be but be not limited only to polyimide layer, layer of silica gel, epoxy
Resin bed, the curable polymeric substrate bed of material or the curable resin base material bed of material.
In one example, the upper surface of the capsulation material layer 14 formed in the second surface of the re-wiring layer 11
Higher than the back side of the semiconductor chip 12, as shown in Figure 5；By the semiconductor chip 12 after plastic packaging via the cloth again
Line layer 11 is installed in before the upper surface of the circuit substrate 18, in addition to the step of remove part capsulation material layer 14,
To cause the upper surface of the capsulation material layer 14 and the back side flush of the semiconductor chip 12 that retain, as shown in Figure 6.
In another example, the capsulation material layer 14 can be formed according to the back side of the semiconductor chip 12 so that
The upper surface of the capsulation material layer 14 formed is just in the back side flush of the semiconductor chip 12.It can so save
Thinned technique is ground to the capsulation material layer 14, so as to reduce processing step, has saved manufacturing cost.
In step 4), the S4 steps in Fig. 1 are referred to, remove the Semiconductor substrate 10.
As an example, any one technique can be used to remove the Semiconductor substrate 10；Preferably, in the present embodiment,
The specific method for removing the Semiconductor substrate 10 is：First the Semiconductor substrate 10 is thinned using mechanical milling tech
Processing (for example, carries out reduction processing) to the Semiconductor substrate 10 using the emery wheel of different-grain diameter from the back side；Treat described half
Conductor substrate 10 is thinned to after certain thickness (now, the thickness of the Semiconductor substrate 10 of reservation is not easy empress dowager), then is adopted
The remaining Semiconductor substrate 10 is removed with chemical grinding technique (for example, to go by grinding technics using chemical grinding liquid etc.
Except the remaining Semiconductor substrate 10).
As an example, referring to Fig. 7, after removing the Semiconductor substrate 10, also it is included in the re-wiring layer 11
First surface formed connection soldered ball 15 the step of, it is described connection soldered ball 15 electrically connected with the re-wiring layer 11.
As an example, the material of the connection soldered ball 15 can be a kind of material or two in copper, aluminium, nickel, gold, silver, titanium
Kind and two or more combined materials, the connection soldered ball 15 can be formed by planting ball reflux technique.
As an example, referring to Fig. 8, multiple semiconductor chips 12, multiple semiconductor cores are provided in step 2)
12 equal face down of piece is installed in the second surface of the re-wiring layer 11, has spacing between adjacent semiconductor chips 12；
After the first surface of the re-wiring layer 11 forms connection soldered ball 15, in addition to the structure that step 4) is obtained is cut
The step of cutting, to obtain several structures to be packaged, include at least one semiconductor core in each structure to be packaged
Piece 12.Specifically, the structure that step 4) is obtained is adhered on a cutting indigo plant film 16, the back side of the semiconductor chip 12 and institute
The blue film 16 of cutting is stated to be in contact.Annular iron ring of the upper surface of the blue film 16 of cutting formed with the fixation blue film 16 of cutting
17, the structure that step 4) obtains adheres on the inner side of the annular iron ring 17.
As an example, after the structure that step 4) is obtained is adhered on the blue film 16 of cutting, can be cut using laser
Cut technique or carry out cutting separation between each semiconductor chip 12 using synthesizing knife, to obtain including described in one
The structure to be packaged of semiconductor chip 12.In another example, laser cutting parameter can also be used or use synthesizing knife
Cutting separation is carried out between two or more semiconductor chips 12, to obtain including two or more semiconductor cores
The structure to be packaged of piece 12, as shown in Figure 8.
In step 5), S5 steps and Fig. 9 in Fig. 1 are referred to, there is provided a circuit substrate 18, the circuit substrate 18
Upper surface is provided with the first connection weld pad 181, and the lower surface of the circuit substrate 18 is provided with the second connection weld pad 182, and described first
Connection weld pad 181 is connected weld pad 182 with described second and electrically connected；By the semiconductor chip 12 after plastic packaging via it is described again
Wiring layer 11 is installed in the upper surface of the circuit substrate 18, and the re-wiring layer 11 is connected the electricity of weld pad 181 with described first
Connection.
Electrically connected specifically, the re-wiring layer 11 is connected weld pad 181 via the connection soldered ball 15 with described first.
It should be noted that the circuit substrate 18 has been internally formed interconnection circuit, weld pad is connected by described first
181 are connected weld pad 182 with described second electrically connects, for the ease of diagram, the interconnection circuit inside the circuit substrate 18
And shown not in the drawings.
As an example, referring to Fig. 10, the semiconductor chip 12 after plastic packaging is filled via the re-wiring layer 11
After the upper surface of the circuit substrate 18, also it is included between the re-wiring layer 11 and the circuit substrate 18 and fills out
The step of filling a glue-line 19, the gap that described glue-line 19 is filled up between the re-wiring layer 11 and the circuit substrate 18.
Filled out specifically, can use but be not limited only to underfill process between the re-wiring layer 11 and the circuit substrate 18
Fill described glue-line 19.
As an example, referring to Figure 11, the point is filled between the re-wiring layer 11 and the circuit substrate 18
After glue-line 19, be also included in the circuit substrate 18 upper surface formed fin 20 the step of, the fin 20 buckle to
In the upper surface of the circuit substrate 18, to form sealing cavity 21 between the fin 20 and the circuit substrate 18；
The re-wiring layer 11, the semiconductor chip 12 and the capsulation material layer 14 are respectively positioned in the sealing cavity 21, and
The back side of the semiconductor chip 12 is in contact with the fin 20.The fin 20 can be played to the cloth again
The effect of line layer 11, the semiconductor chip 12 and the sealing protection of capsulation material layer 14, enhancing described half can be played again
The effect that conductor chip 12 radiates.Certainly, in other examples, the fin 20 can also be to adhere on the semiconductor core
The plate-shape metal plate at the back side of piece 12.
As an example, the fin 20 should have a preferable heat dispersion, the material of the fin 20 can be copper,
The metal materials such as aluminium, iron or metal alloy compositions.Certainly, in other examples, the good material of any heat dispersion is equal
Can be as the material of the fin 20.
As an example, please continue to refer to Figure 11, after forming fin 20 in the upper surface of the circuit substrate 18, also wrap
Include and form the structure of solder projection 22 in the lower surface of the circuit substrate 18, the solder projection 22 is connected weldering with described second
Pad 182 electrically connects
In one example, the structure that solder projection 22 is formed in the lower surface of the circuit substrate 18 comprises the following steps：
Metal column is formed in the lower surface of the circuit substrate 18；
Soldered ball is formed in the surface of the remote circuit substrate 18 of the metal column.
As an example, the material of the metal column can be copper, aluminium, nickel, gold, silver, a kind of material in titanium or two kinds and
Two or more combined materials, can by physical gas-phase deposition (PVD), chemical vapor deposition method (CVD), sputtering,
Any of plating or chemical plating technique form the metal column.The material of the soldered ball can be copper, aluminium, nickel, gold, silver,
A kind of material or two kinds and two or more combined materials in titanium, the soldered ball can be formed by planting ball reflux technique.
In another example, as shown in figure 11, the solder projection 22 is a soldered ball, can be by planting ball reflux technique
Soldered ball is directly formed as the solder projection 22.
Embodiment two
Please continue to refer to Figure 11, the present embodiment also provides a kind of 3D chip-packaging structures, the 3D chip-packaging structures bag
Include：Circuit substrate 18, the upper surface of the circuit substrate 18 are provided with the first connection weld pad 181, the following table of the circuit substrate 18
Face is provided with the second connection weld pad 182, and the first connection weld pad 181 is connected weld pad 182 with described second and electrically connected；Rewiring
Layer 11, the re-wiring layer 11 includes relative first surface and second surface, and the re-wiring layer 11 is via the first table
Face is installed in the upper surface of the circuit substrate 18, and is connected weld pad 181 with described first and electrically connects；Semiconductor chip 12, institute
The face down upside-down mounting of semiconductor chip 12 is stated in the second surface of the re-wiring layer 11, and it is electric with the re-wiring layer 11
Connection；Capsulation material layer 14, the plastic packaging of capsulation material layer 14 is in the periphery of the semiconductor chip 12, and the capsulation material
14 surface away from the re-wiring layer 11 of layer and the back side flush of the semiconductor chip 12；Solder projection 22, it is described
Solder projection 22 is located at the lower surface of the circuit substrate 18, and is connected weld pad 182 with described second and is connected.
It should be noted that the circuit substrate 18 has been internally formed interconnection circuit, weld pad is connected by described first
181 are connected weld pad 182 with described second electrically connects, for the ease of diagram, the interconnection circuit inside the circuit substrate 18
And shown not in the drawings.
As an example, the re-wiring layer 11 includes：Dielectric layer 111；Metal connecting line 112, the metal connecting line 112
In in the dielectric layer 111, the spacing between the line width of the metal connecting line 112 and the adjacent metal connecting line 112 is respectively less than 1
μm。
As an example, between the re-wiring layer 11 and the circuit substrate 18 be provided with connection soldered ball 15, it is described again
Wiring layer 11 is connected weld pad 181 with described first via the connection soldered ball 15 and electrically connected.The material of the connection soldered ball 15 can
Think a kind of material or two kinds and two or more combined materials in copper, aluminium, nickel, gold, silver, titanium, can be flowed back by planting ball
Technique forms the connection soldered ball 15.
As an example, the semiconductor chip 12 can be any one semiconductor functional chip, the semiconductor chip
12 front is formed with the connection weld pad 121 for drawing its inside function device electricity, a surface exposure of the connection weld pad 121
In the front of the semiconductor chip 12, i.e., a surface of described connection weld pad 121 and the positive phase of the semiconductor chip 12
Flush with or slightly higher than the front of the semiconductor chip 12.
As an example, solder-connected structure 13 is additionally provided between the semiconductor chip 12 and the re-wiring layer 11,
The semiconductor chip 12 is installed in (attach on) described re-wiring layer via the face down of solder-connected structure 13
11 second surface.
As an example, the solder-connected structure 13 can be the structure for including metal column 131 and soldered ball 132, wherein, institute
State the one end of metal column 131 and connection, the other end and the soldered ball are contacted with the connection weld pad 121 in the semiconductor chip 12
132 contact connections.Certainly, in other examples, the solder-connected structure 13 can also be the structure for only including a soldered ball.
As an example, the solder-connected structure 13 contacts connection with the metal connecting line 112 in the re-wiring layer 11,
To ensure the semiconductor chip 12 via the metal connecting line 112 in the solder-connected structure 13 and the re-wiring layer 11
Electrical connection.
As an example, the material of the capsulation material layer 14 can be but be not limited only to polyimide layer, layer of silica gel, epoxy
Resin bed, the curable polymeric substrate bed of material or the curable resin base material bed of material.
As an example, the 3D chip-packaging structures also include a point glue-line 19, described glue-line 19 be filled in it is described again
Between wiring layer 11 and the circuit substrate 18
In one example, the 3D chip-packaging structures also include fin 20, and the fin 20 is plate-shape metal plate,
The fin 20 adheres on the back side of the semiconductor chip 12.
In another example, the 3D chip-packaging structures also include fin 20, and the fin 20 is buckled as described
The upper surface of circuit substrate 18, to form sealing cavity 21 between the fin 20 and the circuit substrate 18；It is described heavy
New route layer 11, the semiconductor chip 12 and the capsulation material layer 14 are respectively positioned in the sealing cavity 21, and described half
The back side of conductor chip 12 is in contact with the fin 20.
In one example, the 3D chip-packaging structures include a semiconductor chip 12.
In another example, the 3D chip-packaging structures can also include two or more semiconductor chips 12.
Wherein, Figure 11 is used as example using the 3D chip-packaging structures including two semiconductor chips 12.
In summary, 3D chip-packaging structures of the invention and preparation method thereof, the 3D chip-packaging structures include：Electricity
Base board, the upper surface of the circuit substrate are provided with the first connection weld pad, and lower surface is provided with the second connection weld pad, and described first connects
Connect weld pad and be connected weld pad electrical connection with described second；Re-wiring layer, including relative first surface and second surface are described heavy
New route layer is installed in the upper surface of the circuit substrate via first surface, and is connected weld pad electrical connection with described first；Half
Conductor chip, face down upside-down mounting electrically connect in the second surface of the re-wiring layer, and with the re-wiring layer；Plastic packaging
Material layer, plastic packaging in the periphery of the semiconductor chip, and surface of the capsulation material layer away from the re-wiring layer with
The back side flush of the semiconductor chip；Solder projection, it is connected positioned at the lower surface of the circuit substrate, and with described second
Weld pad is connected.Re-wiring layer in the 3D chip-packaging structures of the present invention directly electrically connects with circuit substrate, it is not necessary in
Interlayer and silicon hole, whole encapsulating structure is fairly simple, and packaging cost is cheap；The line width of metal connecting line in re-wiring layer
And line spacing can reach less than 1 μm, so as to meet the needs of device performance raising.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (15)
1. a kind of 3D chip-packaging structures, it is characterised in that the 3D chip-packaging structures include：
Circuit substrate, the upper surface of the circuit substrate are provided with the first connection weld pad, and lower surface is provided with the second connection weld pad, described
First connection weld pad is connected weld pad electrical connection with described second；
Re-wiring layer, including relative first surface and second surface, the re-wiring layer are installed in via first surface
The upper surface of the circuit substrate, and it is connected weld pad electrical connection with described first；
Semiconductor chip, face down upside-down mounting are electrically connected in the second surface of the re-wiring layer, and with the re-wiring layer
Connect；
Capsulation material layer, plastic packaging is in the periphery of the semiconductor chip, and the capsulation material layer is away from the re-wiring layer
Surface and the semiconductor chip back side flush；
Solder projection, positioned at the lower surface of the circuit substrate, and it is connected weld pad with described second and is connected.
2. 3D chip-packaging structures according to claim 1, it is characterised in that：The re-wiring layer includes：
Dielectric layer；
Metal connecting line, in the dielectric layer, the spacing between the line width of the metal connecting line and the adjacent metal connecting line
Respectively less than 1 μm.
3. 3D chip-packaging structures according to claim 1, it is characterised in that：The 3D chip-packaging structures also include point
Glue-line, described glue-line are filled between the re-wiring layer and the circuit substrate.
4. 3D chip-packaging structures according to claim 1, it is characterised in that：The 3D chip-packaging structures also include dissipating
Backing, the fin adhere on the back side of the semiconductor chip.
5. 3D chip-packaging structures according to claim 1, it is characterised in that：The 3D chip-packaging structures also include dissipating
Backing, the fin buckle the upper surface as the circuit substrate, with the shape between the fin and the circuit substrate
Into sealing cavity；The re-wiring layer, the semiconductor chip and the capsulation material layer are respectively positioned in the sealing cavity,
And the back side of the semiconductor chip is in contact with the fin.
6. 3D chip-packaging structures according to claim 1, it is characterised in that：Described half in the 3D chip-packaging structures
The quantity of conductor chip is one.
7. 3D chip-packaging structures according to claim 1, it is characterised in that：Described half in the 3D chip-packaging structures
The quantity of conductor chip is at least two, has spacing between the adjacent semiconductor chip.
A kind of 8. preparation method of 3D chip-packaging structures, it is characterised in that the preparation method bag of the 3D chip-packaging structures
Include following steps：
1) semi-conductive substrate is provided, re-wiring layer, the re-wiring layer are formed in the upper surface of the Semiconductor substrate
Including relative first surface and second surface, wherein, the first surface of the re-wiring layer and the Semiconductor substrate
Upper surface is in contact；
2) semiconductor chip is provided, the semiconductor chip face down is installed in the second surface of the re-wiring layer；
3) capsulation material layer is formed in the second surface of the re-wiring layer, the capsulation material layer fills up the semiconductor core
The gap between gap and the semiconductor chip and the re-wiring layer between piece, and the semiconductor chip is moulded
Envelope；
4) Semiconductor substrate is removed；
5) circuit substrate is provided, the upper surface of the circuit substrate is provided with the first connection weld pad, and lower surface is provided with the second connection
Weld pad, the first connection weld pad are connected weld pad electrical connection with described second；By the semiconductor chip after plastic packaging via institute
The upper surface that re-wiring layer is installed in the circuit substrate is stated, the re-wiring layer is connected weld pad with described first and is electrically connected
Connect.
9. the preparation method of 3D chip-packaging structures according to claim 8, it is characterised in that：In step 1), in described
The upper surface of Semiconductor substrate forms re-wiring layer and comprised the following steps：
1-1) dielectric layer is formed in the upper surface of the Semiconductor substrate；
1-2) it is less than 1 μm in the groove that up/down perforation is formed in the dielectric layer, the width of the groove, and between adjacent trenches
Away from less than 1 μm；
1-3) in forming metal connecting line in the groove.
10. the preparation method of 3D chip-packaging structures according to claim 8, it is characterised in that：In step 3), in described
The upper surface for the capsulation material layer that the second surface of re-wiring layer is formed is higher than the back side of the semiconductor chip；Will modeling
The semiconductor chip being honored as a queen is installed in via the re-wiring layer before the upper surface of the circuit substrate, in addition to is gone
The step of capsulation material layer described except part, to cause the upper surface of the capsulation material layer of reservation and the semiconductor chip
Back side flush.
11. the preparation method of 3D chip-packaging structures according to claim 8, it is characterised in that：Described in step 4) removes
After Semiconductor substrate, the first surface for being also included in the re-wiring layer forms the step of connecting soldered ball, the connection weldering
Ball electrically connects with the re-wiring layer；In step 5), the re-wiring layer connects via the connection soldered ball with described first
Connect weld pad electrical connection.
12. the preparation method of 3D chip-packaging structures according to claim 11, it is characterised in that：There is provided in step 2) more
The individual semiconductor chip, multiple equal face downs of semiconductor chip are installed in the second surface of the re-wiring layer,
There is spacing between adjacent semiconductor chips；The structure for also including obtaining step 4) between step 4) and step 5) is cut
The step of, to obtain several structures to be packaged, include at least one semiconductor chip in each structure to be packaged；
In step 5), the semiconductor chip after the plastic packaging in the structure to be packaged is installed in institute via the re-wiring layer
State the upper surface of circuit substrate.
13. the preparation method of the 3D chip-packaging structures according to any one of claim 8 to 12, it is characterised in that：Step
It is rapid 5) after, the step of being also included in filling point glue-line between the re-wiring layer and the circuit substrate, described glue-line
The gap filled up between the re-wiring layer and the circuit substrate.
14. the preparation method of 3D chip-packaging structures according to claim 13, it is characterised in that：In the rewiring
Between layer and the circuit substrate after filling point glue-line, the upper surface for being also included in the circuit substrate forms the step of fin
Suddenly, the fin buckles the upper surface as the circuit substrate, to be formed between the fin and the circuit substrate
Sealing cavity；The re-wiring layer, the semiconductor chip and the capsulation material layer are respectively positioned in the sealing cavity, and
The back side of the semiconductor chip is in contact with the fin.
15. the preparation method of 3D chip-packaging structures according to claim 14, it is characterised in that：In the circuit substrate
Upper surface formed fin after, be also included in the circuit substrate lower surface formed solder projection structure, the weldering
Material projection is connected weld pad electrical connection with described second.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710954752.5A CN107785339A (en) | 2017-10-13 | 2017-10-13 | 3D chip-packaging structures and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710954752.5A CN107785339A (en) | 2017-10-13 | 2017-10-13 | 3D chip-packaging structures and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107785339A true CN107785339A (en) | 2018-03-09 |
Family
ID=61433613
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710954752.5A Pending CN107785339A (en) | 2017-10-13 | 2017-10-13 | 3D chip-packaging structures and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107785339A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111599700A (en) * | 2019-06-20 | 2020-08-28 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
| CN111640728A (en) * | 2020-04-21 | 2020-09-08 | 江苏长电科技股份有限公司 | Adapter plate easy for SIP packaging underfill and manufacturing method thereof |
| CN111952198A (en) * | 2020-08-25 | 2020-11-17 | 济南南知信息科技有限公司 | Semiconductor package and preparation method thereof |
| WO2021081855A1 (en) * | 2019-10-30 | 2021-05-06 | 华为技术有限公司 | Chip package on package structure and packaging method therefor, and electronic device |
| CN112802761A (en) * | 2021-01-07 | 2021-05-14 | 山东傲天环保科技有限公司 | Integrated circuit packaging structure and method |
| CN113130435A (en) * | 2019-12-31 | 2021-07-16 | 力成科技股份有限公司 | Package structure and method for manufacturing the same |
| CN113327899A (en) * | 2021-04-22 | 2021-08-31 | 成都芯源系统有限公司 | Flip chip packaging unit and packaging method |
| WO2024060694A1 (en) * | 2022-09-20 | 2024-03-28 | 盛合晶微半导体(江阴)有限公司 | Chip package structure and manufacturing method therefor |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6908784B1 (en) * | 2002-03-06 | 2005-06-21 | Micron Technology, Inc. | Method for fabricating encapsulated semiconductor components |
| US20080050901A1 (en) * | 2006-08-23 | 2008-02-28 | Micron Technology, Inc. | Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices |
| US20100133680A1 (en) * | 2008-12-03 | 2010-06-03 | Samsung Electro-Mechanics Co., Ltd. | Wafer level package and method of manufacturing the same and method of reusing chip |
| TW201312663A (en) * | 2011-09-09 | 2013-03-16 | Taiwan Semiconductor Mfg | Packaged semiconductor device and package for semiconductor device and method of packaging semiconductor device |
| CN104124176A (en) * | 2013-04-24 | 2014-10-29 | 万国半导体股份有限公司 | Method for preparation of semiconductor device used in flip installing process |
| CN104904006A (en) * | 2012-11-09 | 2015-09-09 | 安默克技术股份公司 | Semiconductor device and manufacturing method thereof |
| TW201546954A (en) * | 2014-01-28 | 2015-12-16 | 台灣積體電路製造股份有限公司 | Semiconductor device structure and fabricating method thereof |
| CN207250499U (en) * | 2017-10-13 | 2018-04-17 | 中芯长电半导体（江阴）有限公司 | 3D chip-packaging structures |
-
2017
- 2017-10-13 CN CN201710954752.5A patent/CN107785339A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6908784B1 (en) * | 2002-03-06 | 2005-06-21 | Micron Technology, Inc. | Method for fabricating encapsulated semiconductor components |
| US20080050901A1 (en) * | 2006-08-23 | 2008-02-28 | Micron Technology, Inc. | Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices |
| US20100133680A1 (en) * | 2008-12-03 | 2010-06-03 | Samsung Electro-Mechanics Co., Ltd. | Wafer level package and method of manufacturing the same and method of reusing chip |
| TW201312663A (en) * | 2011-09-09 | 2013-03-16 | Taiwan Semiconductor Mfg | Packaged semiconductor device and package for semiconductor device and method of packaging semiconductor device |
| CN104904006A (en) * | 2012-11-09 | 2015-09-09 | 安默克技术股份公司 | Semiconductor device and manufacturing method thereof |
| CN104124176A (en) * | 2013-04-24 | 2014-10-29 | 万国半导体股份有限公司 | Method for preparation of semiconductor device used in flip installing process |
| TW201546954A (en) * | 2014-01-28 | 2015-12-16 | 台灣積體電路製造股份有限公司 | Semiconductor device structure and fabricating method thereof |
| CN207250499U (en) * | 2017-10-13 | 2018-04-17 | 中芯长电半导体（江阴）有限公司 | 3D chip-packaging structures |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111599700A (en) * | 2019-06-20 | 2020-08-28 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
| WO2021081855A1 (en) * | 2019-10-30 | 2021-05-06 | 华为技术有限公司 | Chip package on package structure and packaging method therefor, and electronic device |
| CN113130435A (en) * | 2019-12-31 | 2021-07-16 | 力成科技股份有限公司 | Package structure and method for manufacturing the same |
| US11557533B2 (en) | 2019-12-31 | 2023-01-17 | Powertech Technology Inc. | Package structure and manufacturing method thereof |
| CN111640728A (en) * | 2020-04-21 | 2020-09-08 | 江苏长电科技股份有限公司 | Adapter plate easy for SIP packaging underfill and manufacturing method thereof |
| CN111952198A (en) * | 2020-08-25 | 2020-11-17 | 济南南知信息科技有限公司 | Semiconductor package and preparation method thereof |
| CN111952198B (en) * | 2020-08-25 | 2022-09-13 | 嘉兴启创科技咨询有限公司 | Semiconductor package and preparation method thereof |
| CN112802761A (en) * | 2021-01-07 | 2021-05-14 | 山东傲天环保科技有限公司 | Integrated circuit packaging structure and method |
| CN112802761B (en) * | 2021-01-07 | 2022-07-08 | 深圳市慧邦电子科技有限公司 | Integrated circuit packaging structure and method |
| CN113327899A (en) * | 2021-04-22 | 2021-08-31 | 成都芯源系统有限公司 | Flip chip packaging unit and packaging method |
| WO2024060694A1 (en) * | 2022-09-20 | 2024-03-28 | 盛合晶微半导体(江阴)有限公司 | Chip package structure and manufacturing method therefor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10446520B2 (en) | 3D semiconductor package interposer with die cavity | |
| CN107785339A (en) | 3D chip-packaging structures and preparation method thereof | |
| US10867897B2 (en) | PoP device | |
| TWI669785B (en) | Semiconductor packages and methods of forming same | |
| TWI670778B (en) | Package structures and methods of forming the same | |
| CN103681613B (en) | There is the semiconductor device of discrete area | |
| US20180182727A1 (en) | Embedded silicon substrate fan-out type packaging structure and manufacturing method therefor | |
| CN106169459A (en) | Semiconductor package and forming method thereof | |
| WO2018212785A1 (en) | Die encapsulation in oxide bonded wafer stack | |
| CN104377170B (en) | Semiconductor package and fabrication method thereof | |
| TW201814858A (en) | Semiconductor package and method of forming the same | |
| US20130252378A1 (en) | 3D Semiconductor Package Interposer with Die Cavity | |
| CN106169452A (en) | Semiconductor package and manufacture method thereof | |
| WO2017124671A1 (en) | Packaging method packaging structure for fan-out chip | |
| CN107706521A (en) | Fan-out-type antenna packages structure and preparation method thereof | |
| CN107301983A (en) | Fan-out package structure and preparation method thereof | |
| CN107527880A (en) | Fan-out package structure and preparation method thereof | |
| KR20140113266A (en) | Package-on-package structure and method of forming same | |
| CN107393885A (en) | Fan-out package structure and preparation method thereof | |
| CN107195551A (en) | Fan-out-type laminated packaging structure and preparation method thereof | |
| CN107611045A (en) | A kind of three-dimensional chip encapsulating structure and its method for packing | |
| CN107195625A (en) | Two-sided system-level laminated packaging structure of plastic packaging fan-out-type and preparation method thereof | |
| CN207250499U (en) | 3D chip-packaging structures | |
| CN207217505U (en) | Semiconductor structure and fan-out package structure | |
| CN207116414U (en) | The system-level fan-out package structures of 3D |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Applicant after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Applicant before: SJ Semiconductor (Jiangyin) Corp. |
|
| CB02 | Change of applicant information |