WO2017124671A1 - Packaging method packaging structure for fan-out chip - Google Patents

Packaging method packaging structure for fan-out chip Download PDF

Info

Publication number
WO2017124671A1
WO2017124671A1 PCT/CN2016/082832 CN2016082832W WO2017124671A1 WO 2017124671 A1 WO2017124671 A1 WO 2017124671A1 CN 2016082832 W CN2016082832 W CN 2016082832W WO 2017124671 A1 WO2017124671 A1 WO 2017124671A1
Authority
WO
WIPO (PCT)
Prior art keywords
fan
packaging
out type
bumps
type chip
Prior art date
Application number
PCT/CN2016/082832
Other languages
French (fr)
Chinese (zh)
Inventor
仇月东
林正忠
Original Assignee
中芯长电半导体（江阴）有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中芯长电半导体（江阴）有限公司 filed Critical 中芯长电半导体（江阴）有限公司
Publication of WO2017124671A1 publication Critical patent/WO2017124671A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Definitions

  • the present invention relates to a semiconductor chip packaging method and package structure, and more particularly to a fan-out type chip packaging method and package structure.
  • the existing packaging technologies include ball grid array package (BGA), chip size package (CSP), and wafer level package (WLP). ), three-dimensional packaging (3D) and system packaging (SiP).
  • BGA ball grid array package
  • CSP chip size package
  • WLP wafer level package
  • 3D three-dimensional packaging
  • SiP system packaging
  • the wafer-level package (WLP) is gradually adopted by most semiconductor manufacturers due to its excellent advantages. All or most of the process steps are completed on the silicon wafer that has completed the pre-process, and finally the wafer is finished. Cut directly into separate, independent devices.
  • Wafer-level package has its unique advantages: 1 package processing efficiency, can be processed simultaneously with multiple wafers; 2 with the advantages of flip chip packaging, namely light, thin, short, small; 3 and the previous process Than, just added two steps of pin rewiring (RDL) and bump fabrication, the rest are all traditional processes; 4 reduces the number of tests in traditional packages. Therefore, the world's major IC packaging companies have invested in the research, development and production of such WLP.
  • the semiconductor chip 203 in which the initial bumps 104 are formed in advance is generally pasted on the film 102 of the carrier 101, as shown in FIG. 1a, and then the molding material is used.
  • 105 is molded, as shown in Fig. 1b, after the plastic sealing, the carrier 101 and the film 102 are removed, as shown in Fig. 1c, after which the rewiring layer 106 is formed and the bumps 107 are formed, as shown in Fig. 1d.
  • the molding material has a large thermal expansion coefficient, which causes deformation and bending of the metal bumps, especially the breakage of the initial bumps. , which greatly affects the performance of the packaged product.
  • an object of the present invention is to provide a method for packaging a fan-out type chip for solving the problem of low package quality of a semiconductor chip with an initial bump in the prior art.
  • the present invention provides a method of packaging a fan-out type chip, the fan-out type
  • the packaging method comprises: step 1), providing a chip with bumps, forming a dielectric layer on the surface of the chip, the surface of the dielectric layer exposing each bump; and step 2) providing a carrier having an adhesive layer formed on the surface And bonding each of the bumped chips to the adhesive layer; step 3), packaging each of the bumped chips; and step 4) forming a rewiring layer on each of the bumped chips to An interconnection between the chips is implemented; and in step 5), an under bump metal layer and micro bumps are formed on the rewiring layer.
  • the method further includes the step of removing the carrier and the adhesive layer.
  • the carrier comprises one of glass, a transparent semiconductor material, and a transparent polymer.
  • the adhesive layer comprises a UV adhesive, and in the step 6), the UV adhesive is reduced in viscosity by an exposure method to achieve separation from the molding material.
  • the dielectric layer includes one of silicon dioxide, phosphosilicate glass, silicon oxycarbide, silicon carbide, and a polymer.
  • a dielectric layer is formed on the surface of the chip by spin coating, chemical vapor deposition or plasma enhanced chemical vapor deposition.
  • the height of the molding material after packaging each of the bump-equipped chips does not exceed the height of each of the bumps, so that the bumps are exposed to the plastic package.
  • the surface of the material is not limited to the surface of the material.
  • the molding material used for packaging each of the bump-equipped chips includes one of polyimide, silica gel and epoxy resin. .
  • the process of packaging each of the bump-equipped chips includes: an injection molding process, a compression molding process, a printing process, and a transfer molding process.
  • an injection molding process a compression molding process, a printing process, and a transfer molding process.
  • the step 4) comprises: step 4-1), forming an insulating medium on each of the bumped chips; and step 4-2) using a photolithography process And forming an via hole corresponding to the electrical extraction of the chip in the insulating medium; and filling the metal conductor into each of the through holes to form a connection via hole; step 4-4)
  • the surface of the insulating medium forms a metal wiring layer correspondingly connected to the connection via.
  • the metal wiring layer is formed by an evaporation process, a sputtering process, an electroplating process, or an electroless plating process.
  • the material of the metal wiring layer includes one of aluminum, copper, tin, nickel, gold, and silver.
  • the micro bumps include gold solder balls, silver tin One of a solder ball or a copper solder ball, or the micro bump includes a copper pillar, a nickel layer formed on the copper pillar, and a solder ball formed on the nickel layer.
  • the invention further provides a package structure of a fan-out type chip, comprising: a chip with a bump, a surface of the chip is formed with a dielectric layer, the surface of the dielectric layer is exposed with each bump; a plastic sealing material is filled in each strip Between the chips of the bumps, the height of the molding material does not exceed the bumps so that the bumps are exposed on the surface of the molding material; and the rewiring layer is formed on the surface of each of the bumped chips to realize the chips. Inter-connector; and under-bump metal layers and micro-bumps are formed over the re-wiring layer.
  • the dielectric layer includes one of silicon dioxide, phosphosilicate glass, silicon oxycarbide, silicon carbide, and a polymer.
  • the molding material includes one of polyimide, silica gel, and epoxy resin.
  • the rewiring layer includes: an insulating medium formed on each of the bump-equipped chips; formed in the insulating medium and the chip electrical lead-out a corresponding through hole; a metal conductor filled in the through hole; and a metal wiring layer formed on the surface of the insulating medium and correspondingly connected to the connection via.
  • the material of the metal wiring layer includes one of aluminum, copper, tin, nickel, gold, and silver.
  • the micro bumps comprise one of a gold solder ball, a silver solder ball, and a copper solder ball.
  • the microbumps comprise a copper pillar, a nickel layer formed on the copper pillar, and a solder ball formed on the nickel layer.
  • the package method and package structure of the fan-out type chip of the present invention have the following advantageous effects: the present invention forms a dielectric layer on the surface of the chip with bumps, and the bumps are exposed on the surface of the dielectric layer. Not only can each bump be protected, but also interconnection between subsequent chips can be realized. Selecting a dielectric layer with a lower thermal expansion coefficient can avoid the breakage or breakage of the bump due to thermal expansion during the subsequent fabrication of the rewiring layer or the solder microbump, thereby greatly improving the performance of the package while improving the yield. .
  • the structure method of the invention is simple and has broad application prospects in the field of semiconductor packaging.
  • FIG. 1a to FIG. 1d are schematic diagrams showing the steps of the steps of the packaging method of a fan-out type chip in the prior art.
  • FIGS. 2 to 9 are schematic diagrams showing the steps of the steps of the package method of the fan-out type chip of the present invention.
  • the embodiment provides a method for packaging a fan-out type chip, and the fan-out type packaging method includes:
  • step 1) is performed to provide a chip 201 with bumps 203, and a dielectric layer 204 is formed on the surface of the chip, and the bumps 203 are exposed on the surface of the dielectric layer 204.
  • step 1-1) is performed to provide a wafer of the chip 201 with the bumps 203, and a dielectric layer 204 is formed on the surface of the wafer, and the surface of the dielectric layer 204 is exposed. Bump 203.
  • the dielectric layer 204 includes one of silicon dioxide, phosphosilicate glass, silicon oxycarbide, silicon carbide, and a polymer.
  • the dielectric layer 204 is selected as a material having a low coefficient of thermal expansion, which can avoid the damage or breakage of the bumps 203 due to thermal expansion during the subsequent fabrication of the rewiring layer 208 or the solder microbumps 211. The performance of the package while improving the yield.
  • the dielectric layer 204 may be formed on the surface of the chip by spin coating, chemical vapor deposition, or plasma enhanced chemical vapor deposition.
  • the dielectric layer 204 is a silicon dioxide layer formed by ion-enhanced chemical vapor deposition.
  • step 1-2 is then performed to split the wafer to obtain a separate chip with bumps 203 and dielectric layer 204.
  • the bumps 203 are fabricated on the metal pads 202 of the chip.
  • step 2) is then performed to provide a carrier 205 having an adhesive layer 206 formed on its surface, and the chips 201 of each bump 203 are bonded to the adhesive layer 206.
  • the adhesive layer 206 may be a material such as a tape, a UV adhesive formed by spin coating, or an epoxy resin.
  • the adhesive layer 206 is a UV adhesive formed by spin coating. In combination with the glue, the UV adhesive is less viscous under ultraviolet light.
  • the carrier 205 may be a glass, a ceramic, a metal, a polymer, or the like.
  • the carrier 205 includes one of glass, a transparent semiconductor material, and a transparent polymer, so that Exposure of the UV adhesive described above from the back side of the carrier 205 greatly simplifies the subsequent stripping process.
  • step 3 is followed to package the chips 201 with the bumps 203.
  • the height of the molding material 207 after the package 201 of each of the bumps 203 is not higher than the bumps 203 so that the bumps 203 are exposed on the surface of the molding material 207.
  • the molding material 207 used for encapsulating the chips 201 each having the bumps 203 includes one of polyimide, silica gel, and epoxy resin. Wherein, the molding material 207 is added by an additive to form an opaque material.
  • the processes for packaging the chips 201 with the bumps 203 include: an injection molding process, a compression molding process, a printing process, a transfer molding process, a liquid sealant curing process, a vacuum lamination process, and a spin coating process.
  • an injection molding process a compression molding process
  • a printing process a transfer molding process
  • a liquid sealant curing process a vacuum lamination process
  • a spin coating process a spin coating process.
  • the chips 201 with the bumps 203 are encapsulated by an injection molding process
  • the molding material 207 is an opaque silica gel.
  • step 4) is then performed to form a rewiring layer 208 on each of the chips 201 with bumps 203 to achieve interconnection between the chips.
  • step 4) includes:
  • Step 4-1) forming an insulating medium on each of the chips 201 with the bumps 203;
  • Step 4-2) forming a through hole corresponding to the electrical extraction of the chip in the insulating medium by using a photolithography process and an etching process;
  • Step 4-3) filling each of the through holes with a metal conductor to form a connection through hole
  • Step 4-4) forming a metal wiring layer 209 corresponding to the connection via hole on the surface of the insulating medium.
  • the metal wiring layer 209 is formed by an evaporation process, a sputtering process, an electroplating process, or an electroless plating process.
  • the metal wiring layer 209 is formed by a sputtering process.
  • the material of the metal wiring layer 209 includes one of aluminum, copper, tin, nickel, gold, and silver. In the embodiment, the material of the metal wiring layer 209 is copper.
  • step 5 is followed to form the under bump metal layer 210 and the micro bumps 211 on the rewiring layer 208.
  • the micro bumps 211 include one of a gold solder ball, a silver solder ball, and a copper solder ball, or the micro bumps 211 include a copper pillar, a nickel layer formed on the copper pillar, And a solder ball formed on the nickel layer.
  • the micro bumps 211 are gold solder balls, and the manufacturing process includes the steps of: first forming a gold tin layer on the surface of the under bump metal layer 210, and then using a high temperature reflow process to make the gold tin layer It is reflowed into a spherical shape, and after cooling, a gold solder ball is formed.
  • step 6 is performed to remove the carrier 205 and the adhesive layer 206.
  • the carrier 205 includes one of glass, a transparent semiconductor material, and a transparent polymer.
  • the adhesive layer 206 includes a UV adhesive, and in the step 6), the UV adhesive is reduced in viscosity by an exposure method to achieve separation from the molding material 207.
  • the embodiment further provides a package structure of a fan-out type chip, comprising: a chip 201 with a bump 203, a surface of the chip is formed with a dielectric layer 204, and a surface of the dielectric layer 204 is exposed.
  • each of the bumps 203; the molding material 207 is filled between the chips 201 of each of the bumps 203, the height of the molding material 207 does not exceed the bumps 203, so that the bumps 203 are exposed on the surface of the molding material 207;
  • a rewiring layer 208 is formed on the surface of each of the chips 201 with bumps 203 to realize interconnection between the chips; and a under bump metal layer 210 and micro bumps 211 are formed on the rewiring layer 208 .
  • the dielectric layer 204 includes one of silicon dioxide, phosphosilicate glass, silicon oxycarbide, silicon carbide, and a polymer.
  • the molding material 207 includes one of polyimide, silica gel, and epoxy resin.
  • the re-wiring layer 208 includes: an insulating medium formed on each of the chips 201 with the bumps 203; a through hole formed in the insulating medium corresponding to the electrical extraction of the chip; filling the through holes a metal conductor inside; and a metal wiring layer 209 formed on the surface of the insulating medium and correspondingly connected to the connection via.
  • the material of the metal wiring layer 209 includes one of aluminum, copper, tin, nickel, gold, and silver.
  • the microbumps 211 include one of a gold solder ball, a silver solder ball, and a copper solder ball.
  • the microbumps 211 include copper pillars, a nickel layer formed on the copper pillars, and solder balls formed on the nickel layers.
  • the package method and package structure of the fan-out type chip of the present invention have the following advantageous effects: the present invention forms the dielectric layer 204 on the surface of the chip 201 with the bumps 203, and the surface of the dielectric layer 204 is exposed. Each bump 203 can not only protect each bump 203, but also realize interconnection between subsequent chips. Selecting the dielectric layer 204 having a lower coefficient of thermal expansion can avoid the damage or breakage of the bumps 203 due to thermal expansion during the subsequent fabrication of the rewiring layer 208 or the solder microbumps 211, thereby greatly improving the performance of the package. At the same time improve the yield.
  • the structure method of the invention is simple and has broad application prospects in the field of semiconductor packaging. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A packaging method and a packaging structure for a fan-out chip. The packaging structure comprises: chips (201) provided with projecting blocks (203), a dielectric layer (204) being formed on the surfaces of the chips (201), and the projecting blocks (203) being exposed from the surfaces; a plastic packaging material (207) filled among the chips (201) provided with the projecting blocks (203), the height of the plastic packaging material (207) being not greater than those of the projecting blocks so as to enable the projecting blocks (203) to be exposed from the surface of the plastic packaging material (207); a rewiring layer (208) formed on the surfaces of the chips (201) provided with the projecting blocks (203), so as to implement interconnection among the chips (201); and projecting block lower metal layers (210); and micro projecting points (211). The dielectric layer (204) exposing the projecting blocks (203) is formed on the surfaces of the chips (201) provided with the projecting blocks (203), the projecting blocks (203) are protected, the subsequent interconnection among the chips (201) is implemented, and damaged or broken conditions of the projecting blocks (203) caused by thermal expansion in the subsequent processes for manufacturing the rewiring layer (208) or solder micro projecting points (211) are avoided, so that the packaging performance is substantially improved, and the rate of finished products is improved.

Description

一种扇出型芯片的封装方法及封装结构Method and package structure for fan-out type chip 技术领域Technical field
本发明涉及一种半导体芯片的封装方法及封装结构，特别是涉及一种扇出型芯片的封装方法及封装结构。The present invention relates to a semiconductor chip packaging method and package structure, and more particularly to a fan-out type chip packaging method and package structure.
背景技术Background technique
随着集成电路制造业的快速发展，人们对集成电路的封装技术的要求也不断提高，现有的封装技术包括球栅阵列封装(BGA)、芯片尺寸封装(CSP)、圆片级封装(WLP)、三维封装(3D)和系统封装(SiP)等。其中，圆片级封装(WLP)由于其出色的优点逐渐被大部分的半导体制造者所采用，它的全部或大部分工艺步骤是在已完成前工序的硅圆片上完成的，最后将圆片直接切割成分离的独立器件。圆片级封装(WLP)具有其独特的优点：①封装加工效率高，可以多个圆片同时加工；②具有倒装芯片封装的优点，即轻、薄、短、小；③与前工序相比，只是增加了引脚重新布线(RDL)和凸点制作两个工序，其余全部是传统工艺；④减少了传统封装中的多次测试。因此世界上各大型IC封装公司纷纷投入这类WLP的研究、开发和生产。With the rapid development of the integrated circuit manufacturing industry, the requirements for packaging technology of integrated circuits are also increasing. The existing packaging technologies include ball grid array package (BGA), chip size package (CSP), and wafer level package (WLP). ), three-dimensional packaging (3D) and system packaging (SiP). Among them, the wafer-level package (WLP) is gradually adopted by most semiconductor manufacturers due to its excellent advantages. All or most of the process steps are completed on the silicon wafer that has completed the pre-process, and finally the wafer is finished. Cut directly into separate, independent devices. Wafer-level package (WLP) has its unique advantages: 1 package processing efficiency, can be processed simultaneously with multiple wafers; 2 with the advantages of flip chip packaging, namely light, thin, short, small; 3 and the previous process Than, just added two steps of pin rewiring (RDL) and bump fabrication, the rest are all traditional processes; 4 reduces the number of tests in traditional packages. Therefore, the world's major IC packaging companies have invested in the research, development and production of such WLP.
在现有的扇出型芯片封装技术中，切割后的半导体芯片大多数不会带有凸块，然而，在实际生产过程中，可能遇到一些的异常问题，例如，如何封装预先形成有初始凸块的半导体芯片，或者如何实现预先形成有初始凸块的芯片以及不带有初始凸块的芯片之间的互连。In the existing fan-out chip packaging technology, most of the semiconductor chips after cutting do not have bumps. However, in the actual production process, some abnormal problems may be encountered, for example, how the package is pre-formed with an initial The semiconductor chip of the bump, or how to realize the interconnection between the chip in which the initial bump is formed and the chip without the initial bump.
如图1a～图1d所示，在现有的工艺中，一般是先将预先形成有初始凸块104的半导体芯片203粘贴于载体101的贴膜102上，如图1a所示，然后采用塑封材料105进行塑封，如图1b所示，塑封之后将载体101及贴膜102去除，如图1c所示，之后会制作重新布线层106以及制作凸块107，如图1d所示。在之后的重新布线层工艺以及凸块回流工艺的过程中，塑封材料由于具有较大的热膨胀系数，从而会使金属凸块出现变形弯曲等问题，尤其是容易造成初始凸块的破损断裂等情况，从而大大影响封装产品的性能。As shown in FIG. 1a to FIG. 1d, in the prior art, the semiconductor chip 203 in which the initial bumps 104 are formed in advance is generally pasted on the film 102 of the carrier 101, as shown in FIG. 1a, and then the molding material is used. 105 is molded, as shown in Fig. 1b, after the plastic sealing, the carrier 101 and the film 102 are removed, as shown in Fig. 1c, after which the rewiring layer 106 is formed and the bumps 107 are formed, as shown in Fig. 1d. In the subsequent rewiring layer process and the bump reflow process, the molding material has a large thermal expansion coefficient, which causes deformation and bending of the metal bumps, especially the breakage of the initial bumps. , which greatly affects the performance of the packaged product.
鉴于以上原因，提供一种能够提高带有初始凸块的半导体芯片的封装质量的方法实属必要。In view of the above, it is necessary to provide a method capable of improving the package quality of a semiconductor chip with an initial bump.
发明内容Summary of the invention
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种扇出型芯片的封装方法，用于解决现有技术中带有初始凸块的半导体芯片的封装质量不高的问题。In view of the above disadvantages of the prior art, an object of the present invention is to provide a method for packaging a fan-out type chip for solving the problem of low package quality of a semiconductor chip with an initial bump in the prior art.
为实现上述目的及其他相关目的，本发明提供一种扇出型芯片的封装方法，所述扇出型 封装方法包括：步骤1)，提供带凸块的芯片，于所述芯片表面形成介质层，所述介质层的表面露出有各凸块；步骤2)，提供一表面形成有粘合层的载体，并将各带凸块的芯片粘合于所述粘合层；步骤3)，对各带凸块的芯片进行封装；步骤4)，于各带凸块的芯片上形成重新布线层，以实现各芯片之间的互连；以及步骤5)，于所述重新布线层上形成凸块下金属层以及微凸点。To achieve the above and other related objects, the present invention provides a method of packaging a fan-out type chip, the fan-out type The packaging method comprises: step 1), providing a chip with bumps, forming a dielectric layer on the surface of the chip, the surface of the dielectric layer exposing each bump; and step 2) providing a carrier having an adhesive layer formed on the surface And bonding each of the bumped chips to the adhesive layer; step 3), packaging each of the bumped chips; and step 4) forming a rewiring layer on each of the bumped chips to An interconnection between the chips is implemented; and in step 5), an under bump metal layer and micro bumps are formed on the rewiring layer.
作为本发明的扇出型芯片的封装方法的一种优选方案，还包括步骤6)，去除所述载体以及粘合层。As a preferred embodiment of the package method of the fan-out type chip of the present invention, the method further includes the step of removing the carrier and the adhesive layer.
作为本发明的扇出型芯片的封装方法的一种优选方案，所述载体包括玻璃、透明半导体材料、以及透明聚合物中的一种。As a preferred embodiment of the encapsulation method of the fan-out type chip of the present invention, the carrier comprises one of glass, a transparent semiconductor material, and a transparent polymer.
进一步地，所述粘合层包括UV粘合胶，步骤6)中，采用曝光方法使所述UV粘合胶降低黏性，以实现其与塑封材料的分离。Further, the adhesive layer comprises a UV adhesive, and in the step 6), the UV adhesive is reduced in viscosity by an exposure method to achieve separation from the molding material.
作为本发明的扇出型芯片的封装方法的一种优选方案，所述介质层包括二氧化硅、磷硅玻璃、碳氧化硅、碳化硅、以及聚合物中的一种。As a preferred embodiment of the packaging method of the fan-out type chip of the present invention, the dielectric layer includes one of silicon dioxide, phosphosilicate glass, silicon oxycarbide, silicon carbide, and a polymer.
作为本发明的扇出型芯片的封装方法的一种优选方案，采用旋涂法、化学气相沉积法或等离子增强化学气相沉积法于所述芯片表面形成介质层。As a preferred embodiment of the encapsulation method of the fan-out type chip of the present invention, a dielectric layer is formed on the surface of the chip by spin coating, chemical vapor deposition or plasma enhanced chemical vapor deposition.
作为本发明的扇出型芯片的封装方法的一种优选方案，步骤3)中，对各带凸块的芯片进行封装后的塑封材料高度不超过各凸块，以使各凸块露出于塑封材料的表面。As a preferred solution of the method for packaging the fan-out type chip of the present invention, in step 3), the height of the molding material after packaging each of the bump-equipped chips does not exceed the height of each of the bumps, so that the bumps are exposed to the plastic package. The surface of the material.
作为本发明的扇出型芯片的封装方法的一种优选方案，步骤3)中，对各带凸块的芯片进行封装采用的塑封材料包括聚酰亚胺、硅胶以及环氧树脂中的一种。As a preferred solution of the method for packaging the fan-out type chip of the present invention, in the step 3), the molding material used for packaging each of the bump-equipped chips includes one of polyimide, silica gel and epoxy resin. .
作为本发明的扇出型芯片的封装方法的一种优选方案，步骤3)中，对各带凸块的芯片进行封装采用的工艺包括：注塑工艺、压缩成型工艺、印刷工艺、传递模塑工艺、液体密封剂固化成型工艺、真空层压工艺以及旋涂工艺中的一种。As a preferred solution of the package method of the fan-out type chip of the present invention, in the step 3), the process of packaging each of the bump-equipped chips includes: an injection molding process, a compression molding process, a printing process, and a transfer molding process. One of a liquid sealant curing molding process, a vacuum lamination process, and a spin coating process.
作为本发明的扇出型芯片的封装方法的一种优选方案，步骤4)包括：步骤4-1)，于各带凸块的芯片上形成绝缘介质；步骤4-2)，采用光刻工艺及刻蚀工艺于所述绝缘介质中形成与芯片电性引出所对应的通孔；步骤4-3)，于各通孔中填充金属导体，形成连接通孔；步骤4-4)，于所述绝缘介质表面形成与所述连接通孔对应连接的金属布线层。As a preferred solution of the method for packaging the fan-out type chip of the present invention, the step 4) comprises: step 4-1), forming an insulating medium on each of the bumped chips; and step 4-2) using a photolithography process And forming an via hole corresponding to the electrical extraction of the chip in the insulating medium; and filling the metal conductor into each of the through holes to form a connection via hole; step 4-4) The surface of the insulating medium forms a metal wiring layer correspondingly connected to the connection via.
优选地，步骤4-4)中，采用蒸镀工艺、溅射工艺、电镀工艺或化学镀工艺制作所述金属布线层。Preferably, in step 4-4), the metal wiring layer is formed by an evaporation process, a sputtering process, an electroplating process, or an electroless plating process.
优选地，所述金属布线层的材料包括铝、铜、锡、镍、金及银中的一种。Preferably, the material of the metal wiring layer includes one of aluminum, copper, tin, nickel, gold, and silver.
作为本发明的扇出型芯片的封装方法的一种优选方案，所述微凸点包括金锡焊球、银锡 焊球、铜锡焊球中的一种，或者，所述微凸点包括铜柱，形成于铜柱上的镍层、以及形成于所述镍层上的焊球。As a preferred solution of the package method of the fan-out type chip of the present invention, the micro bumps include gold solder balls, silver tin One of a solder ball or a copper solder ball, or the micro bump includes a copper pillar, a nickel layer formed on the copper pillar, and a solder ball formed on the nickel layer.
本发明还提供一种扇出型芯片的封装结构，包括：带凸块的芯片，所述芯片表面形成有介质层，所述介质层的表面露出有各凸块；塑封材料，填充于各带凸块的芯片之间，所述塑封材料的高度不超过各凸块，以使各凸块露出于塑封材料的表面；重新布线层，形成于各带凸块的芯片表面，以实现各芯片之间的互连；以及凸块下金属层以及微凸点，形成于所述重新布线层之上。The invention further provides a package structure of a fan-out type chip, comprising: a chip with a bump, a surface of the chip is formed with a dielectric layer, the surface of the dielectric layer is exposed with each bump; a plastic sealing material is filled in each strip Between the chips of the bumps, the height of the molding material does not exceed the bumps so that the bumps are exposed on the surface of the molding material; and the rewiring layer is formed on the surface of each of the bumped chips to realize the chips. Inter-connector; and under-bump metal layers and micro-bumps are formed over the re-wiring layer.
作为本发明的扇出型芯片的封装结构的一种优选方案，所述介质层包括二氧化硅、磷硅玻璃、碳氧化硅、碳化硅、以及聚合物中的一种。As a preferred embodiment of the package structure of the fan-out type chip of the present invention, the dielectric layer includes one of silicon dioxide, phosphosilicate glass, silicon oxycarbide, silicon carbide, and a polymer.
作为本发明的扇出型芯片的封装结构的一种优选方案，所述塑封材料包括聚酰亚胺、硅胶以及环氧树脂中的一种。As a preferred embodiment of the package structure of the fan-out type chip of the present invention, the molding material includes one of polyimide, silica gel, and epoxy resin.
作为本发明的扇出型芯片的封装结构的一种优选方案，所述重新布线层包括：形成于各带凸块的芯片上的绝缘介质；形成于所述绝缘介质中与芯片电性引出所对应的通孔；填充于所述通孔内的金属导体；以及形成于所述绝缘介质表面与所述连接通孔对应连接的金属布线层。As a preferred embodiment of the package structure of the fan-out type chip of the present invention, the rewiring layer includes: an insulating medium formed on each of the bump-equipped chips; formed in the insulating medium and the chip electrical lead-out a corresponding through hole; a metal conductor filled in the through hole; and a metal wiring layer formed on the surface of the insulating medium and correspondingly connected to the connection via.
优选地，所述金属布线层的材料包括铝、铜、锡、镍、金及银中的一种。Preferably, the material of the metal wiring layer includes one of aluminum, copper, tin, nickel, gold, and silver.
优选地，所述微凸点包括金锡焊球、银锡焊球、铜锡焊球中的一种。Preferably, the micro bumps comprise one of a gold solder ball, a silver solder ball, and a copper solder ball.
优选地，所述微凸点包括铜柱，形成于铜柱上的镍层、以及形成于所述镍层上的焊球。Preferably, the microbumps comprise a copper pillar, a nickel layer formed on the copper pillar, and a solder ball formed on the nickel layer.
如上所述，本发明的扇出型芯片的封装方法及封装结构，具有以下有益效果：本发明通过在带凸块的芯片表面形成介质层，且所述介质层的表面露出有各凸块，不仅可以对各凸块进行保护，且可以实现后续芯片之间的互连。选择热膨胀系数较低的介质层，可以避免后续制作重新布线层或焊料微凸点的过程中，由于热膨胀而导致的凸块的破损或断裂等情况，大大提高了封装的性能，同时提高成品率。本发明结构方法简单，在半导体封装领域具有广泛的应用前景。As described above, the package method and package structure of the fan-out type chip of the present invention have the following advantageous effects: the present invention forms a dielectric layer on the surface of the chip with bumps, and the bumps are exposed on the surface of the dielectric layer. Not only can each bump be protected, but also interconnection between subsequent chips can be realized. Selecting a dielectric layer with a lower thermal expansion coefficient can avoid the breakage or breakage of the bump due to thermal expansion during the subsequent fabrication of the rewiring layer or the solder microbump, thereby greatly improving the performance of the package while improving the yield. . The structure method of the invention is simple and has broad application prospects in the field of semiconductor packaging.
附图说明DRAWINGS
图1a～图1d显示为现有技术中的一种扇出型芯片的封装方法各步骤所呈现的结构示意图。FIG. 1a to FIG. 1d are schematic diagrams showing the steps of the steps of the packaging method of a fan-out type chip in the prior art.
图2～图9显示为本发明的扇出型芯片的封装方法各步骤所呈现的结构示意图。2 to 9 are schematic diagrams showing the steps of the steps of the package method of the fan-out type chip of the present invention.
元件标号说明 Component label description
201    带凸块的芯片201 chip with bump
202    金属焊盘202 metal pad
203    凸块203 bump
204    介质层204 dielectric layer
205    载体205 carrier
206    粘合层206 adhesive layer
207    塑封材料207 plastic packaging material
208    重新布线层208 rewiring layer
209    金属布线层209 metal wiring layer
210    凸块下金属层210 under bump metal layer
211    微凸点211 micro bumps
具体实施方式detailed description
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention.
请参阅图2～图9。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。Please refer to Figures 2-9. It should be noted that the illustrations provided in the embodiments merely illustrate the basic concept of the present invention in a schematic manner, and only the components related to the present invention are shown in the drawings, rather than the number and shape of components in actual implementation. Dimensional drawing, the actual type of implementation of each component's type, number and proportion can be a random change, and its component layout can be more complicated.
如图2～图9所示，本实施例提供一种扇出型芯片的封装方法，所述扇出型封装方法包括：As shown in FIG. 2 to FIG. 9 , the embodiment provides a method for packaging a fan-out type chip, and the fan-out type packaging method includes:
如图2～图4所示，首先进行步骤1)，提供带凸块203的芯片201，于所述芯片表面形成介质层204，所述介质层204的表面露出有各凸块203。As shown in FIG. 2 to FIG. 4, first, step 1) is performed to provide a chip 201 with bumps 203, and a dielectric layer 204 is formed on the surface of the chip, and the bumps 203 are exposed on the surface of the dielectric layer 204.
具体地，包括以下步骤：Specifically, the following steps are included:
如图2及图3所示，首先进行步骤1-1)，提供带凸块203的芯片201的晶圆，于所述晶圆表面形成介质层204，所述介质层204的表面露出有各凸块203。As shown in FIG. 2 and FIG. 3, first, step 1-1) is performed to provide a wafer of the chip 201 with the bumps 203, and a dielectric layer 204 is formed on the surface of the wafer, and the surface of the dielectric layer 204 is exposed. Bump 203.
作为示例，所述介质层204包括二氧化硅、磷硅玻璃、碳氧化硅、碳化硅、以及聚合物中的一种。所述介质层204选用为热膨胀系数较低的材料，可以避免后续制作重新布线层208或焊料微凸点211的过程中，由于热膨胀而导致的凸块203的破损或断裂等情况，大大提高 了封装的性能，同时提高成品率。As an example, the dielectric layer 204 includes one of silicon dioxide, phosphosilicate glass, silicon oxycarbide, silicon carbide, and a polymer. The dielectric layer 204 is selected as a material having a low coefficient of thermal expansion, which can avoid the damage or breakage of the bumps 203 due to thermal expansion during the subsequent fabrication of the rewiring layer 208 or the solder microbumps 211. The performance of the package while improving the yield.
作为示例，可以采用旋涂法、化学气相沉积法或等离子增强化学气相沉积法于所述芯片表面形成介质层204。As an example, the dielectric layer 204 may be formed on the surface of the chip by spin coating, chemical vapor deposition, or plasma enhanced chemical vapor deposition.
在本实施例中，所述介质层204为采用离子增强化学气相沉积法形成的二氧化硅层。In the present embodiment, the dielectric layer 204 is a silicon dioxide layer formed by ion-enhanced chemical vapor deposition.
如图4所示，然后进行步骤1-2)，对所述晶圆进行裂片，获得独立的带凸块203以及介质层204的芯片。As shown in FIG. 4, step 1-2) is then performed to split the wafer to obtain a separate chip with bumps 203 and dielectric layer 204.
作为示例，所述凸块203制作于芯片的金属焊盘202上。As an example, the bumps 203 are fabricated on the metal pads 202 of the chip.
如图5所示，然后进行步骤2)，提供一表面形成有粘合层206的载体205，并将各带凸块203的芯片201粘合于所述粘合层206。As shown in FIG. 5, step 2) is then performed to provide a carrier 205 having an adhesive layer 206 formed on its surface, and the chips 201 of each bump 203 are bonded to the adhesive layer 206.
作为示例，所述粘合层206可以为如胶带、通过旋涂形成的UV粘合胶或者环氧树脂等材料，在本实施例中，所述粘合层206为通过旋涂形成的UV粘合胶，该UV粘合胶在紫外光照射下黏性会降低。As an example, the adhesive layer 206 may be a material such as a tape, a UV adhesive formed by spin coating, or an epoxy resin. In the embodiment, the adhesive layer 206 is a UV adhesive formed by spin coating. In combination with the glue, the UV adhesive is less viscous under ultraviolet light.
作为示例，所述载体205可以为玻璃、陶瓷、金属、聚合物等材料，在本实施例中，所述载体205包括玻璃、透明半导体材料、以及透明聚合物中的一种，以使得后续可以从载体205的背面对上述的UV粘合胶进行曝光操作，大大简化后续的剥离工艺。As an example, the carrier 205 may be a glass, a ceramic, a metal, a polymer, or the like. In the embodiment, the carrier 205 includes one of glass, a transparent semiconductor material, and a transparent polymer, so that Exposure of the UV adhesive described above from the back side of the carrier 205 greatly simplifies the subsequent stripping process.
如图6所示，接着进行步骤3)，对各带凸块203的芯片201进行封装。As shown in FIG. 6, step 3) is followed to package the chips 201 with the bumps 203.
作为示例，对各带凸块203的芯片201进行封装后的塑封材料207高度不超过各凸块203，以使各凸块203露出于塑封材料207的表面。As an example, the height of the molding material 207 after the package 201 of each of the bumps 203 is not higher than the bumps 203 so that the bumps 203 are exposed on the surface of the molding material 207.
作为示例，对各带凸块203的芯片201进行封装采用的塑封材料207包括聚酰亚胺、硅胶以及环氧树脂中的一种。其中，所述塑封材料207添通过添加剂而形成不透光材料。As an example, the molding material 207 used for encapsulating the chips 201 each having the bumps 203 includes one of polyimide, silica gel, and epoxy resin. Wherein, the molding material 207 is added by an additive to form an opaque material.
作为示例，对各带凸块203的芯片201进行封装采用的工艺包括：注塑工艺、压缩成型工艺、印刷工艺、传递模塑工艺、液体密封剂固化成型工艺、真空层压工艺以及旋涂工艺中的一种。在本实施例中，通过注塑工艺对各带凸块203的芯片201进行封装，所述塑封材料207为不透光的硅胶。As an example, the processes for packaging the chips 201 with the bumps 203 include: an injection molding process, a compression molding process, a printing process, a transfer molding process, a liquid sealant curing process, a vacuum lamination process, and a spin coating process. One kind. In this embodiment, the chips 201 with the bumps 203 are encapsulated by an injection molding process, and the molding material 207 is an opaque silica gel.
如图7所示，然后进行步骤4)，于各带凸块203的芯片201上形成重新布线层208，以实现各芯片之间的互连。As shown in FIG. 7, step 4) is then performed to form a rewiring layer 208 on each of the chips 201 with bumps 203 to achieve interconnection between the chips.
作为示例，步骤4)包括：As an example, step 4) includes:
步骤4-1)，于各带凸块203的芯片201上形成绝缘介质；Step 4-1), forming an insulating medium on each of the chips 201 with the bumps 203;
步骤4-2)，采用光刻工艺及刻蚀工艺于所述绝缘介质中形成与芯片电性引出所对应的通孔； Step 4-2), forming a through hole corresponding to the electrical extraction of the chip in the insulating medium by using a photolithography process and an etching process;
步骤4-3)，于各通孔中填充金属导体，形成连接通孔；Step 4-3), filling each of the through holes with a metal conductor to form a connection through hole;
步骤4-4)，于所述绝缘介质表面形成与所述连接通孔对应连接的金属布线层209。Step 4-4), forming a metal wiring layer 209 corresponding to the connection via hole on the surface of the insulating medium.
作为示例，步骤4-4)中，采用蒸镀工艺、溅射工艺、电镀工艺或化学镀工艺制作所述金属布线层209。在本实施例中，采用溅射工艺制作所述金属布线层209。As an example, in the step 4-4), the metal wiring layer 209 is formed by an evaporation process, a sputtering process, an electroplating process, or an electroless plating process. In the present embodiment, the metal wiring layer 209 is formed by a sputtering process.
作为示例，所述金属布线层209的材料包括铝、铜、锡、镍、金及银中的一种。在本实施例中，所述金属布线层209的材料为铜。As an example, the material of the metal wiring layer 209 includes one of aluminum, copper, tin, nickel, gold, and silver. In the embodiment, the material of the metal wiring layer 209 is copper.
如图8所示，接着进行步骤5)，于所述重新布线层208上形成凸块下金属层210以及微凸点211。As shown in FIG. 8, step 5) is followed to form the under bump metal layer 210 and the micro bumps 211 on the rewiring layer 208.
作为示例，所述微凸点211包括金锡焊球、银锡焊球、铜锡焊球中的一种，或者，所述微凸点211包括铜柱，形成于铜柱上的镍层、以及形成于所述镍层上的焊球。在本实施例中，所述微凸点211为金锡焊球，其制作包括步骤：首先于所述凸块下金属层210表面形成金锡层，然后采用高温回流工艺使所述金锡层回流成球状，降温后形成金锡焊球。As an example, the micro bumps 211 include one of a gold solder ball, a silver solder ball, and a copper solder ball, or the micro bumps 211 include a copper pillar, a nickel layer formed on the copper pillar, And a solder ball formed on the nickel layer. In this embodiment, the micro bumps 211 are gold solder balls, and the manufacturing process includes the steps of: first forming a gold tin layer on the surface of the under bump metal layer 210, and then using a high temperature reflow process to make the gold tin layer It is reflowed into a spherical shape, and after cooling, a gold solder ball is formed.
如图9所示，最后进行步骤6)，去除所述载体205以及粘合层206。As shown in FIG. 9, finally step 6) is performed to remove the carrier 205 and the adhesive layer 206.
作为示例，所述载体205包括玻璃、透明半导体材料、以及透明聚合物中的一种。As an example, the carrier 205 includes one of glass, a transparent semiconductor material, and a transparent polymer.
作为示例，所述粘合层206包括UV粘合胶，步骤6)中，采用曝光方法使所述UV粘合胶降低黏性，以实现其与塑封材料207的分离。As an example, the adhesive layer 206 includes a UV adhesive, and in the step 6), the UV adhesive is reduced in viscosity by an exposure method to achieve separation from the molding material 207.
如图9所示，本实施例还提供一种扇出型芯片的封装结构，包括：带凸块203的芯片201，所述芯片表面形成有介质层204，所述介质层204的表面露出有各凸块203；塑封材料207，填充于各带凸块203的芯片201之间，所述塑封材料207的高度不超过各凸块203，以使各凸块203露出于塑封材料207的表面；重新布线层208，形成于各带凸块203的芯片201表面，以实现各芯片之间的互连；以及凸块下金属层210以及微凸点211，形成于所述重新布线层208之上。As shown in FIG. 9, the embodiment further provides a package structure of a fan-out type chip, comprising: a chip 201 with a bump 203, a surface of the chip is formed with a dielectric layer 204, and a surface of the dielectric layer 204 is exposed. Each of the bumps 203; the molding material 207 is filled between the chips 201 of each of the bumps 203, the height of the molding material 207 does not exceed the bumps 203, so that the bumps 203 are exposed on the surface of the molding material 207; A rewiring layer 208 is formed on the surface of each of the chips 201 with bumps 203 to realize interconnection between the chips; and a under bump metal layer 210 and micro bumps 211 are formed on the rewiring layer 208 .
作为示例，所述介质层204包括二氧化硅、磷硅玻璃、碳氧化硅、碳化硅、以及聚合物中的一种。As an example, the dielectric layer 204 includes one of silicon dioxide, phosphosilicate glass, silicon oxycarbide, silicon carbide, and a polymer.
作为示例，所述塑封材料207包括聚酰亚胺、硅胶以及环氧树脂中的一种。As an example, the molding material 207 includes one of polyimide, silica gel, and epoxy resin.
作为示例，所述重新布线层208包括：形成于各带凸块203的芯片201上的绝缘介质；形成于所述绝缘介质中与芯片电性引出所对应的通孔；填充于所述通孔内的金属导体；以及形成于所述绝缘介质表面与所述连接通孔对应连接的金属布线层209。As an example, the re-wiring layer 208 includes: an insulating medium formed on each of the chips 201 with the bumps 203; a through hole formed in the insulating medium corresponding to the electrical extraction of the chip; filling the through holes a metal conductor inside; and a metal wiring layer 209 formed on the surface of the insulating medium and correspondingly connected to the connection via.
作为示例，所述金属布线层209的材料包括铝、铜、锡、镍、金及银中的一种。As an example, the material of the metal wiring layer 209 includes one of aluminum, copper, tin, nickel, gold, and silver.
作为示例，所述微凸点211包括金锡焊球、银锡焊球、铜锡焊球中的一种。 As an example, the microbumps 211 include one of a gold solder ball, a silver solder ball, and a copper solder ball.
作为示例，所述微凸点211包括铜柱，形成于铜柱上的镍层、以及形成于所述镍层上的焊球。As an example, the microbumps 211 include copper pillars, a nickel layer formed on the copper pillars, and solder balls formed on the nickel layers.
如上所述，本发明的扇出型芯片的封装方法及封装结构，具有以下有益效果：本发明通过在带凸块203的芯片201表面形成介质层204，且所述介质层204的表面露出有各凸块203，不仅可以对各凸块203进行保护，且可以实现后续芯片之间的互连。选择热膨胀系数较低的介质层204，可以避免后续制作重新布线层208或焊料微凸点211的过程中，由于热膨胀而导致的凸块203的破损或断裂等情况，大大提高了封装的性能，同时提高成品率。本发明结构方法简单，在半导体封装领域具有广泛的应用前景。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。As described above, the package method and package structure of the fan-out type chip of the present invention have the following advantageous effects: the present invention forms the dielectric layer 204 on the surface of the chip 201 with the bumps 203, and the surface of the dielectric layer 204 is exposed. Each bump 203 can not only protect each bump 203, but also realize interconnection between subsequent chips. Selecting the dielectric layer 204 having a lower coefficient of thermal expansion can avoid the damage or breakage of the bumps 203 due to thermal expansion during the subsequent fabrication of the rewiring layer 208 or the solder microbumps 211, thereby greatly improving the performance of the package. At the same time improve the yield. The structure method of the invention is simple and has broad application prospects in the field of semiconductor packaging. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。 The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications or variations of the above-described embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and scope of the invention will be covered by the appended claims.

Claims (20)

  1. 一种扇出型芯片的封装方法，其特征在于，所述扇出型封装方法包括：A method for packaging a fan-out type chip, characterized in that the fan-out type packaging method comprises:
    步骤1)，提供带凸块的芯片，于所述芯片表面形成介质层，所述介质层的表面露出有各凸块；Step 1), providing a chip with bumps, forming a dielectric layer on the surface of the chip, the surface of the dielectric layer is exposed with bumps;
    步骤2)，提供一表面形成有粘合层的载体，并将各带凸块的芯片粘合于所述粘合层；Step 2), providing a carrier having an adhesive layer formed on the surface, and bonding each of the bumped chips to the adhesive layer;
    步骤3)，对各带凸块的芯片进行封装；Step 3), packaging each chip with bumps;
    步骤4)，于各带凸块的芯片上形成重新布线层，以实现各芯片之间的互连；Step 4), forming a rewiring layer on each of the bumped chips to realize interconnection between the chips;
    步骤5)，于所述重新布线层上形成凸块下金属层以及微凸点。Step 5), forming an under bump metal layer and micro bumps on the rewiring layer.
  2. 根据权利要求1所述的扇出型芯片的封装方法，其特征在于：还包括步骤6)，去除所述载体以及粘合层。The method of packaging a fan-out type chip according to claim 1, further comprising the step of: removing the carrier and the adhesive layer.
  3. 根据权利要求1所述的扇出型芯片的封装方法，其特征在于：所述载体包括玻璃、透明半导体材料、以及透明聚合物中的一种。The method of packaging a fan-out type chip according to claim 1, wherein the carrier comprises one of glass, a transparent semiconductor material, and a transparent polymer.
  4. 根据权利要求3所述的扇出型芯片的封装方法，其特征在于：所述粘合层包括UV粘合胶，步骤6)中，采用曝光方法使所述UV粘合胶降低黏性，以实现其与塑封材料的分离。The method of packaging a fan-out type chip according to claim 3, wherein the adhesive layer comprises a UV adhesive, and in the step 6), the UV adhesive is reduced in viscosity by an exposure method, Achieve separation from the molding material.
  5. 根据权利要求1所述的扇出型芯片的封装方法，其特征在于：所述介质层包括二氧化硅、磷硅玻璃、碳氧化硅、碳化硅、以及聚合物中的一种。The method of packaging a fan-out type chip according to claim 1, wherein the dielectric layer comprises one of silicon dioxide, phosphosilicate glass, silicon oxycarbide, silicon carbide, and a polymer.
  6. 根据权利要求1所述的扇出型芯片的封装方法，其特征在于：采用旋涂法、化学气相沉积法或等离子增强化学气相沉积法于所述芯片表面形成介质层。The method of packaging a fan-out type chip according to claim 1, wherein a dielectric layer is formed on the surface of the chip by spin coating, chemical vapor deposition or plasma enhanced chemical vapor deposition.
  7. 根据权利要求1所述的扇出型芯片的封装方法，其特征在于：步骤3)中，对各带凸块的芯片进行封装后的塑封材料高度不超过各凸块，以使各凸块露出于塑封材料的表面。The method of packaging a fan-out type chip according to claim 1, wherein in step 3), the height of the molding material after encapsulation of each of the bump-equipped chips does not exceed the height of each of the bumps, so that the bumps are exposed. On the surface of the plastic packaging material.
  8. 根据权利要求1所述的扇出型芯片的封装方法，其特征在于：步骤3)中，对各带凸块的芯片进行封装采用的塑封材料包括聚酰亚胺、硅胶以及环氧树脂中的一种。The method for packaging a fan-out type chip according to claim 1, wherein in the step 3), the plastic sealing material used for packaging each of the bumped chips comprises polyimide, silica gel and epoxy resin. One.
  9. 根据权利要求1所述的扇出型芯片的封装方法，其特征在于：步骤3)中，对各带凸块的 芯片进行封装采用的工艺包括：注塑工艺、压缩成型工艺、印刷工艺、传递模塑工艺、液体密封剂固化成型工艺、真空层压工艺以及旋涂工艺中的一种。The method of packaging a fan-out type chip according to claim 1, wherein in step 3), each of the bumps is The process for packaging the chip includes: an injection molding process, a compression molding process, a printing process, a transfer molding process, a liquid sealant curing process, a vacuum lamination process, and a spin coating process.
  10. 根据权利要求1所述的扇出型芯片的封装方法，其特征在于：步骤4)包括：The method of packaging a fan-out type chip according to claim 1, wherein the step 4) comprises:
    步骤4-1)，于各带凸块的芯片上形成绝缘介质；Step 4-1), forming an insulating medium on each of the bumped chips;
    步骤4-2)，采用光刻工艺及刻蚀工艺于所述绝缘介质中形成与芯片电性引出所对应的通孔；Step 4-2), forming a through hole corresponding to the electrical extraction of the chip in the insulating medium by using a photolithography process and an etching process;
    步骤4-3)，于各通孔中填充金属导体，形成连接通孔；Step 4-3), filling each of the through holes with a metal conductor to form a connection through hole;
    步骤4-4)，于所述绝缘介质表面形成与所述连接通孔对应连接的金属布线层。Step 4-4), forming a metal wiring layer corresponding to the connection via hole on the surface of the insulating medium.
  11. 根据权利要求10所述的扇出型芯片的封装方法，其特征在于：步骤4-4)中，采用蒸镀工艺、溅射工艺、电镀工艺或化学镀工艺制作所述金属布线层。The method of packaging a fan-out type chip according to claim 10, wherein in the step 4-4), the metal wiring layer is formed by an evaporation process, a sputtering process, an electroplating process, or an electroless plating process.
  12. 根据权利要求10所述的扇出型芯片的封装方法，其特征在于：所述金属布线层的材料包括铝、铜、锡、镍、金及银中的一种。The method of packaging a fan-out type chip according to claim 10, wherein the material of the metal wiring layer comprises one of aluminum, copper, tin, nickel, gold, and silver.
  13. 根据权利要求1所述的扇出型芯片的封装方法，其特征在于：所述微凸点包括金锡焊球、银锡焊球、铜锡焊球中的一种，或者，所述微凸点包括铜柱，形成于铜柱上的镍层、以及形成于所述镍层上的焊球。The method of packaging a fan-out type chip according to claim 1, wherein the microbumps comprise one of a gold solder ball, a silver solder ball, and a copper solder ball, or the micro convex The dots include copper pillars, a nickel layer formed on the copper pillars, and solder balls formed on the nickel layers.
  14. 一种扇出型芯片的封装结构，其特征在于，包括：A package structure of a fan-out type chip, comprising:
    带凸块的芯片，所述芯片表面形成有介质层，所述介质层的表面露出有各凸块；a chip with a bump, a surface of the chip is formed with a dielectric layer, and a surface of the dielectric layer is exposed with a bump;
    塑封材料，填充于各带凸块的芯片之间，所述塑封材料的高度不超过各凸块，以使各凸块露出于塑封材料的表面；a molding material filled between the bumped chips, the height of the molding material not exceeding the bumps, so that the bumps are exposed on the surface of the molding material;
    重新布线层，形成于各带凸块的芯片表面，以实现各芯片之间的互连；Rewiring layers are formed on the surface of each of the bumped chips to achieve interconnection between the chips;
    凸块下金属层以及微凸点，形成于所述重新布线层之上。A bump under metal layer and micro bumps are formed over the rewiring layer.
  15. 根据权利要求14所述的扇出型芯片的封装结构，其特征在于：所述介质层包括二氧化硅、磷硅玻璃、碳氧化硅、碳化硅、以及聚合物中的一种。The package structure of a fan-out type chip according to claim 14, wherein the dielectric layer comprises one of silicon dioxide, phosphosilicate glass, silicon oxycarbide, silicon carbide, and a polymer.
  16. 根据权利要求14所述的扇出型芯片的封装结构，其特征在于：所述塑封材料包括聚 酰亚胺、硅胶以及环氧树脂中的一种。The package structure of a fan-out type chip according to claim 14, wherein the molding material comprises a poly One of an imide, a silica gel, and an epoxy resin.
  17. 根据权利要求14所述的扇出型芯片的封装结构，其特征在于：所述重新布线层包括：The package structure of a fan-out type chip according to claim 14, wherein the rewiring layer comprises:
    形成于各带凸块的芯片上的绝缘介质；An insulating medium formed on each of the bumped chips;
    形成于所述绝缘介质中与芯片电性引出所对应的通孔；a through hole corresponding to the electrical lead of the chip formed in the insulating medium;
    填充于所述通孔内的金属导体；以及a metal conductor filled in the through hole;
    形成于所述绝缘介质表面与所述连接通孔对应连接的金属布线层。a metal wiring layer formed on the surface of the insulating medium and correspondingly connected to the connection via.
  18. 根据权利要求17所述的扇出型芯片的封装结构，其特征在于：所述金属布线层的材料包括铝、铜、锡、镍、金及银中的一种。The package structure of a fan-out type chip according to claim 17, wherein the material of the metal wiring layer comprises one of aluminum, copper, tin, nickel, gold, and silver.
  19. 根据权利要求17所述的扇出型芯片的封装结构，其特征在于：所述微凸点包括金锡焊球、银锡焊球、铜锡焊球中的一种。The package structure of the fan-out type chip according to claim 17, wherein the micro bumps comprise one of a gold solder ball, a silver solder ball, and a copper solder ball.
  20. 根据权利要求17所述的扇出型芯片的封装结构，其特征在于：所述微凸点包括铜柱，形成于铜柱上的镍层、以及形成于所述镍层上的焊球。 The package structure of a fan-out type chip according to claim 17, wherein the microbumps comprise copper pillars, a nickel layer formed on the copper pillars, and solder balls formed on the nickel layer.
PCT/CN2016/082832 2016-01-22 2016-05-20 Packaging method packaging structure for fan-out chip WO2017124671A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610046689.0A CN105489516A (en) 2016-01-22 2016-01-22 Packaging method of fan-out type chip, and packaging structure
CN201610046689.0 2016-01-22

Publications (1)

Publication Number Publication Date
WO2017124671A1 true WO2017124671A1 (en) 2017-07-27

Family

ID=55676421

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/082832 WO2017124671A1 (en) 2016-01-22 2016-05-20 Packaging method packaging structure for fan-out chip

Country Status (2)

Country Link
CN (1) CN105489516A (en)
WO (1) WO2017124671A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113192936A (en) * 2021-04-23 2021-07-30 泓林微电子（昆山）有限公司 Double-sided chip packaging structure
CN113380637A (en) * 2021-05-20 2021-09-10 苏州通富超威半导体有限公司 Fan-out type packaging method and fan-out type packaging device

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105489516A (en) * 2016-01-22 2016-04-13 中芯长电半导体（江阴）有限公司 Packaging method of fan-out type chip, and packaging structure
CN111968958B (en) 2016-12-30 2022-08-19 华为技术有限公司 Packaged chip and signal transmission method based on packaged chip
CN106920784A (en) * 2017-03-31 2017-07-04 华进半导体封装先导技术研发中心有限公司 The fan-out package structure and method for packing of a kind of power electronic devices
US10325868B2 (en) 2017-04-24 2019-06-18 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
CN109686716A (en) * 2018-11-28 2019-04-26 中国电子科技集团公司第五十八研究所 Wafer scale is fanned out to the wafer architecture of encapsulation and is fanned out to packaging technology using the wafer scale of the wafer architecture
CN109755375A (en) * 2019-03-20 2019-05-14 中芯长电半导体（江阴）有限公司 The encapsulating structure and packaging method of fan-out-type LED
CN109755376A (en) * 2019-03-20 2019-05-14 中芯长电半导体（江阴）有限公司 The encapsulating structure and packaging method of fan-out-type LED
CN112180128B (en) * 2020-09-29 2023-08-01 珠海天成先进半导体科技有限公司 Interconnection substrate with elastic conductive micro-bumps and KGD socket based on interconnection substrate
WO2023015480A1 (en) * 2021-08-11 2023-02-16 华为技术有限公司 Fan-out chip package structure and preparation method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130001776A1 (en) * 2011-06-28 2013-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structure for Wafer Level Package
US20140197535A1 (en) * 2012-05-18 2014-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
CN105489516A (en) * 2016-01-22 2016-04-13 中芯长电半导体（江阴）有限公司 Packaging method of fan-out type chip, and packaging structure

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3888302B2 (en) * 2002-12-24 2007-02-28 カシオ計算機株式会社 Semiconductor device
US9117682B2 (en) * 2011-10-11 2015-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of packaging semiconductor devices and structures thereof
US9263511B2 (en) * 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9368460B2 (en) * 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
CN104952743A (en) * 2015-05-19 2015-09-30 南通富士通微电子股份有限公司 Wafer level chip package method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130001776A1 (en) * 2011-06-28 2013-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structure for Wafer Level Package
US20140197535A1 (en) * 2012-05-18 2014-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
CN105489516A (en) * 2016-01-22 2016-04-13 中芯长电半导体（江阴）有限公司 Packaging method of fan-out type chip, and packaging structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113192936A (en) * 2021-04-23 2021-07-30 泓林微电子（昆山）有限公司 Double-sided chip packaging structure
CN113380637A (en) * 2021-05-20 2021-09-10 苏州通富超威半导体有限公司 Fan-out type packaging method and fan-out type packaging device
CN113380637B (en) * 2021-05-20 2023-11-17 苏州通富超威半导体有限公司 Fan-out type packaging method and fan-out type packaging device

Also Published As

Publication number Publication date
CN105489516A (en) 2016-04-13

Similar Documents

Publication Publication Date Title
WO2017124671A1 (en) Packaging method packaging structure for fan-out chip
US10971467B2 (en) Packaging method and package structure of fan-out chip
TWI646609B (en) Three-layer package upper package structure and manufacturing method thereof
WO2017024794A1 (en) Wafer level chip encapsulation method
US20180233441A1 (en) PoP Device
WO2017024847A1 (en) Wafer level chip packaging method
WO2017041519A1 (en) Chip packaging method
US20130203215A1 (en) Packaging Methods for Semiconductor Devices
US20130154062A1 (en) Die Structure and Method of Fabrication Thereof
CN104716103A (en) Underfill Pattern with Gap
TW201906127A (en) Semiconductor package and method manufacturing the same
TW201523806A (en) Package structure and methods of forming the same
WO2017024846A1 (en) Wafer level chip packaging method
CN105810593B (en) A kind of fan-out package structure and its packaging method
CN205355040U (en) Packaging structure of fan -out cake core
CN109037082B (en) Package structure and method for forming the same
CN110379721A (en) Fan-out package method and encapsulating structure
US11735564B2 (en) Three-dimensional chip packaging structure and method thereof
CN115692222A (en) Chip packaging structure and preparation method
CN212392233U (en) Wafer level chip packaging structure
CN108962766B (en) Package structure and method for forming the same
CN108962772B (en) Package structure and method for forming the same
CN110828430A (en) Packaging structure and preparation method thereof
CN205542754U (en) Packaging structure of fan -out cake core
CN210516718U (en) Packaging structure

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16885934

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16885934

Country of ref document: EP

Kind code of ref document: A1