CN110828430A - Packaging structure and preparation method thereof - Google Patents

Packaging structure and preparation method thereof Download PDF

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Publication number
CN110828430A
CN110828430A CN201911078754.8A CN201911078754A CN110828430A CN 110828430 A CN110828430 A CN 110828430A CN 201911078754 A CN201911078754 A CN 201911078754A CN 110828430 A CN110828430 A CN 110828430A
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China
Prior art keywords
layer
semiconductor chip
rewiring
rewiring layer
electrically connected
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CN201911078754.8A
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Chinese (zh)
Inventor
林章申
陈彦亨
林正忠
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SJ Semiconductor Jiangyin Corp
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SJ Semiconductor Jiangyin Corp
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Priority to CN201911078754.8A priority Critical patent/CN110828430A/en
Publication of CN110828430A publication Critical patent/CN110828430A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

The invention provides a packaging structure and a preparation method thereof, wherein the packaging structure comprises: a second rewiring layer; a first rewiring layer electrically connected to the second rewiring layer; a semiconductor chip, which is upside down mounted on the second surface of the first rewiring layer with the front surface facing downwards and is electrically connected with the first rewiring layer; the plastic packaging layer is plastically packaged at the periphery of the semiconductor chip, and the surface of the plastic packaging layer, which is far away from the first rewiring layer, is flush with the back surface of the semiconductor chip; a heat sink in contact with a back surface of the semiconductor chip; and the ball grid array is arranged on the lower surface of the second rewiring layer and is electrically connected with the second rewiring layer. The invention can effectively reduce the packaging thickness by using the rewiring layer to replace the circuit substrate; through two rewiring layers, the use of a silicon middle layer and a silicon through hole is avoided, and the cost is reduced; the line width and the line distance can be less than 2 mu m, and the requirement of small line width is met.

Description

Packaging structure and preparation method thereof
Technical Field
The invention relates to the field of semiconductor technology packaging, in particular to a packaging structure and a preparation method thereof.
Background
With the trend of multi-functionalization and miniaturization of electronic products, high-density microelectronic assembly technology is becoming mainstream in new generation of electronic products. In order to match the development of the new generation of electronic products, especially the development of products such as smart phones, palm computers, super books and the like, the size of the chip is developed towards the directions of higher density, higher speed, smaller size, thinner thickness, lower cost and the like.
Three-dimensional integrated circuits utilize through-silicon vias to interconnect multiple stacked wafers in the vertical direction, and 2.5D integrated circuits utilize silicon interposer to interconnect multiple wafers or three-dimensional integrated circuits in the horizontal direction through-silicon vias and rewiring layer transmission lines. However, when the line width and the line distance are less than 2 μm, a silicon intermediate layer is required to be used between the chip and the PCB, and then through silicon vias are required, but the manufacturing cost of the technology is very high, and the packaging thickness is increased.
Therefore, in the semiconductor chip package, how to satisfy the requirement of small line width and reduce the package thickness is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above drawbacks of the prior art, the present invention is directed to a package structure and a manufacturing method thereof, which are used to solve the problems of high cost, complex process and thick package thickness of the prior art.
To achieve the above and other related objects, the present invention provides a package structure, comprising:
a second rewiring layer having an upper surface and a lower surface corresponding to the upper surface;
a first rewiring layer provided with a first surface and a second surface corresponding to the first surface, the first rewiring layer being mounted on an upper surface of the first rewiring layer via the first surface, the first rewiring layer being electrically connected to the second rewiring layer;
a semiconductor chip, which is upside down mounted on the second surface of the first rewiring layer with the front surface facing downwards and is electrically connected with the first rewiring layer;
the plastic packaging layer is plastically packaged at the periphery of the semiconductor chip, and the surface of the plastic packaging layer, which is far away from the first rewiring layer, is flush with the back surface of the semiconductor chip;
a heat sink in contact with a back surface of the semiconductor chip;
and the solder ball array is arranged on the lower surface of the second re-wiring layer and is electrically connected with the second re-wiring layer.
Optionally, a filler layer is further included, the filler layer filling a gap between the semiconductor chip and the first re-wiring layer.
Optionally, the second redistribution layer and the first redistribution layer respectively include a dielectric layer and a metal stack structure located in the dielectric layer, where the metal stack structure includes a plurality of metal line layers arranged at intervals and metal plugs located between adjacent metal line layers to electrically connect the adjacent metal line layers.
Optionally, the material of the dielectric layer comprises SiO2PI or PBO.
Optionally, the heat sink includes a heat sink, and the back surface of the semiconductor chip is in contact with the heat sink.
Optionally, the number of the semiconductor chips in the package structure includes at least two, the plurality of semiconductor chips are flip-mounted face down on the second surface of the first redistribution layer, and a space is provided between adjacent semiconductor chips.
The invention also provides a preparation method of the packaging structure, which comprises the following steps:
1) providing a carrier plate, wherein the carrier plate is provided with an upper surface and a lower surface corresponding to the upper surface, a first rewiring layer is formed on the upper surface of the carrier plate, the first rewiring layer is provided with a first surface and a second surface corresponding to the first surface, and the first surface of the first rewiring layer is in contact with the upper surface of the carrier plate;
2) providing a semiconductor chip, and inversely placing the semiconductor chip on the second surface of the first rewiring layer, wherein the semiconductor chip is electrically connected with the first rewiring layer;
3) forming a plastic packaging layer on the surface of the structure formed in the step 2);
4) removing the carrier plate to expose the first rewiring layer;
5) forming a second redistribution layer on the first surface of the first redistribution layer, wherein the second redistribution layer is provided with an upper surface and a lower surface corresponding to the upper surface, the second redistribution layer is electrically connected with the first redistribution layer through the upper surface, and a ball grid array is formed on the lower surface of the second redistribution layer and is electrically connected with the second redistribution layer;
6) removing part of the plastic packaging layer so that the surface of the plastic packaging layer which is remained is flush with the back surface of the semiconductor chip;
7) providing a heat sink in contact with the back surface of the semiconductor chip.
Optionally, in step 1), forming a first redistribution layer on the upper surface of the carrier includes the following steps:
forming a first metal wire layer on the upper surface of the carrier plate;
forming a dielectric layer on the upper surface of the structure formed in the step;
and forming other metal wire layers electrically connected with the first metal wire layer in the dielectric layer, wherein the connected metal wire layers are electrically connected through metal plugs, so that a metal laminated structure is formed.
Optionally, in the step 5), forming a second redistribution layer on the first surface of the first redistribution layer includes:
forming a first metal wire layer on the first surface of the first re-wiring layer;
forming a dielectric layer on the upper surface of the structure formed in the step;
and forming other metal wire layers electrically connected with the first metal wire layer in the dielectric layer, wherein the connected metal wire layers are electrically connected through metal plugs, so that a metal laminated structure is formed.
Optionally, in step 2, a plurality of semiconductor chips are provided, and each of the plurality of semiconductor chips is mounted on the second surface of the redistribution layer with a front side facing downward, and a space is provided between the adjacent semiconductor chips.
Optionally, the heat sink includes a heat sink, and the back surface of the semiconductor chip is in contact with the back surface of the heat sink.
Optionally, between step 2) and step 3), a step of filling a gap between the semiconductor chip and the first redistribution layer with a filler to form a filler layer is further included.
Optionally, the material of the carrier plate comprises any one of silicon, glass, metal, semiconductor, polymer and ceramic; the shape of the carrier plate comprises a round shape and a panel shape.
Optionally, in step 4), the step of removing the carrier plate includes: firstly, thinning the carrier plate by adopting a mechanical grinding process, and then removing the rest carrier plate by adopting a chemical grinding process.
Optionally, in step 1), before forming the first redistribution layer on the upper surface of the carrier, a step of forming a release layer on the upper surface of the carrier is further included; in the step 4), the carrier plate is removed by removing the release layer.
As described above, the invention can effectively reduce the package thickness by using the rewiring layer instead of the circuit substrate; through the two rewiring layers, the use of a silicon middle layer and a silicon through hole is avoided, the process flow is reduced, and the cost is reduced; the line width and the line distance of the metal connecting lines in the rewiring layer can be smaller than 2 mu m, so that the requirement of small line width is met.
Drawings
Fig. 1 is a flow chart illustrating a method for manufacturing a package structure according to the present invention.
FIG. 2 is a schematic diagram illustrating a carrier and a first redistribution layer formed on the upper surface of the carrier according to an embodiment of the invention
FIG. 3 is a schematic view of a semiconductor chip mounted in the first embodiment.
Fig. 4 is a schematic diagram illustrating formation of a molding layer according to a first embodiment.
Fig. 5 is a schematic view illustrating the carrier plate removed in the first embodiment.
Fig. 6 is a schematic diagram illustrating the formation of a second redistribution layer according to a first embodiment.
Fig. 7 is a schematic view illustrating a portion of a molding layer is removed according to a first embodiment.
Fig. 8 is a schematic view of a heat sink assembly according to a first embodiment.
Description of the element reference numerals
10 carrier plate
11 first rewiring layer
11a first surface
11b second surface
111 metal wire layer
112 metal plug
113 dielectric layer
12 Release layer
13 semiconductor chip
14 plastic packaging layer
15 packing layer
16 second rewiring layer
16a upper surface
16b lower surface
161 metal wire layer
162 metal plug
163 dielectric layer
17 ball grid array
18 radiator element
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 8. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
As shown in fig. 8, the present invention provides a package structure, which includes: a second rewiring layer 16 provided with an upper surface and a lower surface corresponding to the upper surface; a first rewiring layer 11 provided with a first surface and a second surface corresponding to the first surface, the first rewiring layer 11 being mounted on an upper surface of the second rewiring layer via the first surface, the first rewiring layer being electrically connected to the second rewiring layer; a semiconductor chip 13 flip-chip mounted face down on the second surface of the first rewiring layer 11 and electrically connected to the first rewiring layer 11; the plastic packaging layer 14 is plastically packaged on the periphery of the semiconductor chip 13, and the surface, away from the first rewiring layer, of the plastic packaging layer 14 is flush with the back surface of the semiconductor chip 13; a heat sink 18 in contact with the back surface of the semiconductor chip 13; and a ball grid array 17 provided on a lower surface of the second rewiring layer 16 and electrically connected to the second rewiring layer 16.
As an example, the package structure further includes a filler layer 15, and the filler layer 15 fills a gap between the semiconductor chip 13 and the first re-wiring layer 11.
As an example, the rewiring layer 11 includes a dielectric layer 113 and a metal stack structure located in the dielectric layer 113, the metal stack structure includes a plurality of metal line layers 111 arranged at intervals and metal plugs 112 located between adjacent metal line layers 111 to electrically connect the adjacent metal line layers 111.
As an example, the dielectric layer is made of low-k dielectric material, including SiO2And PI or PBO, and the like.
As an example, the heat sink 18 includes a heat sink, and the back surface of the semiconductor chip 13 is in contact with the heat sink 18.
As an example, the number of the semiconductor chips 13 in the package structure includes at least two, and the plurality of semiconductor chips 13 are each flip-chip mounted face down on the second surface of the first re-wiring layer 11 with a space between adjacent semiconductor chips 13.
The invention also provides a preparation method of the packaging structure, which at least comprises the following steps:
1) providing a carrier plate, wherein the carrier plate is provided with an upper surface and a lower surface corresponding to the upper surface, a first rewiring layer is formed on the upper surface of the carrier plate, the first rewiring layer is provided with a first surface and a second surface corresponding to the first surface, and the first surface of the first rewiring layer is in contact with the upper surface of the carrier plate;
2) providing a semiconductor chip, and inversely placing the semiconductor chip on the second surface of the first rewiring layer, wherein the semiconductor chip is electrically connected with the first rewiring layer;
3) forming a plastic packaging layer on the surface of the structure formed in the step 2);
4) removing the carrier plate to expose the first rewiring layer;
5) forming a second redistribution layer on the first surface of the first redistribution layer, wherein the second redistribution layer is provided with an upper surface and a lower surface corresponding to the upper surface, the second redistribution layer is electrically connected with the first redistribution layer through the upper surface, and a ball grid array is formed on the lower surface of the second redistribution layer and is electrically connected with the second redistribution layer;
6) removing part of the plastic packaging layer so that the surface of the plastic packaging layer which is remained is flush with the back surface of the semiconductor chip;
7) providing a heat sink in contact with the back surface of the semiconductor chip.
As an example, in step 1), before forming a redistribution layer on the upper surface of the carrier board, a step of forming a release layer on the upper surface of the carrier board is further included; in step 5), the carrier plate is removed by removing the release layer. In this embodiment, a method of removing a carrier by forming a release layer on the carrier and then removing the release layer is adopted.
The technical solution of the present embodiment is described in detail below with reference to the accompanying drawings.
As shown in fig. 2, step 1) is performed to provide a carrier 10, forming a first redistribution layer 11 on an upper surface of the carrier 10, where the first redistribution layer 11 has a first surface 11a and a second surface 11b corresponding to the first surface 11a, and the first surface of the first redistribution layer 11 contacts the upper surface of the carrier 10.
As an example, in step 1), a step of forming a release layer 12 on the upper surface of the carrier board 10 is further included. The release layer 12, which is used as a separation layer between the first redistribution layer 11 and the carrier 10 in the subsequent process, is preferably made of an adhesive material with a smooth surface, which has to have a certain bonding force with the carrier 10. As an example, the material of the release layer 12 is selected from an adhesive tape with both sides sticky or an adhesive glue made by a spin coating process, and the like, and the adhesive tape is preferably a UV adhesive tape, which can be easily torn off under the irradiation of UV light, so as to facilitate the removal of the carrier plate. In other embodiments, the release layer may also be made of other materials prepared by physical vapor deposition or chemical vapor deposition, such as epoxy resin, silicone rubber, polyimide, etc. During subsequent separation of the carrier, wet etching, chemical mechanical polishing, etc. may be used to remove the release layer 12.
As an example, the material of the carrier plate 10 may be selected from one of silicon, glass, metal plate, semiconductor, polymer, and ceramic. The shape of the carrier plate 10 may be wafer-like, panel-like or other desired shape. The carrier plate 10 serves to prevent cracking, warping, breaking, etc. of the thin wafer of the mold apparatus. In the present embodiment, the carrier 10 is a wafer-shaped carrier made of glass.
As an example, the step of preparing the first re-wiring layer 11 includes:
forming a first metal wire layer 111 on the upper surface of the carrier 10;
forming a dielectric layer 113 on the upper surface of the structure formed in the above step;
other metal line layers electrically connected to the first metal line layer 111 are formed in the dielectric layer 113, and the connected metal line layers are electrically connected through the metal plug 112, thereby forming a metal stack structure.
As an example, the material of the metal laminated structure includes any one of copper, aluminum, gold, nickel, and titanium, and the metal wire layer may be formed by using physical vapor deposition, chemical vapor deposition, magnetron sputtering, or electroplating, chemical plating, or the like; the dielectric layer 113 is made of a low-k dielectric material, such as an organic or inorganic insulating material, such as epoxy, silicone, PI, PBO, or silicon dioxide, and the dielectric layer 113 can be formed by spin coating, chemical vapor deposition, or plasma enhanced chemical vapor deposition.
As shown in fig. 3, step 2) is performed to provide a semiconductor chip 13, and the semiconductor chip is mounted on the second surface 11b of the first redistribution layer 11 with the front surface facing downward, so that the semiconductor chip 13 is electrically connected to the first redistribution layer 11.
As an example, the semiconductor chips 13 include one or more, and a plurality of semiconductor chips have a gap left therebetween. In the present embodiment, two semiconductor chips are mounted with their front surfaces facing down on the second surface of the first re-wiring layer 11.
As shown in fig. 4, step 3) is performed to form a molding layer 14 on the second surface of the first redistribution layer 11, and the molding layer 14 fills the gap between the semiconductor chips 13 and covers the semiconductor chips 13.
As an example, in step 3), before forming the molding layer 14, a step of filling a gap between the semiconductor chip 13 and the first rewiring layer 11 with a filler to form a first filler layer 15 is further included. The material of the filler layer comprises epoxy resin and other materials. The filler layer can protect the chip from the influence of the environment, reduce the influence of the thermal expansion incompatibility between the chip and the substrate, and greatly improve the reliability of the element.
As an example, the material of the molding layer 14 may be one of a polyimide layer, an epoxy-based resin, a liquid type thermosetting epoxy resin, and a plastic compound. The plastic package process includes compression molding, liquid sealing, spin coating and transfer molding.
As shown in fig. 5, step 4) is performed to remove the carrier board 10 and expose the first redistribution layer 11.
In the present embodiment, the carrier plate 10 is removed by removing the release layer 12 by UV light irradiation or wet etching, chemical mechanical polishing, or the like.
As shown in fig. 6, step 5) is performed to form a second redistribution layer 16 on the first surface of the first redistribution layer 11, and solder balls are implanted on the lower surface of the second redistribution layer to form a ball grid array 17.
As an example, the step of forming the second re-wiring layer includes:
forming a metal line layer 161 on the first surface 11a of the first re-wiring layer 11;
forming a dielectric layer 163 covering the upper surface and sidewalls of the metal line layer 161 on the first surface 11a of the first re-wiring layer 11;
other metal line layers electrically connected to the metal line layers 161 are formed in the dielectric layer 163, and the connected metal line layers 161 are electrically connected through metal plugs 162, thereby forming a metal stack structure.
As shown in fig. 7, step 6) is performed to remove a portion of the molding layer 14 so that the upper surface of the remaining molding layer 14 is flush with the back surface of the semiconductor chip 13.
As an example, a portion of the molding layer 14 is removed by chemical mechanical polishing.
As shown in fig. 8, step 7) is performed to provide a heat spreader 18, and the heat spreader 18 is brought into contact with the back surface of the semiconductor chip 13.
As an example, the heat sink includes a semi-surrounding type heat sink frame or heat sink. In the present embodiment, a heat sink structure is employed to mount on the back surface of the semiconductor chip 13. In other embodiments, a thermal paste is further disposed between the heat spreader and the semiconductor chip to further facilitate heat dissipation of the semiconductor chip.
Through the process steps, the packaging structure without the circuit substrate is formed, and the packaging thickness can be effectively reduced by using the rewiring layer to replace the circuit substrate; through the two rewiring layers, the use of a silicon middle layer and a silicon through hole is avoided, the process flow is reduced, and the cost is reduced; the line width and the line distance of the metal connecting lines in the rewiring layer can be smaller than 2 mu m, so that the requirement of small line width is met.
Example two
The technical solution of this embodiment is basically the same as that of the first embodiment, and is different from the first embodiment in that, in the step 4), the step of removing the carrier includes: firstly, thinning the carrier plate by adopting a mechanical grinding process, and then removing the rest carrier plate by adopting a chemical grinding process.
Specifically, firstly, grinding wheels with different particle sizes are used to thin the carrier plate 10 from the back, and after the carrier plate 10 is thinned to a certain thickness, a chemical grinding process is used to remove the rest of the carrier plate 10.
Therefore, in the embodiment, the carrier plate is removed by the grinding method, compared with the method of forming the release layer on the upper surface of the carrier plate and removing the release layer in the embodiment, the process steps are reduced, and the manufacturing cost is saved.
Other technical solutions of the present embodiment are the same as those of the first embodiment, and are not further described herein.
Through the process steps, the packaging structure without the circuit substrate is formed, the line width and the line distance of the packaging structure are smaller than 2 microns, the requirement of a small line can be met, the rewiring layer is directly and electrically connected with the circuit substrate, a silicon middle layer and a silicon through hole are avoided, the process flow is reduced, and the cost is reduced.
In summary, the present invention provides a package structure and a method for manufacturing the same, wherein the package structure includes: a second rewiring layer having an upper surface and a lower surface corresponding to the upper surface; a first rewiring layer provided with a first surface and a second surface corresponding to the first surface, the first rewiring layer being mounted on an upper surface of the second rewiring layer via the first surface, the first rewiring layer being electrically connected to the second rewiring layer; a semiconductor chip, which is upside down mounted on the second surface of the first rewiring layer with the front surface facing downwards and is electrically connected with the first rewiring layer; the plastic packaging layer is plastically packaged at the periphery of the semiconductor chip, and the surface of the plastic packaging layer, which is far away from the first rewiring layer, is flush with the back surface of the semiconductor chip; a heat sink in contact with a back surface of the semiconductor chip; and the ball grid array is arranged on the lower surface of the second rewiring layer and is electrically connected with the second rewiring layer. According to the packaging structure and the preparation method thereof, the rewiring layer is used for replacing the circuit substrate, so that the packaging thickness can be effectively reduced; through the two rewiring layers, the use of a silicon middle layer and a silicon through hole is avoided, the process flow is reduced, and the cost is reduced; the line width and the line distance of the metal connecting lines in the rewiring layer can be smaller than 2 mu m, so that the requirement of small line width is met.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (15)

1. A package structure, comprising:
a second rewiring layer having an upper surface and a lower surface corresponding to the upper surface;
a first rewiring layer provided with a first surface and a second surface corresponding to the first surface, the first rewiring layer being mounted on an upper surface of the second rewiring layer via the first surface, the first rewiring layer being electrically connected to the second rewiring layer;
a semiconductor chip, which is upside down mounted on the second surface of the first rewiring layer with the front surface facing downwards and is electrically connected with the first rewiring layer;
the plastic packaging layer is plastically packaged at the periphery of the semiconductor chip, and the surface of the plastic packaging layer, which is far away from the first rewiring layer, is flush with the back surface of the semiconductor chip;
a heat sink in contact with a back surface of the semiconductor chip;
and the ball grid array is arranged on the lower surface of the second rewiring layer and is electrically connected with the second rewiring layer.
2. The package structure of claim 1, further comprising a filler layer filling a gap between the semiconductor chip and the first re-wiring layer.
3. The package structure of claim 1, wherein the second redistribution layer and the first redistribution layer respectively comprise a dielectric layer and a metal stack structure in the dielectric layer, the metal stack structure comprises a plurality of metal wire layers arranged at intervals and metal plugs, and the metal plugs are located between adjacent metal wire layers to electrically connect the adjacent metal wire layers.
4. The package structure of claim 3, wherein the material of the dielectric layer comprises SiO2PI or PBO.
5. The package structure of claim 1, wherein the heat spreader comprises a heat sink, and wherein the back surface of the semiconductor chip is in contact with the heat sink.
6. The package structure of claim 1, wherein the number of the semiconductor chips in the package structure includes at least two, and a plurality of the semiconductor chips are flip-chip mounted face down on the second surface of the first redistribution layer with a space between adjacent semiconductor chips.
7. A method for manufacturing a package structure is characterized by comprising the following steps:
1) providing a carrier plate, wherein the carrier plate is provided with an upper surface and a lower surface corresponding to the upper surface, a first rewiring layer is formed on the upper surface of the carrier plate, the first rewiring layer is provided with a first surface and a second surface corresponding to the first surface, and the first surface of the first rewiring layer is in contact with the upper surface of the carrier plate;
2) providing a semiconductor chip, and inversely placing the semiconductor chip on the second surface of the first rewiring layer, wherein the semiconductor chip is electrically connected with the first rewiring layer;
3) forming a plastic packaging layer on the surface of the structure formed in the step 2);
4) removing the carrier plate to expose the first rewiring layer;
5) forming a second redistribution layer on the first surface of the first redistribution layer, wherein the second redistribution layer is provided with an upper surface and a lower surface corresponding to the upper surface, the second redistribution layer is electrically connected with the first redistribution layer through the upper surface, and a ball grid array is formed on the lower surface of the second redistribution layer and is electrically connected with the second redistribution layer;
6) removing part of the plastic packaging layer so that the surface of the plastic packaging layer which is remained is flush with the back surface of the semiconductor chip;
7) providing a heat sink in contact with the back surface of the semiconductor chip.
8. The method for manufacturing a package structure according to claim 7, wherein the step 1) of forming a first redistribution layer on the upper surface of the carrier comprises the steps of:
forming a first metal wire layer on the upper surface of the carrier plate;
forming a dielectric layer on the upper surface of the structure formed in the step;
and forming other metal wire layers electrically connected with the first metal wire layer in the dielectric layer, wherein the connected metal wire layers are electrically connected through metal plugs, so that a metal laminated structure is formed.
9. The method of claim 7, wherein the step 5) of forming a second redistribution layer on the first surface of the first redistribution layer comprises the steps of:
forming a first metal wire layer on the first surface of the first re-wiring layer;
forming a dielectric layer on the upper surface of the structure formed in the step;
and forming other metal wire layers electrically connected with the first metal wire layer in the dielectric layer, wherein the connected metal wire layers are electrically connected through metal plugs, so that a metal laminated structure is formed.
10. The method for manufacturing a package structure according to claim 7, wherein in step 2), a plurality of semiconductor chips are provided, and the semiconductor chips are mounted on the second surface of the redistribution layer with their faces facing downward, and a space is provided between the semiconductor chips.
11. The method for manufacturing a package structure according to claim 7, wherein the heat sink includes a heat sink, and a back surface of the semiconductor chip is in contact with a back surface of the heat sink.
12. The method for manufacturing the package structure according to claim 7, further comprising a step of filling a gap between the semiconductor chip and the first re-wiring layer with a filler to form a filler layer between the step 2) and the step 3).
13. The method for manufacturing the package structure according to claim 7, wherein the material of the carrier includes any one of silicon, glass, metal, semiconductor, polymer, and ceramic; the shape of the carrier plate comprises a round shape and a panel shape.
14. The method for manufacturing a package structure according to any one of claims 7 to 12, wherein in step 4), the step of removing the carrier includes: firstly, thinning the carrier plate by adopting a mechanical grinding process, and then removing the rest carrier plate by adopting a chemical grinding process.
15. The method for manufacturing a package structure according to any one of claims 7 to 12, wherein the step 1) further comprises a step of forming a release layer on the upper surface of the carrier before forming the first redistribution layer on the upper surface of the carrier; in the step 4), the carrier plate is removed by removing the release layer.
CN201911078754.8A 2019-11-07 2019-11-07 Packaging structure and preparation method thereof Pending CN110828430A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111739840A (en) * 2020-07-24 2020-10-02 联合微电子中心有限责任公司 Preparation method of silicon adapter plate and packaging structure of silicon adapter plate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111739840A (en) * 2020-07-24 2020-10-02 联合微电子中心有限责任公司 Preparation method of silicon adapter plate and packaging structure of silicon adapter plate
CN111739840B (en) * 2020-07-24 2023-04-11 联合微电子中心有限责任公司 Preparation method of silicon adapter plate and packaging structure of silicon adapter plate

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