CN112385036A - Molded direct bond and interconnect stack - Google Patents

Abstract

The die and/or wafer are stacked and bonded in various arrangements, including stacking, and may be covered by a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover the stack more or less to facilitate connections with devices in the stack, enhance thermal management, and so forth.

Description

Molded direct bond and interconnect stack

Priority and cross-reference to related applications

The present application claims the benefit of U.S. non-provisional application No. 16/460,068 filed on 7/2/2019 and U.S. provisional application No. 62/694,845 filed on 7/6/2018, in accordance with 35u.s.c. § 119(e) (1), which are incorporated herein by reference in their entirety.

Technical Field

The following description relates to processing of integrated circuits ("ICs"). More particularly, the following description relates to techniques for packaging dies or wafers, as well as other microelectronic components.

Background

Microelectronic elements typically comprise thin plates of semiconductor material such as silicon or gallium arsenide, commonly referred to as semiconductor wafers. The wafer may be formed to include a plurality of integrated chips or dies on a surface of the wafer and/or partially embedded within the wafer. The dies separated from the wafer are typically provided as individual pre-packaged units. In some package designs, the die is mounted to a substrate or chip carrier, which in turn is mounted on a circuit board, such as a Printed Circuit Board (PCB). For example, many dies are provided in packages suitable for surface mounting.

Packaged semiconductor dies may also be provided in a "stacked" arrangement, where one package is provided on, for example, a circuit board or other carrier, and another package is mounted on top of the first package. These arrangements may allow multiple different dies or devices to be mounted in a single footprint (footprint) on a circuit board, and may further facilitate high speed operation by providing short interconnections between packages. Typically, this interconnect distance is only slightly greater than the thickness of the die itself. To achieve interconnection within the stack of die packages, interconnect structures for mechanical and electrical connections may be provided on both sides (e.g., faces) of each die package (except for the topmost package).

Additionally, as part of various microelectronic packaging schemes, dies or wafers may be stacked in a three-dimensional arrangement. This may include stacking one or more dies, device layers, and/or wafers on a larger base die, device, wafer, substrate, etc., stacking multiple dies or wafers in a vertical or horizontal arrangement, and various combinations of the two.

The die or wafer may be bonded in a stacked arrangement using various bonding techniques, including direct dielectric bonding, non-adhesive techniques (such as

) Or hybrid bonding techniques (such as

) Both of which are available from Invensas binding Technologies Inc. (formerly Ziptronix, Inc.), Xperi. Direct dielectric bonding techniques include spontaneous covalent bonding processes that are performed when two prepared dielectric surfaces are brought together under ambient conditions without an adhesive or intermediate material, and hybrid bonding techniques incorporate direct metal-to-metal bonding of respective metal bonding pads at the bonding surfaces of respective dies or wafers, also without an intermediate material, to form a unified conductive structure (see, e.g., U.S. patent nos. 6,864,585 and 7,485,968, the entire contents of which are incorporated herein). Thermal annealing of the metal bond pads may be used to enhance the metal-to-metal bond.

The respective mating surfaces of the bonded die or wafer typically include embedded conductive interconnect structures (which may be metal) or the like. In some examples, the bonding surfaces are arranged and aligned such that conductive interconnect structures from the respective surfaces are joined during bonding. The bonded interconnect structures form continuous conductive interconnects (for signals, power, etc.) between the stacked dies or wafers.

Implementing stacked die and wafer arrangements can present a number of challenges. When bonding stacked dies or wafers using direct bonding or hybrid bonding techniques, it is often desirable that the surfaces of the dies or wafers to be bonded be extremely flat, smooth, and clean. For example, in general, a surface should have very low variation in surface topology (i.e., nanoscale variation) so that the surfaces can be closely fitted to form a durable bond.

A double-sided die or wafer may be formed and prepared for stacking and bonding, where both sides of the die or wafer are to be bonded to other substrates, wafers, or dies, such as with a multiple die-to-die or die-to-wafer application. Preparing both sides of a die or wafer includes trimming both surfaces to meet dielectric roughness specifications and metal layer (e.g., copper, etc.) recess specifications. Hybrid surfaces for bonding to another die, wafer, or other substrate may be prepared using Chemical Mechanical Polishing (CMP) processes, plasma processes, wet and dry cleaning methods, and the like.

It may be desirable to package stacked and bonded dies and wafers in various configurations for purposes of various connections, performance optimization, and enhanced thermal management.

Drawings

The detailed description is set forth with reference to the accompanying drawings. In the drawings, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears. The use of the same reference symbols in different drawings indicates similar or identical items.

For purposes of discussion, the devices and systems shown in the figures are illustrated as having a number of components. As described herein, various implementations of devices and/or systems may include fewer components and still be within the scope of the present disclosure. Alternatively, other implementations of devices and/or systems may include more components or various combinations of the described components and still be within the scope of the present disclosure.

Fig. 1 is a cross-sectional profile view of an example die-to-wafer and/or die-to-die stack and molding in accordance with one embodiment.

Fig. 2 is a cross-sectional profile view of an example die-to-wafer and/or die-to-die stack and molding in accordance with one embodiment, where the top of the stack is uncovered.

Fig. 3 is a cross-sectional profile view of an example die-to-wafer and/or die-to-die stack and molding in which the top of the stack is covered, according to one embodiment.

Fig. 4 is a cross-sectional profile view of an example die-to-wafer and/or die-to-die stack and molding, according to one embodiment, where the top of the stack is uncovered and the molding extends to the bottom of the stack.

Fig. 5 is a cross-sectional profile view of an example die-to-wafer and/or die-to-die stack and molding, where the top of the stack is covered and the molding extends to the bottom of the stack, according to one embodiment.

Fig. 6 is a cross-sectional profile view of an example die-to-wafer and/or die-to-die stack and molding, where the die sizes are unequal, with the top of the stack covered, according to one embodiment.

Fig. 7 is a cross-sectional profile view of an example die-to-wafer and/or die-to-die stack and molding, where the die sizes are unequal, where the top of the stack is covered and the molding extends to the bottom of the stack, according to one embodiment.

Fig. 8 is a cross-sectional profile view of an example die-to-wafer and/or die-to-die stack and molding in which the top die of the stack is free of interconnects on one side, according to one embodiment.

Fig. 9 is a cross-sectional profile view of an example die-to-wafer and/or die-to-die stack and molding in which the top die of the stack is free of interconnects on one side and the molding extends to the bottom of the stack, according to one embodiment.

Fig. 10 is a cross-sectional profile view of an example die-to-wafer and/or die-to-die stack and molding including some lateral placement of the dies on the same level, according to one embodiment.

Fig. 11 is a cross-sectional profile view of an example die-to-wafer and/or die-to-die stack and molding including some lateral placement of die and wafer on the same level, according to one embodiment.

Fig. 12 is a cross-sectional profile view of an example die-to-wafer and/or die-to-die stack that includes some etching of the die edges, according to one embodiment.

Fig. 13 is a cross-sectional profile view of an example die-to-wafer and/or die-to-die stack and molding including some etching of the die edges, according to one embodiment.

Fig. 14 is a cross-sectional profile view of an example die-to-wafer and/or die-to-die hybrid bonding stack including some etching of the die edges, according to another embodiment.

Fig. 15 is a cross-sectional profile view of an example die-to-wafer and/or die-to-die memory stack in accordance with one embodiment.

Fig. 16 is a cross-sectional profile view of an example die-to-wafer and/or die-to-die hybrid bonding stack including flip-chip termination, according to one embodiment.

Fig. 17-20 illustrate cross-sectional profile views of example die-to-wafer and/or die-to-die hybrid bonding stacks including various combinations on a substrate, according to various embodiments.

FIG. 21 is a flow diagram illustrating an example process for forming a stack and bond structure according to one embodiment.

Detailed Description

SUMMARY

Representative techniques and devices are disclosed, including process steps for stacking and bonding dies and/or wafers, including die-to-die, die-to-wafer, and wafer-to-wafer hybrid bonding without adhesives. In various embodiments, the die and/or wafer are stacked and bonded in various arrangements, including stacking, and may be covered by a molding to facilitate handling, packaging, and the like. In various examples, the molding may more or less cover the stack to facilitate connection with devices in the stack, enhance thermal management, and so forth.

Various implementations and arrangements are discussed with reference to electrical and electronic components and various carriers. Although reference is made to a particular component (i.e., die, wafer, Integrated Circuit (IC) chip die, substrate, etc.), this is not meant to be limiting, but is done for ease of discussion and illustration. The techniques and devices discussed with reference to wafers, dies, substrates, etc., are applicable to any type or number of electronic components, circuits (e.g., Integrated Circuits (ICs), hybrid circuits, ASICS, memory devices, processors, etc.), grouped components, passive components, MEMS (micro-electro-mechanical systems) components, packaged components, structures (e.g., wafers, panels, boards, PCBs, etc.), etc., that may be integrated and coupled to interface with each other, external circuits, systems, carriers, etc. Each of these various components, circuits, groups, packages, structures, etc. may be collectively referred to as a "microelectronic component". For simplicity, a component bonded to another component is referred to herein as a "die" unless otherwise specified.

Example embodiments

Fig. 1 is a cross-sectional profile view of an example die-to-wafer and/or die-to-die stack and molding in accordance with one embodiment. In the example shown, the stack 100 (or microelectronic assembly 100) is formed by stacking and bonding (e.g., hybrid bonding without an adhesive) a plurality of dies 102 (e.g., any number of desired dies 102). In an alternative embodiment, the stack 100 is formed by stacking and bonding (e.g., hybrid bonding without adhesive) multiple wafers that are then singulated into the die 102 shown in fig. 1. In one implementation, as shown in fig. 1, the die 102 may not be fully aligned in the stack 100. In other words, the edges of the dies 102 are not precisely aligned, and there is some error or misalignment "e" from one die 102 to another die 102 of the stack 100. In different examples, the misalignment "e" may be due to precision tolerances of pick and place tools and the like.

The die 102 (or wafer) may be formed using various techniques to include a substrate 104 and one or more insulating or dielectric layers 106. For example, the die 102 shown in fig. 1 may represent a double-sided die 102, the double-sided die 102 having insulating layers 106 on both surfaces of a base layer 104. A die 102 'may also be included, and as shown in fig. 1, the die 102' may be a single-sided or double-sided host die or wafer. In cases where direct bond connections to both sides of the die 102 are not required, a single-sided die 102 or 102' may be positioned in the stack 100 as the top die 102, the bottom die 102, or as any other die 102 in the stack 100. As used herein, unless otherwise noted, reference to "die 102" includes both single-sided and double-sided dies and wafers.

The substrate 104 may comprise silicon, germanium, glass, quartz, a dielectric surface, a direct or indirect gap semiconductor material or layer, or another suitable material. The insulating layer 106 is deposited or formed over the substrate 104 and may be composed of a layer of inorganic dielectric material, such as an oxide, nitride, oxynitride, oxycarbide, carbide, carbonitride, diamond-like material, glass, ceramic, glass-ceramic, or the like.

The bonding surface 108 of the die 102 may include conductive features 110, such as TSVs, traces, pads, and interconnect structures, for example, the conductive features 110 being embedded in the insulating layer 106 and arranged such that the conductive features 110 from the respective bonding surfaces 108 of opposing devices may be matched and joined as desired during the bonding process. The joined conductive features 110 may form a continuous conductive interconnection (for signals, power, ground, etc.) between stacked devices.

A damascene process (or the like) may be used to form the embedded conductive features 110 in the insulating layer 106. The conductive features 110 may be comprised of a metal (e.g., copper, etc.) or other conductive material or combination of materials, and include structures, traces, pads, patterns, and the like. In some examples, prior to depositing the material of the conductive feature 110, a barrier layer may be deposited in the chamber for the conductive feature 110 such that the barrier layer is disposed between the conductive feature 110 and the insulating layer 106. The barrier layer may be composed of tantalum, titanium, tungsten layers, or combinations thereof (e.g., or another conductive material) with their various corresponding compounds or alloys to prevent or reduce diffusion of the material of the conductive features 110 into the insulating layer 106. After forming the conductive features 110, the exposed surface of the device wafer 102 including the insulating layer 106 and the conductive features 110 may be planarized (e.g., via CMP) to form a planar bonding surface 108.

Forming the bonding surface 108 includes modifying the surface 108 to meet dielectric roughness specifications and metal layer (e.g., copper, etc.) dishing specifications, if specified, to prepare the surface 108 for hybrid bonding. In other words, the bonding surface 108 is formed as flat and smooth as possible, with very little surface topology variation (on the order of nanometers). Low surface roughness can be achieved using various conventional processes such as Chemical Mechanical Polishing (CMP), dry etching, or wet etching. This process provides a flat smooth surface 108 that produces a reliable bond.

Embedded conductive traces 112 extending partially into the dielectric substrate 106 under the prepared surface 108 may be used to electrically couple the conductive features 110 to the desired components of the overall die 102. For example, the conductive features 110 may be coupled to conductive (e.g., copper) Through Silicon Vias (TSVs) 114 or the like that extend through some or all of the die 102 to make electrical connections through the thickness of the die 102. For example, in some cases, the TSVs 114 may extend about 50 microns, depending on the thickness of the die 102. The figures illustrate examples of a die 102 having various arrangements of conductive features 110, traces 112, and TSVs 114, which are not intended to be limiting. In various embodiments, some of the conductive features 110, traces 112, and TSVs 114 may not be present in the die 102 (or wafer), while in other embodiments, additional conductive features 110, traces 112, and TSVs 114 may be present, or other circuit components, etc.

For example, the die 102 may be hybrid bonded to other dies 102 having metal pads 110, traces 112, and/or TSVs 114 without an adhesive to achieve the desired electrical connections through the die 102 while forming the stack 100. Hybrid bonding includes direct dielectric-to-dielectric bonding of the respective insulating layers 106 of each die 102 without adhesives or other intermediate materials (e.g.,

) And the respective conductive features 110 of each die 102 without an intervening material (e.g.,

). Dielectric-to-dielectric bonding occurs naturally when the respective bonding surfaces 108 are brought together at ambient temperature. Metal-to-metal bonding (which may include of the metal of the conductive feature 10)Interstitial diffusion) can occur with or without pressure by means of heat.

As shown in fig. 1, electrical connections may be established from the top surface of the top die 102 of the stack 100 (e.g., through the conductive features 110), through the die 102 (any number of dies 102) of the stack 100 (e.g., through the conductive features 110, the traces 112, and the TSVs 114), and to the bottom surface of the bottom die 102 of the stack 100 (e.g., through the TSVs 114). In the example of fig. 1, the conductive feature 110 provides a connection to the top surface of the stack 100, and the TSV 114, having at least one electrically coupled pad 116, provides a connection to the bottom surface of the bottom die 102 of the stack 100 (in some cases, a layer of titanium (not shown) or the like may couple the TSV 114 to the pad 116). In alternative embodiments, one or both of the top and bottom surfaces of the stack 100 may have no connections, or components other than those shown may provide connections to the top or bottom surface of the stack 100. For example, in some embodiments, the stack 100 may not include the conductive features 110 at the top surface of the stack 100 or the TSVs 114 in the top die 102 or the TSVs 114 and pads 116 in the bottom die 102.

In some implementations, one or more TSVs 114 provide thermal connections between the dies 102. For example, TSVs may help dissipate or transfer heat from some dies 102 to other dies 102 and/or the external environment. In this implementation, the TSVs 114 are constructed of a thermally conductive material and may include a thermally conductive barrier layer (not shown). In some examples, the TSVs 114 may be sized for optimal heat dissipation based on the function (e.g., heat generation) of the associated die 102.

Fig. 2 is a cross-sectional profile view of a microelectronic assembly 200 including a plurality of stacks 100 of dies 102. In some embodiments, each stack 100 includes the same number of dies 102. In other embodiments, some stacks 100 may include a different number of dies 102 than other stacks 100 of the assembly 200. In one implementation, as shown in fig. 2, the die 102 is not perfectly aligned in the stack 100. In other words, the edges of the die 102 are not precisely aligned within the stack 100, and there is some error or misalignment from the die 102 to the die 102. In some embodiments, the stack 100 is singulated from a plurality of wafers that have been stacked and bonded as described above.

In one implementation, the bottom set of dies 102' includes a main wafer 202 for the stack 100. In this implementation, the die 102 may be stacked onto the host wafer 202, and the host wafer 202 is then singulated at the boundaries of the stack 100 as needed. In other implementations, the main wafer 202 may be singulated at different stages of the process (if any).

As shown in fig. 2, one or more stacks 100 of components 200 may be covered in a molding 204 that includes a sealant or the like. In various embodiments, the molding 204 may comprise a high strength, high thermal stress (high heat resistance) encapsulant material, which may also have high heat dissipation characteristics. In addition, it may be desirable for the molded article 204 to have a Coefficient of Thermal Expansion (CTE) of less than 20 to aid in warpage control. For example,

such sealants or "epoxy molding compounds," known as "CEL" are provided. Other similar products are also commercially available. In one embodiment, the assembly 200 is covered by a molding 204, and then the assembly 200 is sliced into a plurality of stacks 100. The individual stacks 100 may be covered with additional encapsulant 204 as desired. In other embodiments, molding the stack 100 after forming the stack 100 includes stacking and bonding individual dies 102 into the stack 100 or singulating a wafer to form the dies 102 and the stack 100. For example, the molding 204 may be deposited before or after singulation of the die 102. In both cases, the molding 204 may cover the entire stack 100 of dies 102 or selected dies 102. For example, in one embodiment, the host wafer 202 (and die 102') may not be covered by the molding 204. This may be due to the manufacturing process or design.

For all implementations disclosed herein, the molding 204 may include a single layer of encapsulant overlying and/or around some or all of the dies 102 of the stack 100, or the molding 204 may include multiple layers (e.g., a laminate) of the same or different materials of encapsulant. Further, in one implementation, the molding 204 includes particles within the encapsulant, and the molding 204 has a variation in density of the particles: from a low particle or no particle state at the top or bottom of the stack 100 to a higher density particle state at the other of the top or bottom of the stack 100. In one example, when present, the particles may be present in the multilayer encapsulant at different densities. In various embodiments, the molding 204 comprises an inorganic housing or the like.

In some examples, adding molding 204 to the stack 100 of the die 102 and/or the assembly 200 may provide a final package for the stack 100 or the assembly 200. The stacking solution enables easy handling during processing and assembly and deployment in applications. The molding 204 provides protection for the die 102 and the stack 100, as well as the assembly 200 and any discrete components that may be packaged with the die 102.

In one implementation, as shown in fig. 2, the top surface of one or more stacks 100 (or all stacks 100) may be free of molding 204. The bare top surface of the top die 102 may be used to further interconnect the top die 102 of the stack 100 to other circuits, devices (e.g., optical, Radio Frequency (RF), analog, digital, logic, memory, or other devices), etc. (e.g., when the conductive features 110 are present at the top surface of the die 102), including, for example, additional die 102 or components 200. Alternatively or additionally, the top surface of the top die 102 may not be covered to enhance heat dissipation. For example, without the encapsulant 204 at the top surface of the top die 102 of the assembly 200, heat may be more easily and efficiently dissipated from the die 102. In this case, the conductive features 110 (and traces 112) may not be present at the top surface of the top die 102. For example, if the TSV 114 is used to help dissipate heat through the top surface, the TSV 114 may be present.

In one implementation, the assembly 200 includes one or more electrical contacts or terminals 206 at a surface (e.g., a bottom surface) of the assembly 200. The terminals 206 may be used to electrically couple the assembly to another circuit, device, Printed Circuit Board (PCB), or the like. As shown in fig. 2, the terminals 206 may be electrically coupled to the TSVs 114 (or other interconnects) of the dies 102 (such as the bottommost die 102) of the stack 100 of the assembly 200 through the pads 116. For example, the assembly 200 may include electrical connections from one or more top dies 102 of the stack 100 (e.g., in some cases, a top surface of the top die 102) through the dies 102 of the stack 100 to the terminals 206.

In some embodiments, additional layers, circuit components, vias, and the like may also be incorporated into the stack 100 and/or the assembly 200 as desired. In alternative implementations, the TSVs 114 may be optional in certain dies 102 and/or certain stacks 100.

In one implementation, as shown in fig. 3, the top surface of one or more stacks 100 (or all stacks 100) may include a molding 204. In this implementation, the molding 204 at the top surface of the stack 100 and the assembly 200 protects the stack 100 and the assembly 200 during handling, assembly, deployment, and the like. In one embodiment, each stack 100 is individually covered by a molding 204, including the top and sides of the stack 100. In one embodiment, the host wafer 202 (and die 102') may not be covered by the molding 204. As shown in the example of fig. 3, in some embodiments, the top die 102 of the assembly 200 may not include the conductive features 110 (or traces 112 and/or TSVs 114) when no electrical connection is intended at the top surfaces of the die 102 and the assembly 200. These components may be optional, such as when they are used for other purposes (e.g., when circuit components are disposed on or within upper insulating layer 106, etc.).

Also, as shown in the example of fig. 3, the die 102 may have various component configurations and arrangements in some applications. For example, as shown in fig. 3, the die 102 "may include TSVs 114, the TSVs 114 being directly coupled to the conductive pads 110 on the adjacent die 102 to provide connections to the adjacent bonded die 102. For example, the end face of the TSV 114 may be exposed at the bonding surface 108 of the die 102 "to form a contact surface for bonding to the conductive pad 110 on an adjacent die 102. In other embodiments, as shown in fig. 3, the die 102 "may include a conductive pad 110 at the bonding surface, wherein the TSV 114 is directly coupled to the conductive pad 110. These conductive pads 110 may be bonded to conductive pads 110 (or other conductive structures) on adjacent dies 102.

In one implementation, as shown in fig. 4 and 5, the entire stack 100 may be covered with a molding 204, including the host wafer 202 and the die 102'. In this implementation, the host wafer 202 may be singulated into the dies 102' prior to the packaging step so that they are covered by the molding 204. A plurality of die 102 (in groups or one at a time) may be stacked onto a primary die 102' to form a stack 100, and then the stack 100 may be covered with a molding 204. Alternatively, the molding 204 may be applied to the assembly 200 after all of the dies 102 are stacked and bonded to the stack 100. In any case, the molding 204 may be present on a side of the stack 100. Furthermore, in an alternative embodiment, the stacks 100 of components 200 may be separated from each other after the molding step.

As shown, fig. 4 illustrates an example assembly 200 in which the assembly 200 and the top surface (i.e., the back) of the stack 100 are devoid of the molding 204. In one embodiment, the molding 204 may be deposited over the assembly 200 and then removed from the top surface of the stack 100. In various examples, the molding 204 may be removed from the top surface of the stack 100 to provide interconnection to the top die 102, improvement in heat dissipation, and the like. Fig. 5 shows a case in which the top surface (i.e., the back surface) is covered by the molding 204.

As shown in fig. 6 and 7, the size (e.g., size, area, footprint, thickness, etc.) of the dies 102 of the stack 100 may be non-uniform. For example, dies 102 having different footprints or thicknesses may be stacked and bonded to form the stack 100. Without the molding 204, the stack 100 of non-conforming die 102 exhibits uneven side edges and/or stacks 100 having different heights. Covering the stack 100 with the molding 204 may provide the same packaging (in terms of side edges/surfaces and height) as the stack 100 and/or the assembly 200.

The example shown in fig. 6 shows an embodiment in which the die 102 is covered by the molding 204 but the main wafer (main die 102') is not covered by the molding 204. In some embodiments, the thickness of the molding layer 204 on the side edge of the top die 102 is greater than the thickness of the molding layer 204 on the side edge of the second die 102 disposed below. The example of fig. 7 shows an embodiment in which both the die 102 and the main die 102' are covered by the molding 204, as described above.

As shown in fig. 8 and 9, in some implementations, the stack 100 may include a die 102, the die 102 having interconnects on one side rather than no interconnects on the other side. For example, as shown, the top die 102 may not have interconnects to the top surface of the die 102. In this case, no interconnects may be required on the top surface (e.g., backside) of the stack 100 or the component 200. In alternative embodiments, other dies 102 may include interconnects on only one side. In some embodiments, the TSVs 114 are also optional for the top die 102, however, the TSVs 114 may be used for heat dissipation.

In some examples, as shown in fig. 8 and 9, a heat sink 802 or other component 902 (e.g., a sensor, an optical component, etc.) may be included in the stack 100. For example, a heat spreader 802 may be located at the top of the stack 100 to assist in dissipating heat from one or more dies 102 of the stack 100 to the environment. In some cases, the thermally conductive TSVs 114 may help transfer excess heat from some dies 102 to other dies 102 and the heat spreader 802. In alternative embodiments, the heat sink 802 or other component 902 may be located somewhere within the stack 100 or at the bottom of the stack 100 as required by its application and performance.

As shown in fig. 8 and 9, the top of the stack 100 (e.g., the top surface or "back" of the die 102) may not have the molding 204 when the heat spreader 802 or other component 902 is on top of the stack 100. In some cases, some stacks 100 of assemblies 200 may include a molding 204 around the stack 100 and at a top surface of the stack 100, while other stacks 100 (e.g., stacks 100 including a heat sink 802 or other component 902) may have no molding 204 at the top surface and molding 204 at a side of the stack 100.

As shown in fig. 10 and 11, in some embodiments, conforming and/or non-conforming die 102 may be stacked and bonded to form a stack 100 in which multiple die 102 are laterally placed on the same level within a package 200 package. For example, as shown in fig. 10, the master wafer 202 may not be singulated at each stack 100. Thus, more than one stack 100 may be bonded to a single master die 102'. For example, in the example of fig. 10, the second and third stacks 100 are bonded to a single master die 102', and the fourth and fifth stacks 100 are bonded to another master die 102'.

As shown in fig. 10, the stack 100 groups bonded to the primary core 102' may be covered together in a molding 204. For example, in this example, the second and third stacks 100 may be covered (e.g., co-packaged) together in the molding 204, while the fourth and fifth stacks 100 may be covered (e.g., co-packaged) together in the molding 204. Alternatively or in combination, the molding 204 of some of the groups of stacks 100 bonded to a common main die 102' may be separated, with the separated molding 204 individually surrounding each stack 100. As shown in the example, the main die 102' (or wafer) may be free of molding. Alternatively, the primary die 102' (or wafer) may be covered with the molding 204.

As shown in fig. 11, in some embodiments, additional dies 102 may be stacked in a lateral arrangement on the same level of the assembly 200 to form one or more common stacks or partial common stacks 1100. For example, fig. 11 shows an example of a partial common stack 1100. In this example, the first row of die 102 bonded to the primary die 102' may not be singulated at each stack 100. Thus, more than one stack 100 may be bonded to a single master die 102' and the same "first row" of dies 102.

For example, in the example of fig. 11, the second and third stacks 100 include the same first row of dies 102 bonded to the same main die 102'. Subsequent rows of dies 102 of the second and third stacks 100 are bonded to the same first row of dies 102. Thus, the second and third stacks 100 share a common main die 102' and a common first row die 102. When some of the dies 102 are common to multiple stacks 100, this results in a partially common stack 1100. In other embodiments, additional rows of dies 102 may be common to the second and third stacks 100. For example, if the dies 102 in all rows of the plurality of stacks 100 are common to the plurality of stacks 100, this will result in a common stack 1100.

As shown in fig. 11, the fourth and fifth stacks 100 also include the same first row die 102 bonded to the same master die 102'. Subsequent rows of dies 102 of the fourth and fifth stacks 100 are bonded to the same first row of dies 102. Thus, the fourth and fifth stacks 100 share a common main die 102' and a common first row die 102, resulting in a partially common stack 1100.

As shown in fig. 10 and 11, the first stack 100 is covered by the molding 204 (except for the main die 102'), and each partial common stack 1100 is also covered by the molding 204 (except for the main die 102'). However, as shown in fig. 10 and 11, one or more partial common stacks 1100 may include a molding 204 at a top surface of the die 102 of the partial common stack 1100, and one or more partial common stacks 1100 may be devoid of the molding 204 at the top surface of the die 102 of the partial common stack 1100. As described above, removing the molding 204 at the top surface of the top die 102 (or not depositing the molding 204) may allow for interconnection with the top die 102, may improve heat dissipation from the top die 102, and so on.

Additional embodiments

Fig. 12 and 13 illustrate an example embodiment of an assembly 200 in which one or more stacks 100 of bonded dies 102 are bonded to a host wafer 202. In some examples, the host wafer 202 may be singulated into host die 102' (not shown). In the various embodiments shown, the die 102 may be a double-sided die with conductive features 110 embedded within the insulating layer 106 on either side of the base layer 104. In some embodiments, some details may be assumed to be present, such as traces 112 and TSVs 114, but are not shown for clarity of the drawing.

In one implementation, as shown in fig. 12 and 13, one or more insulating layers 106 may be etched at the perimeter edges of the die 102 (see 1202), removing some of the insulating layers 106 at the perimeter. The perimeter etch 1202 may be intentional based on the specifications of the device, packaging, processing, etc. In this implementation, the etch 1202 may be present on one or more sides or edges of the die 102. In some cases, etching 1202 includes peripherally removing portions of insulating layer 106 and exposing underlying base layer 104. In other cases, etch 1202 does not expose base layer 104, or etch 1202 also removes some of base layer 104.

Fig. 14 is another illustration of a die 102 having an etched peripheral edge (recess 1202) according to an embodiment. In an example embodiment, the illustration of fig. 14 more closely shows the relative proportions of the recess 1202 with respect to the base layer 104 and the insulating layer 106. In other embodiments, other ratios may be present.

In some cases, as described above, the molded article 204 compound may be filled with particles. For example, particles may be added to the molding 204 to change the Coefficient of Thermal Expansion (CTE) of the molding 204. This may help reduce package warpage, for example, by balancing the CTE across the package (e.g., assembly 200). However, in some cases, the particles in the molding 204 may be too large to be accommodated within the smaller recesses 1202 formed by the perimeter etching. Any voids left after the molding 204 is applied to the stack 100 may result in "popcorn" failure in the packaged assembly (e.g., assembly 200).

In various implementations, instead of including particles in the molding 204 (and not accepting the benefits of doing so), a multi-layer molding 204 may be used to mitigate possible failures, as shown in fig. 13. For example, a first low viscosity compound 1302 may be applied around the stack 100 to form a compound layer 1302 around the stack 100 and to penetrate the etched recess 1202. Then, layer 1302 may be followed by a layer of molding 204.

In this implementation, the first layer compound 1302 may not include fillers or particles. For example, with low viscosity, the primary purpose of the compound 1302 may be to fill the etched recesses 1302 in the die 102. However, the compound 1302 may also form a layer over the vertical walls of the die 102 of the stack 100. After applying the first layer of compound 1302, the stack 100 and/or assembly 200 may be covered by the molding 204. In alternative embodiments, additional layers may also be used to cover the stack 100 and/or the assembly 200.

In other implementations, the first layer (low viscosity) compound 1302 (or resin) may include sub-micron particles or even nanoparticles small enough to be incorporated within the recess 1202. The submicron or nano-particles may comprise silica, silicon, silica/silicon compounds, and the like. The size (e.g., diameter) of the nanoparticles may average 20nm in some cases, while smaller or larger in other cases.

In one embodiment, a first layer of compound 1302 (with sub-micron or nano-sized filler particles) forms a layer over the vertical walls of the die 102 and the recess 1202. In some embodiments, it is preferred that the submicron or nanoparticle content of the first layer of compounds 1302 is greater than 5%. The molded layer 204 typically includes reinforcing particles with a particle content typically greater than 50%, and it may be preferred that the particle content of the molded layer 204 is higher than the particle content of the first layer compound 1302 within the recess 1202. Similarly, in some applications, it may be preferable that the nominal size of the particles in the molded layer 204 be greater than the nominal size of the particles in the first layer of the compound 1302.

Referring to fig. 15 and 16, in common practice, memory dies are coupled to other memory dies using Ball Grid Array (BGA) and other similar techniques. In these cases, the memory die-to-memory die pitch is typically about 45 microns. Using similar techniques, the logic die to interposer pitch is about 90-100 microns. However, in some embodiments, it is possible and practical to separately assemble a stack of memory dies (such as stack 100) at a finer pitch and then stack them on a logic die. Note that in some cases, the logic die may not be larger than the memory die.

Fig. 15 and 16 show an example of a "high bandwidth memory" assembly 200, the assembly 200 including a stack 100 of memory dies 102 (e.g., Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), flash memory, etc.) coupled to a logic die 1502. As described above, in various implementations, the die 102 is hybrid bonded

To form a stack 100. As shown in fig. 15, the stack 100 (or the bottom die 102) may be hybrid bonded to the logic die 1502. The logic die 1502 may include a logic circuit for coupling a plurality of logic circuits to a plurality of logic circuitsThe assembly 200 is coupled to terminals 206 of a circuit, PCB, device, etc., as described above. Using direct or hybrid bonding techniques, the distance between the die 102 and the logic die 1502 (which is the die thickness plus the copper pillar and solder ball height due to the die thickness versus current technology) can be greatly reduced. In one embodiment, the circuit elements (such as the conductive features 110, etc.) at one bonding surface of one or more of the bonded dies 102 are less than 20 microns, and in other applications less than 5 microns or even less than 1 micron.

As shown in fig. 16, the stack 100 may alternatively be coupled to the logic die 1502 using flip chip technology or the like. For example, flip-chip terminals 1602 may be coupled to the bottom side of the bottom die 102, which are joined with terminals 1602 at the top surface of the logic die 1502. Thus, a combination of hybrid bonding and flip chip techniques may be used with the assembly 200. In alternative embodiments, other coupling techniques may also be used to couple the hybrid bond stack 100 to the logic die 1502, interposer, etc., if desired.

Also shown in fig. 16 is molding 1604, the molding 1604 covering the flip-chip terminals 1602 and filling the gap between the stack 100 and the logic die 1502. In some embodiments, the assembly 200 may also be covered by a molding 204, depending on processing, packaging, etc.

Fig. 17-20 illustrate additional implementations using the stack 100 and/or the assembly 200 in various applications. For example, in fig. 17, an assembly 1700 is shown, the assembly 1700 including a variety of dies 102, including a stack 100 of dies 102 hybrid bonded to an interposer 1702. In one embodiment, insert 1702 is constructed of a semiconductor, such as silicon, for example. The drawings are simplified for clarity.

In various embodiments, as shown in fig. 17, some of the dies 102 may be molded while other dies 102 may not be molded. A heat sink or other cooling device 1704 (e.g., a fan, etc.) is coupled to the unmolded die 102 to cool the die 102 (which may include high power components, such as a processor, etc.). Insert 1702 includes hybrid bond pad 110 and at least one wire bond pad 1706.

As shown in fig. 18, wire-bonded pads 1706 can be used to couple remote components (e.g., to (or through) laminate 1802 or components integral with laminate 1802) to pads 1706 via wires 1804. In the illustrated embodiment, the laminate 1802 is hybrid bonded to the insert 1702. Alternatively, laminate 1802 may be coupled to insert 1702 by another bonding technique.

For example, as shown in FIG. 19, laminate 1802 can be coupled to insert 1702 using BGA technology, another surface mount technology, or the like. In one implementation, as shown in fig. 19, the laminate 1802 can include one or more wire bond pads 1902, the wire bond pads 1902 can be used with the wires 1804 to couple to the wire bond pads 1706, or the like.

In one embodiment, as shown in FIG. 19, the assembly 200 or stack 100 may be packaged with another part 1904, which other part 1904 may be hybrid-bonded to the insert 1702. The component 1904 and assembly 200 or stack 100 may be covered in a molding 1906 that includes an encapsulant (or other encapsulation) as desired. Package or stack 100 and feature 1904 may be hybrid bonded to insert 1702. Cooling device 1704 may be coupled to component 1904 and/or stack 100 as shown in fig. 19. Additionally, a filler 1604 may be used to cover the terminals 206 and fill the gap between the insert 1702 and the laminate 1802. Alternatively, insert 1702 may be packaged with other components or separately.

As shown in fig. 20, the stack 100 may be covered by the molding 204, while other dies 102 and/or components may not be covered. A heat sink or other cooling device 1704 (e.g., a fan, etc.) is coupled to the unmolded die 102 to cool the die 102 (which may include high power components, such as a processor, etc.). Additional cooling devices may also be coupled to the stack 100, and the stack 100 may be devoid of the molding 204 at the top surface of the stack 100. Insert 1702 includes hybrid bond pad 110 and at least one wire bond pad 1706. As shown, insert 1702 may be coupled to laminate 1802 via a BGA arrangement or other coupling technique.

Example procedure

Fig. 21 is a flow diagram illustrating an example process 2100 for forming a stacked and bonded microelectronic assembly, such as microelectronic assembly 200, including a stack of dies (e.g., stack 100 of dies 102). In some embodiments, the stack of dies may be covered by a molding (e.g., molding 204) for handling, processing, applying, and the like. Process 2100 refers to fig. 1 through 20.

The order in which the processes are described is not intended to be construed as a limitation, and any number of the described process blocks in a process can be combined in any order to implement the process, or an alternate process. In addition, various blocks may be deleted from the processes without departing from the spirit and scope of the subject matter described herein. Further, the processes may be implemented in any suitable hardware, software, firmware, or combination thereof, without departing from the scope of the subject matter described herein. In alternative implementations, other techniques may be included in the process in various combinations and still be within the scope of the present disclosure.

At block 2102, the process includes forming a microelectronic stack (e.g., the stack 100 of dies 102). In an alternative embodiment, the process includes forming a plurality of microelectronic stacks. In one implementation, forming a microelectronic stack includes the following:

at block 2104, the process includes providing a first substrate (e.g., the first die 102) having a front side and a back side. The back side has a bonding surface including a non-conductive bonding layer and an exposed conductive first circuit element. The first substrate has a first conductive via electrically coupled to the first circuit element of the first substrate and extending at least partially through the first substrate.

At block 2106, the process includes providing a second substrate having a front side and a back side. The front side includes a non-conductive bonding layer and an exposed conductive first circuit element.

At block 2108, the process includes coupling a front side of the second substrate to a back side of the first substrate by contacting the non-conductive bonding layer of the first substrate and the second substrate. In one embodiment, the side edges of the first substrate are misaligned relative to the side edges of the second substrate. Coupling includes contacting (e.g., hybrid bonding) the first circuit element of the first substrate with the first circuit element of the second substrate.

At block 2110, the process includes covering side edges of the first and second substrates with a molding (e.g., molding 204). In one implementation, the process includes covering a back side of the second substrate with a molding. In various embodiments, the molded article comprises more than one layer or more than one material or compound. In some embodiments, at least one of the layers of the molded article includes particles to help balance the CTE of the assembly to avoid warping of the assembly.

In one embodiment, the back side of the second substrate includes a second non-conductive bonding layer and an exposed conductive second circuit element. In this embodiment, the second substrate has a second conductive via electrically coupling the first circuit element and the second circuit element of the second substrate.

In one implementation, the process includes providing a third substrate having a front side and a back side, the front side including a non-conductive bonding layer and an exposed conductive first circuit element. The process includes coupling the front side of the third substrate to the back side of the second substrate by contacting the non-conductive bonding layer of the third substrate to the non-conductive bonding layer of the second substrate. In one embodiment, the side edges of the third substrate are misaligned relative to the side edges of the second substrate and/or the first substrate. Coupling includes contacting (e.g., hybrid bonding) the first circuit element of the third substrate with the second circuit element of the second substrate.

In this implementation, the process includes forming a recess at the bonding layer of the first and/or second substrate at a periphery of the first and/or second substrate before covering the side edges of the first and second substrate with the molding, and filling at least the recess with a low viscosity compound.

In another implementation, the process includes covering a side edge of the third substrate with a molding. In another implementation, the process includes covering a back side of the third substrate with a molding.

In one implementation, the process includes hybrid bonding a microelectronic stack to a semiconductor interposer having at least one wire bond contact pad. In another implementation, the process includes coupling an interposer to a laminate having a second wirebond contact pad, and wirebonding at least one wirebond contact pad of the interposer to the second wirebond contact pad of the laminate with a wire. For example, the insert may be hybrid bonded to the laminate.

In other implementations, portions of the microelectronic assembly are covered by one or more molding layers, while other portions are uncovered.

Although various implementations and examples are discussed herein, other implementations and examples are possible by combining features and elements of the various implementations and examples. In various embodiments, some process steps may be modified or eliminated as compared to those described herein.

The techniques, components, and apparatus described herein are not limited to the illustrations of fig. 1-21, and may be applied to other designs, types, arrangements, and configurations, including other electrical components, without departing from the scope of the present disclosure. In some cases, the techniques described herein may be implemented using additional or alternative components, techniques, sequences, or processes. Further, these components and/or techniques may be arranged and/or combined in various combinations while producing similar or nearly identical results.

Conclusion

Although implementations of the disclosure have been described in language specific to structural features and/or methodological acts, it is to be understood that implementations are not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as representative forms of implementing the example devices and techniques.

Each claim of this document constitutes a separate embodiment, and embodiments combining different claims and/or different embodiments are within the scope of the present disclosure and will be apparent to those of ordinary skill in the art upon review of the present disclosure.

Claims (38)

1. A microelectronic assembly, comprising:

a first substrate having a first bonding surface and a first microelectronic circuit element embedded therein, a portion of the first circuit element of the first substrate being exposed at the first bonding surface of the first substrate;

a second substrate having a first bonding surface and a first microelectronic circuit element embedded therein, a portion of the first circuit element of the second substrate being exposed at the first bonding surface of the second substrate, the first bonding surface of the second substrate being hybrid bonded to the first bonding surface of the first substrate without an adhesive such that the first circuit element of the second substrate is electrically coupled to the first circuit element of the first substrate, wherein side edges of the first substrate are misaligned relative to side edges of the second substrate; and

a molding covering at least the side edge of the second substrate.

2. The microelectronic assembly as claimed in claim 1, further comprising a first conductive via electrically coupled to the first circuit element of the first substrate and extending at least partially through the first substrate.

3. The microelectronic assembly as claimed in claim 2, wherein the first substrate includes a second surface opposite the first bonding surface, and wherein the first conductive via extends to the second surface of the first substrate and provides an electrical connection from the first bonding surface of the first substrate to the second surface of the first substrate.

4. The microelectronic assembly as claimed in claim 3, further comprising a terminal connection coupled to the second surface of the first substrate and electrically coupled to the first conductive via.

5. The microelectronic assembly as claimed in claim 2, wherein the second substrate includes a second bonding surface opposite the first bonding surface and a second microelectronic circuit element embedded in the second substrate, a portion of the second circuit element of the second substrate being exposed at the second bonding surface of the second substrate.

6. The microelectronic assembly as claimed in claim 5, further comprising a second conductive via electrically coupled to the first and second circuit elements of the second substrate and extending at least partially through the second substrate, the second conductive via providing an electrical connection from the first bonding surface of the second substrate to the second bonding surface of the second substrate.

7. The microelectronic assembly as claimed in claim 6, wherein the second conductive via provides an electrical connection from a second surface of the first substrate opposite the first bonding surface of the first substrate to the second bonding surface of the second substrate.

8. The microelectronic assembly as claimed in claim 6, further comprising a third substrate having a first bonding surface and a first microelectronic circuit element embedded therein, a portion of the first circuit element of the third substrate being exposed at the first bonding surface of the third substrate, the first bonding surface of the third substrate being bonded to the second bonding surface of the second substrate such that the first circuit element of the third substrate is electrically coupled to the second circuit element of the second substrate.

9. The microelectronic assembly of claim 8, wherein a side edge of the third substrate is misaligned relative to the side edge of the second substrate or the first substrate.

10. The microelectronic assembly of claim 8, wherein the molding covers the side edges of the first, second, and third substrates.

11. The microelectronic assembly of claim 8, wherein the molding covers the side edges of the second and third substrates, but does not cover the side edge of the first substrate.

12. The microelectronic assembly of claim 8, wherein the molding covers a second surface of the third substrate opposite the first bonding surface of the third substrate.

13. The microelectronic assembly of claim 1, wherein the molding covers a second surface of the second substrate opposite the first bonding surface of the first substrate.

14. A microelectronic assembly comprising a plurality of microelectronic assemblies as claimed in claim 10.

15. The microelectronic assembly of claim 14, wherein footprints of the first, second, and third substrates are non-uniform, and wherein an outer edge of the mold extending from the first substrate to the third substrate is planar.

16. A microelectronic assembly, comprising:

a plurality of stacks of molded microelectronic elements, each stack comprising:

a first substrate having a first bonding surface and a first microelectronic circuit element embedded therein, a portion of the first circuit element of the first substrate being exposed at the first bonding surface of the first substrate, and a first conductive via electrically coupled to the first circuit element of the first substrate and extending at least partially through the first substrate;

a second substrate having a first bonding surface and a first microelectronic circuit element embedded therein, a portion of the first circuit element of the second substrate being exposed at the first bonding surface of the second substrate, and a second conductive via electrically coupled to the first circuit element of the second substrate and extending at least partially through the second substrate, the first bonding surface of the second substrate being hybrid bonded to the first bonding surface of the first substrate without an adhesive such that the first circuit element of the second substrate is electrically coupled to the first circuit element of the first substrate, wherein a side edge of the first substrate is misaligned relative to a side edge of the second substrate; and

a molding covering at least the side edge of the second substrate.

17. The microelectronic assembly of claim 16, wherein the first substrate includes a second surface opposite the first bonding surface, and wherein the first conductive via extends to the second surface of the first substrate and provides an electrical connection from the first bonding surface of the first substrate to the second surface of the first substrate.

18. The microelectronic assembly as claimed in claim 17, wherein the second substrate includes a second bonding surface opposite the first bonding surface and a second microelectronic circuit element embedded in the second substrate, portions of the second circuit element of the second substrate being exposed at the bonding surface of the second substrate, and wherein the second conductive via is electrically coupled to the second circuit element of the second substrate.

19. The microelectronic assembly of claim 18, wherein at least one of the first and second bonding surfaces of the second substrate includes an intentional recess at a peripheral edge of the second substrate.

20. The microelectronic assembly as claimed in claim 19, wherein the molding includes:

a first low viscosity compound free of particles, the first low viscosity compound penetrating the recess at the peripheral edge of the second substrate, and

a second compound having particles, the second compound overlaying the first low viscosity compound.

21. The microelectronic assembly as claimed in claim 16, further comprising a laminate and/or an interposer, and wherein the plurality of stacks of molded microelectronic elements are hybrid bonded to the laminate or the interposer without an adhesive or an intermediate material.

22. The microelectronic assembly as claimed in claim 21, further comprising at least one wire bond pad on a surface of the laminate and/or on a surface of the interposer.

23. The microelectronic assembly of claim 21, wherein the laminate is coupled to the interposer using wires coupled at wire bond pads on a surface of the laminate and at wire bond pads on a surface of the interposer.

24. The microelectronic assembly of claim 21, further comprising a non-molded die hybrid bonded to the laminate and/or the interposer without an adhesive.

25. The microelectronic assembly of claim 16, wherein at least the second substrate includes a solid state memory device.

26. A method of forming a microelectronic assembly, comprising:

forming a microelectronic stack comprising:

providing a first substrate having a front side and a back side, the back side having a bonding surface including a non-conductive bonding layer and an exposed conductive first circuit element, the first substrate having a first conductive via electrically coupled to the first circuit element of the first substrate and extending at least partially through the first substrate;

providing a second substrate having a front side and a back side, the front side comprising a non-conductive bonding layer and an exposed conductive first circuit element;

coupling the front side of the second substrate to the back side of the first substrate by contacting the non-conductive bonding layer of the first substrate and the second substrate and contacting the first circuit element of the first substrate to the first circuit element of the second substrate, a side edge of the first substrate being misaligned relative to a side edge of the second substrate; and

covering at least the side edges of the second substrate with a molding.

27. The method of claim 26, further comprising covering the back side of the second substrate with the molding.

28. The method of claim 26, wherein the back side of the second substrate comprises a second non-conductive bonding layer and an exposed conductive second circuit element, the second substrate having a second conductive via electrically coupling the first circuit element and the second circuit element of the second substrate.

29. The method of claim 28, further comprising:

providing a third substrate having a front side and a back side, the front side comprising a non-conductive bonding layer and an exposed conductive first circuit element;

coupling the front side of the third substrate to the back side of the second substrate by contacting the non-conductive bonding layer of the third substrate to the non-conductive bonding layer of the second substrate and contacting the first circuit elements of the third substrate to the second circuit elements of the second substrate, side edges of the third substrate being misaligned relative to side edges of the second substrate and/or the first substrate; and

covering the side edges of the third substrate with the molding.

30. The method of claim 26, further comprising forming a recess at the bonding layer of the first and/or second substrate at a periphery of the first and/or second substrate before covering the side edges of the first and second substrate with the molding, and filling at least the recess with a low viscosity compound.

31. The method of claim 26, further comprising hybrid bonding said microelectronic stack to a semiconductor interposer having at least one wire bond contact pad.

32. The method of claim 31, further comprising coupling the interposer to a laminate having a second wirebond contact pad, and wirebonding the at least one wirebond contact pad of the interposer to the second wirebond contact pad of the laminate with a wire.

33. The method of claim 26, wherein forming the microelectronic assembly includes forming a plurality of the microelectronic stacks.

34. A microelectronic assembly, comprising:

a first die having a first bonding surface and a first microelectronic circuit element embedded therein, a portion of the first circuit element being exposed at the first bonding surface of the first die; and

a second die having a first bonding surface and a first microelectronic circuit element embedded therein, a portion of the first circuit element of the second die being exposed at the first bonding surface of the second die, the first bonding surface of the first die being hybrid bonded to the first bonding surface of the second die to electrically couple the first die to the second die without an adhesive layer, wherein a side edge of the first die includes a molding layer that is thinner than a molding layer disposed on a side edge of the second die.

35. A microelectronic assembly, comprising:

a first die having a first bonding surface including a first microelectronic circuit element;

a second die having a first bonding surface including a second microelectronic circuit element;

the first bonding surface of the first die is hybrid bonded to the first bonding surface of the second die to electrically couple the first die to the second die without an adhesive layer; and

a molding layer disposed on side edges of the first die and the second die, wherein a thickness of the molding layer on the first die is different than a thickness of the molding layer on the second die.

36. The microelectronic assembly of claim 35, further comprising a first conductive via electrically coupled to the first circuit element of the first die and extending at least partially through the first die.

37. The microelectronic assembly of claim 35, wherein the first bonding surface of the first die or the first bonding surface of the second die includes a plurality of circuit elements having a pitch of less than 20 microns.

38. The microelectronic assembly of claim 35, wherein the first bonding surface of the first die or the first bonding surface of the second die includes a plurality of circuit elements having a pitch of less than 1 micron.

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