CN205542754U - Packaging structure of fan -out cake core - Google Patents
Packaging structure of fan -out cake core Download PDFInfo
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- CN205542754U CN205542754U CN201620067650.2U CN201620067650U CN205542754U CN 205542754 U CN205542754 U CN 205542754U CN 201620067650 U CN201620067650 U CN 201620067650U CN 205542754 U CN205542754 U CN 205542754U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Abstract
The utility model provides a packaging structure of fan -out cake core, packaging structure includes: take the chip of lug, chip surface is formed with the dielectric layer, and expose on its surface has each lug, plastic package material fills between the chip of respectively taking the lug, plastic package material's height is no longer than each lug to make each lug expose in plastic package material's surface, the rewiring layer is formed at the chip surface who respectively takes the lug to realize the interconnection between each chip, and under the lug metal level and dimpling point. The utility model discloses a form the dielectric layer that exposes each lug at the chip surface that takes the lug, not only can protect each lug, and can realize the interconnection between the follow -up chip, can avoid the in -process of follow -up preparation rewiring layer or solder dimpling point, because the condition such as the damage of thermal energy and the lug that leads to or fracture have improved the performance that encapsulates greatly, carry high yield simultaneously.
Description
Technical field
This utility model relates to method for packing and the encapsulating structure of a kind of semiconductor chip, particularly relates to a kind of fan-out-type
The method for packing class encapsulation structure of chip.
Background technology
Along with the fast development of integrated circuit manufacturing industry, the requirement of the encapsulation technology of integrated circuit is the most constantly carried by people
Height, existing encapsulation technology includes BGA Package (BGA), chip size packages (CSP), wafer level packaging (WLP), three-dimensional
Encapsulation (3D) and system encapsulation (SiP) etc..Wherein, wafer level packaging (WLP) due to its outstanding advantage the most most
Semiconductor manufacturers is used, and its wholly or largely processing step is to complete on the silicon wafer of operation before completing,
Finally disk is cut directly into the individual devices of separation.The advantage that wafer level packaging (WLP) has its uniqueness: 1. encapsulation process
Efficiency is high, can process with multiple disks simultaneously；The advantage 2. with Flip-Chip Using, the gentliest, thin, short, little；3. with front operation
Comparing, only increase pin rewiring (RDL) and two operations of stud bump making, remaining is entirely traditional handicraft；4. reduce
Repeatedly test in conventional package.The most each large-scale IC encapsulation company put into one after another the research of this kind of WLP, exploitation and
Produce.
In existing fan-out-type chip encapsulation technology, the semiconductor chip great majority after cutting will not be with projection, so
And, in actual production process, it is likely encountered the abnormal problem of some, such as, how to encapsulate and be pre-formed with initial projection
Semiconductor chip, or how to realize being pre-formed with between the chip of initial projection and the chip without initial projection
Interconnection.
As shown in Fig. 1 a～Fig. 1 d, in existing technique, it is usually and first will be pre-formed with partly leading of initial projection 104
Body chip 203 is pasted on the pad pasting 102 of carrier 101, as shown in Figure 1a, then uses capsulation material 105 to carry out plastic packaging, such as figure
Shown in 1b, after plastic packaging, carrier 101 and pad pasting 102 are removed, as illustrated in figure 1 c, can make afterwards re-wiring layer 106 and
Make projection 107, as shown in Figure 1 d.During rewiring layer process later and solder reflow technique, plastic packaging material
Material is owing to having bigger thermal coefficient of expansion, thus metal coupling can be made the problems such as bending occur, especially easily causes
The situations such as the damaged fracture of initial projection, thus largely effect on the performance of encapsulating products.
For these reasons, it is provided that the method for the package quality of a kind of semiconductor chip that can improve with initial projection
It is necessary.
Utility model content
The shortcoming of prior art in view of the above, the purpose of this utility model is to provide the envelope of a kind of fan-out-type chip
Dress method and encapsulating structure, for solving in prior art the highest the asking of package quality of the semiconductor chip with initial projection
Topic.
For achieving the above object and other relevant purposes, this utility model provides the method for packing of a kind of fan-out-type chip,
Described fan-out package method includes: step 1), it is provided that the chip of band projection, form dielectric layer in described chip surface, described
The surface of dielectric layer is exposed each projection；Step 2), it is provided that a surface is formed with the carrier of adhesive layer, and by the core of each band projection
Sheet is bonded in described adhesive layer；Step 3), the chip of each band projection is packaged；Step 4), on the chip of each band projection
Form re-wiring layer, to realize the interconnection between each chip；And step 5), formed under projection on described re-wiring layer
Metal level and micro convex point.
As a kind of preferred version of the method for packing of fan-out-type chip of the present utility model, also include step 6), remove
Described carrier and adhesive layer.
As a kind of preferred version of the method for packing of fan-out-type chip of the present utility model, described carrier include glass,
One in transparent conductor material and transparent polymer.
Further, described adhesive layer includes UV adhesive glue, step 6) in, use exposure method to make described UV adhesive glue drop
Low stickiness, separates with capsulation material realizing it.
As a kind of preferred version of the method for packing of fan-out-type chip of the present utility model, described dielectric layer includes dioxy
One in SiClx, phosphorosilicate glass, silicon oxide carbide, carborundum and polymer.
As a kind of preferred version of the method for packing of fan-out-type chip of the present utility model, use spin-coating method, chemistry gas
Phase sedimentation or plasma reinforced chemical vapour deposition method form dielectric layer in described chip surface.
As a kind of preferred version of the method for packing of fan-out-type chip of the present utility model, step 3) in, convex to each band
Capsulation material height after the chip of block is packaged is less than each projection, so that each projection is exposed to the surface of capsulation material.
As a kind of preferred version of the method for packing of fan-out-type chip of the present utility model, step 3) in, convex to each band
The capsulation material that the chip of block is packaged using includes the one in polyimides, silica gel and epoxy resin.
As a kind of preferred version of the method for packing of fan-out-type chip of the present utility model, step 3) in, convex to each band
The technique that the chip of block is packaged using includes: Shooting Technique, compressing and forming process, typography, transfer modling technique, liquid
One in body sealant cures moulding process, vacuum lamination process and spin coating proceeding.
As a kind of preferred version of the method for packing of fan-out-type chip of the present utility model, step 4) including: step 4-
1), on the chip of each band projection, dielectric is formed；Step 4-2), use photoetching process and etching technics to be situated between in described insulation
Matter is formed and electrically draws corresponding through hole with chip；Step 4-3), filler metal conductor in each through hole, formed to connect and lead to
Hole；Step 4-4), the metal wiring layer of connection corresponding with described connection through hole is formed in described dielectric surface.
Preferably, step 4-4) in, use evaporation process, sputtering technology, electroplating technology or chemical plating process to make described
Metal wiring layer.
Preferably, the one during the material of described metal wiring layer includes aluminum, copper, stannum, nickel, gold and silver.
As a kind of preferred version of the method for packing of fan-out-type chip of the present utility model, described micro convex point includes gold stannum
Soldered ball, silver soldering ball, copper and tin soldered ball in one, or, described micro convex point includes copper post, be formed at the nickel dam on copper post, with
And it is formed at the soldered ball on described nickel dam.
This utility model also provides for the encapsulating structure of a kind of fan-out-type chip, including: the chip of band projection, described chip list
Face is formed with dielectric layer, and the surface of described dielectric layer is exposed each projection；Capsulation material, be filled in each band projection chip it
Between, the height of described capsulation material is less than each projection, so that each projection is exposed to the surface of capsulation material；Re-wiring layer,
It is formed at the chip surface of each band projection, to realize the interconnection between each chip；And Underbump metallization layer and micro convex point, shape
On re-wiring layer described in Cheng Yu.
As a kind of preferred version of the encapsulating structure of fan-out-type chip of the present utility model, described dielectric layer includes dioxy
One in SiClx, phosphorosilicate glass, silicon oxide carbide, carborundum and polymer.
As a kind of preferred version of the encapsulating structure of fan-out-type chip of the present utility model, described capsulation material includes gathering
One in acid imide, silica gel and epoxy resin.
As a kind of preferred version of the encapsulating structure of fan-out-type chip of the present utility model, described re-wiring layer bag
Include: be formed at the dielectric on the chip of each band projection；It is formed in described dielectric corresponding to electrically drawing with chip
Through hole；It is filled in the metallic conductor in described through hole；And be formed at described dielectric surface and be connected through hole pair with described
The metal wiring layer that should connect.
Preferably, the one during the material of described metal wiring layer includes aluminum, copper, stannum, nickel, gold and silver.
Preferably, the one during described micro convex point includes gold soldering ball, silver soldering ball, copper and tin soldered ball.
Preferably, described micro convex point includes copper post, is formed at the nickel dam on copper post and is formed at the weldering on described nickel dam
Ball.
As it has been described above, the method for packing of fan-out-type chip of the present utility model and encapsulating structure, have the advantages that
This utility model forms dielectric layer by the chip surface at band projection, and the surface of described dielectric layer is exposed and had each projection, no
Only each projection can be protected, and the interconnection between follow-up chip can be realized.Select the medium that thermal coefficient of expansion is relatively low
Layer, during follow-up making re-wiring layer or solder micro convex point can be avoided, breaking of the projection caused due to thermal expansion
The situations such as damage or fracture, substantially increase the performance of encapsulation, improve yield rate simultaneously.This utility model structural approach is simple,
Field of semiconductor package is with a wide range of applications.
Accompanying drawing explanation
Fig. 1 a～Fig. 1 d is shown as the knot that each step of method for packing of a kind of fan-out-type chip of the prior art is presented
Structure schematic diagram.
Fig. 2～Fig. 9 is shown as the structural representation that each step of method for packing of fan-out-type chip of the present utility model is presented
Figure.
Element numbers explanation
The chip of 201 band projections
202 metal pads
203 projections
204 dielectric layers
205 carriers
206 adhesive layers
207 capsulation materials
208 re-wiring layers
209 metal wiring layers
210 Underbump metallization layers
211 micro convex point
Detailed description of the invention
Below by way of specific instantiation, embodiment of the present utility model being described, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages of the present utility model and effect easily.This utility model can also be by additionally
Different detailed description of the invention is carried out or applies, the every details in this specification can also based on different viewpoints with should
With, under without departing from spirit of the present utility model, carry out various modification or change.
Refer to Fig. 2～Fig. 9.It should be noted that the diagram provided in the present embodiment illustrates this most in a schematic way
The basic conception of utility model, when then diagram only showing the assembly relevant with this utility model rather than implement according to reality
Component count, shape and size are drawn, and during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random changing
Become, and its assembly layout kenel is likely to increasingly complex.
As shown in Fig. 2～Fig. 9, the present embodiment provides the method for packing of a kind of fan-out-type chip, described fan-out package side
Method includes:
As shown in Figure 2 to 4, step 1 is first carried out), it is provided that the chip 201 of band projection 203, in described chip surface shape
Becoming dielectric layer 204, the surface of described dielectric layer 204 is exposed each projection 203.
Specifically, comprise the following steps:
As shown in Figures 2 and 3, step 1-1 is first carried out), it is provided that the wafer of the chip 201 of band projection 203, in described crystalline substance
Circular surfaces forms dielectric layer 204, and the surface of described dielectric layer 204 is exposed each projection 203.
As example, described dielectric layer 204 includes silicon dioxide, phosphorosilicate glass, silicon oxide carbide, carborundum and polymerization
One in thing.The selection of described dielectric layer 204 is the material that thermal coefficient of expansion is relatively low, can avoid follow-up making re-wiring layer
208 or solder micro convex point 211 during, the situation such as the breakage of the projection 203 caused due to thermal expansion or fracture, significantly carry
The high performance of encapsulation, improves yield rate simultaneously.
As example, spin-coating method, chemical vapour deposition technique or plasma reinforced chemical vapour deposition method can be used in institute
State chip surface and form dielectric layer 204.
In the present embodiment, described dielectric layer 204 is the silicon dioxide using plasma enhanced chemical vapor sedimentation to be formed
Layer.
As shown in Figure 4, then carry out step 1-2), described wafer is carried out sliver, it is thus achieved that independent band projection 203 and
The chip of dielectric layer 204.
As example, described projection 203 is made on the metal pad 202 of chip.
As it is shown in figure 5, then carry out step 2), it is provided that a surface is formed with the carrier 205 of adhesive layer 206, and by each band
The chip 201 of projection 203 is bonded in described adhesive layer 206.
As example, described adhesive layer 206 can be the UV adhesive glue or epoxy resin such as adhesive tape, formed by spin coating
Deng material, in the present embodiment, described adhesive layer 206 is the UV adhesive glue formed by spin coating, and this UV adhesive glue is at ultraviolet light
Irradiate lower stickiness can reduce.
As example, described carrier 205 can be the materials such as glass, pottery, metal, polymer, in the present embodiment, institute
State carrier 205 and include the one in glass, transparent conductor material and transparent polymer so that follow-up can be from carrier
The back side of 205 is exposed operation to above-mentioned UV adhesive glue, is greatly simplified follow-up stripping technology.
As shown in Figure 6, then carry out step 3), the chip 201 of each band projection 203 is packaged.
As example, capsulation material 207 height after being packaged the chip 201 of each band projection 203 is less than each convex
Block 203, so that each projection 203 is exposed to the surface of capsulation material 207.
As example, the capsulation material 207 that the chip 201 of each band projection 203 is packaged using include polyimides,
One in silica gel and epoxy resin.Wherein, described capsulation material 207 is added and is formed light-proof material by additive.
As example, the technique being packaged using to the chip 201 of each band projection 203 includes: Shooting Technique, be compressed into
Type technique, typography, transfer modling technique, fluid sealant cure process, vacuum lamination process and spin coating proceeding
In one.In the present embodiment, by Shooting Technique, the chip 201 of each band projection 203 is packaged, described capsulation material
207 is lighttight silica gel.
As it is shown in fig. 7, then carry out step 4), on the chip 201 of each band projection 203, form re-wiring layer 208, with
Realize the interconnection between each chip.
As example, step 4) including:
Step 4-1), on the chip 201 of each band projection 203, form dielectric；
Step 4-2), use photoetching process and etching technics is formed in described dielectric electrically draw with chip right
The through hole answered；
Step 4-3), filler metal conductor in each through hole, formed and connect through hole；
Step 4-4), the metal wiring layer 209 of connection corresponding with described connection through hole is formed in described dielectric surface.
As example, step 4-4) in, use evaporation process, sputtering technology, electroplating technology or chemical plating process to make institute
State metal wiring layer 209.In the present embodiment, sputtering technology is used to make described metal wiring layer 209.
As example, the material of described metal wiring layer 209 includes the one in aluminum, copper, stannum, nickel, gold and silver.In this reality
Executing in example, the material of described metal wiring layer 209 is copper.
As shown in Figure 8, then carry out step 5), on described re-wiring layer 208 formed Underbump metallization layer 210 and
Micro convex point 211.
As example, described micro convex point 211 includes the one in gold soldering ball, silver soldering ball, copper and tin soldered ball, or, institute
State micro convex point 211 and include copper post, be formed at the nickel dam on copper post and be formed at the soldered ball on described nickel dam.At the present embodiment
In, described micro convex point 211 is gold soldering ball, and its making includes step: first form gold in described Underbump metallization layer 210 surface
Tin layers, then uses high temperature reflow processes to make described gold tin layers backflow glomeration, forms gold soldering ball after cooling.
As it is shown in figure 9, finally carry out step 6), remove described carrier 205 and adhesive layer 206.
As example, described carrier 205 includes the one in glass, transparent conductor material and transparent polymer.
As example, described adhesive layer 206 includes UV adhesive glue, step 6) in, use exposure method to make described UV bond
Glue reduces stickiness, separates with capsulation material 207 realizing it.
As it is shown in figure 9, the present embodiment also provides for the encapsulating structure of a kind of fan-out-type chip, including: the chip of band projection 203
201, described chip surface is formed with dielectric layer 204, and the surface of described dielectric layer 204 is exposed each projection 203；Capsulation material
207, it is filled between the chip 201 of each band projection 203, the height of described capsulation material 207 is less than each projection 203, so that
Each projection 203 is exposed to the surface of capsulation material 207；Re-wiring layer 208, is formed at chip 201 table of each band projection 203
Face, to realize the interconnection between each chip；And Underbump metallization layer 210 and micro convex point 211, it is formed at described rewiring
On layer 208.
As example, described dielectric layer 204 includes silicon dioxide, phosphorosilicate glass, silicon oxide carbide, carborundum and polymerization
One in thing.
As example, described capsulation material 207 includes the one in polyimides, silica gel and epoxy resin.
As example, described re-wiring layer 208 includes: the insulation being formed on the chip 201 of each band projection 203 is situated between
Matter；It is formed in described dielectric and electrically draws corresponding through hole with chip；It is filled in the metallic conductor in described through hole；
And it is formed at the metal wiring layer 209 of described dielectric surface connection corresponding with described connection through hole.
As example, the material of described metal wiring layer 209 includes the one in aluminum, copper, stannum, nickel, gold and silver.
As example, described micro convex point 211 includes the one in gold soldering ball, silver soldering ball, copper and tin soldered ball.
As example, described micro convex point 211 includes copper post, is formed at the nickel dam on copper post and is formed at described nickel dam
On soldered ball.
As it has been described above, the method for packing of fan-out-type chip of the present utility model and encapsulating structure, have the advantages that
This utility model by forming dielectric layer 204 on chip 201 surface of band projection 203, and the surface of described dielectric layer 204 is exposed
There is each projection 203, be possible not only to each projection 203 is protected, and the interconnection between follow-up chip can be realized.Select heat swollen
The dielectric layer 204 that swollen coefficient is relatively low, during follow-up making re-wiring layer 208 or solder micro convex point 211 can be avoided, by
The situations such as the breakage of the projection 203 caused in thermal expansion or fracture, substantially increase the performance of encapsulation, improve finished product simultaneously
Rate.This utility model structural approach is simple, is with a wide range of applications in field of semiconductor package.So, this utility model
Effectively overcome various shortcoming of the prior art and have high industrial utilization.
Above-described embodiment only illustrative principle of the present utility model and effect thereof are new not for limiting this practicality
Type.Above-described embodiment all can be carried out by any person skilled in the art under spirit and the scope of the present utility model
Modify or change.Therefore, art has usually intellectual such as without departing from the essence disclosed in this utility model
All equivalences completed under god and technological thought are modified or change, and must be contained by claim of the present utility model.
Claims (7)
1. the encapsulating structure of a fan-out-type chip, it is characterised in that including:
With the chip of projection, described chip surface is formed with dielectric layer, and the surface of described dielectric layer is exposed each projection；
Capsulation material, is filled between the chip of each band projection, and the height of described capsulation material is less than each projection, so that each convex
Block is exposed to the surface of capsulation material；
Re-wiring layer, is formed at the chip surface of each band projection, to realize the interconnection between each chip；
Underbump metallization layer and micro convex point, be formed on described re-wiring layer.
The encapsulating structure of fan-out-type chip the most according to claim 1, it is characterised in that: described dielectric layer includes titanium dioxide
One in silicon, phosphorosilicate glass, silicon oxide carbide, carborundum and polymer.
The encapsulating structure of fan-out-type chip the most according to claim 1, it is characterised in that: described capsulation material includes polyamides
One in imines, silica gel and epoxy resin.
The encapsulating structure of fan-out-type chip the most according to claim 1, it is characterised in that: described re-wiring layer includes:
It is formed at the dielectric on the chip of each band projection；
It is formed in described dielectric and electrically draws corresponding through hole with chip；
It is filled in the metallic conductor in described through hole；And
It is formed at the metal wiring layer of described dielectric surface connection corresponding with described through hole.
The encapsulating structure of fan-out-type chip the most according to claim 1, it is characterised in that: the material of described metal wiring layer
Including the one in aluminum, copper, stannum, nickel, gold and silver.
The encapsulating structure of fan-out-type chip the most according to claim 1, it is characterised in that: described micro convex point includes gold soldering
One in ball, silver soldering ball, copper and tin soldered ball.
The encapsulating structure of fan-out-type chip the most according to claim 1, it is characterised in that: described micro convex point includes copper post,
It is formed at the nickel dam on copper post and is formed at the soldered ball on described nickel dam.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620067650.2U CN205542754U (en) | 2016-01-22 | 2016-01-22 | Packaging structure of fan -out cake core |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620067650.2U CN205542754U (en) | 2016-01-22 | 2016-01-22 | Packaging structure of fan -out cake core |
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| Publication Number | Publication Date |
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| CN205542754U true CN205542754U (en) | 2016-08-31 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115433912A (en) * | 2022-08-30 | 2022-12-06 | 歌尔微电子股份有限公司 | Magnetic control sputtering method of BGA product and BGA product |
-
2016
- 2016-01-22 CN CN201620067650.2U patent/CN205542754U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115433912A (en) * | 2022-08-30 | 2022-12-06 | 歌尔微电子股份有限公司 | Magnetic control sputtering method of BGA product and BGA product |
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