CN105185717A - Wafer level chip encapsulation method - Google Patents
Wafer level chip encapsulation method Download PDFInfo
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- CN105185717A CN105185717A CN201510492479.XA CN201510492479A CN105185717A CN 105185717 A CN105185717 A CN 105185717A CN 201510492479 A CN201510492479 A CN 201510492479A CN 105185717 A CN105185717 A CN 105185717A
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- 238000000034 method Methods 0.000 title claims abstract description 98
- 238000005538 encapsulation Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 claims abstract description 65
- 239000000463 material Substances 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 77
- 239000012790 adhesive layer Substances 0.000 claims description 61
- 229920000642 polymer Polymers 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 13
- 239000000853 adhesive Substances 0.000 claims description 10
- 230000001070 adhesive effect Effects 0.000 claims description 10
- 239000003292 glue Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 239000002131 composite material Substances 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 8
- 239000011521 glass Substances 0.000 claims description 8
- 238000004528 spin coating Methods 0.000 claims description 8
- 239000000945 filler Substances 0.000 claims description 7
- 238000000926 separation method Methods 0.000 claims description 7
- 239000002390 adhesive tape Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 6
- 239000002904 solvent Substances 0.000 claims description 6
- 238000010992 reflux Methods 0.000 claims description 5
- 239000003822 epoxy resin Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 229920000647 polyepoxide Polymers 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 239000000969 carrier Substances 0.000 abstract description 2
- 238000001746 injection moulding Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 9
- 238000004806 packaging method and process Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000004033 plastic Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000012856 packing Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention provides a wafer level chip encapsulation method comprising the following steps: (1) providing a first carrier and a first bonding layer, and adhering semiconductor chips to the first bonding layer; (2) encapsulating the semiconductor chips through an injection molding process to form an encapsulation layer; (3) providing a second carrier and a second bonding layer, and adhering the encapsulation layer to the second bonding layer; (4) removing the first carrier and the first bonding layer; (5) forming a dielectric layer on the front of each semiconductor layer, and making a rewiring layer for each semiconductor chip based on the dielectric layer; (6) carrying out a ball reflow process on the rewiring layers to form micro bumps; and (7) removing the second carrier and the second bonding layer. According to the invention, the encapsulated semiconductor chips are fixed to the carriers in order to enhance the stability of the encapsulation material and prevent the encapsulation material from deforming in the subsequent rewiring process and ball mounting process. The wafer level chip encapsulation method has a broad application prospect in the field of semiconductor manufacturing.
Description
Technical field
The invention belongs to field of semiconductor manufacture, particularly relate to a kind of wafer stage chip encapsulation method.
Background technology
Along with the fast development of integrated circuit manufacturing industry, the requirement of people to the encapsulation technology of integrated circuit also improves constantly, and existing encapsulation technology comprises BGA Package (BGA), chip size packages (CSP), wafer level packaging (WLP), three-dimension packaging (3D) and system in package (SiP) etc.Wherein, wafer level packaging (WLP) due to its outstanding advantage gradually adopt by most semiconductor manufacturers, its whole or most of processing steps be operation before completing silicon wafer on complete, finally disk is directly cut into the individual devices of separation.Wafer level packaging (WLP) has the advantage of its uniqueness: 1. encapsulation process efficiency is high, can process by multiple disk simultaneously; 2. there is the advantage of Flip-Chip Using, namely gently, thin, short, little; 3., compared with front operation, only increase pin rewiring (RDL) and stud bump making two operations, all the other are all traditional handicrafts; 4. the repeatedly test in conventional package is decreased.Therefore each large-scale IC encapsulates research, the development and production that company drops into this kind of WLP one after another in the world.The deficiency of WLP is that current number of pins is lower, also do not have standardization and cost higher.Key technology involved by WLP, except the necessary Metal deposition technology of front operation, photoetching technique, etching technique etc., also comprises rewiring (RDL) technology and stud bump making technology.Exit pad on usual chip is discharged to the square aluminium lamination in die perimeter, the wider pad pitch of SMT second level package has been adapted in order to make WLP, these pads need be redistributed, these pads are arranged by chip perimeter and changes array arrangement on chip active face into, this just needs rewiring (RDL) technology.
Re-wiring layer (RDL) is the connection interface between flip-chip assembly chips and encapsulation.Re-wiring layer is an extra metal level, is made up of core metal top trace, for the I/O pad of nude film is outwards tied to other positions such as such as bump pad.Salient point is arranged with comb mesh pattern usually, and each salient point is cast with two pads (at top, in bottom), and they connect re-wiring layer and base plate for packaging respectively.
Existing fan-out-type chip encapsulation technology often faces one and compares distinct issues: assembly deflections.In existing technique, be generally that semiconductor chip face down is pasted on the pad pasting of carrier, then carry out plastic packaging, after plastic packaging, carrier and pad pasting are removed.At rewiring layer process afterwards and plant in the process of ball reflux technique, often there is the problems such as bending in capsulation material, thus greatly affects the performance of encapsulating products.
In order to overcome above-mentioned defect, existing a solution is, semiconductor chip is assemblied in capsulation material with facing up, due to described capsulation material by rigid carrier as support, this method greatly can reduce follow-up rewiring layer process and plant the deformation probability of the capsulation material that ball technique causes.But this method needs some processing steps such as increasing as grind, be thinning, thus can cause the raising of product cost.
In view of above reason, provide one to avoid rewiring and plant capsulation material in ball technical process and hold yielding problem, and don't the wafer stage chip encapsulation method increasing product cost is necessary.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of wafer stage chip encapsulation method, holds yielding problem for solve in prior art rewiring and plant capsulation material in ball technical process.
For achieving the above object and other relevant objects, the invention provides a kind of wafer stage chip encapsulation method, described wafer stage chip encapsulation method comprises step: 1) provide the first carrier, described first carrier surface has the first adhesive layer, and semiconductor chip face down is adhered to described first adhesive layer surface; 2) adopt Shooting Technique to encapsulate each semiconductor chip, form encapsulated layer; 3) provide Second support, described Second support surface has the second adhesive layer, and described encapsulated layer is bonded in described second adhesive layer; 4) described first adhesive layer and each semiconductor chip is separated, to remove described first carrier and the first adhesive layer; 5) dielectric layer is formed in each semiconductor chip front, and based on described dielectric layer to each semiconductor chip fabrication re-wiring layer; 6) carry out planting ball reflux technique on described re-wiring layer, form micro convex point; 7) described second adhesive layer and encapsulated layer is separated, to remove described Second support and the second adhesive layer.
As a kind of preferred version of wafer stage chip encapsulation method of the present invention, described semiconductor chip is fan-out-type semiconductor chip.
As a kind of preferred version of wafer stage chip encapsulation method of the present invention, described first carrier comprises the one in the polymer of glass, semiconductor, metal and rigidity.
As a kind of preferred version of wafer stage chip encapsulation method of the present invention, the adhesive glue that described first adhesive layer is the sticking adhesive tape of two-sided equal tool or is made by spin coating proceeding, the separation method of described first adhesive layer and each semiconductor chip comprises chemical-solvent method, UV light exposure method or heating and thermal insulation method.
As a kind of preferred version of wafer stage chip encapsulation method of the present invention, described Second support comprises the one in the polymer of glass, semiconductor, metal and rigidity.
As a kind of preferred version of wafer stage chip encapsulation method of the present invention, the adhesive glue that described second adhesive layer is the sticking adhesive tape of two-sided equal tool or is made by spin coating proceeding, the separation method of described second adhesive layer and described encapsulated layer comprises chemical-solvent method, UV light exposure method or heating and thermal insulation method.
As a kind of preferred version of wafer stage chip encapsulation method of the present invention, step 2) the encapsulating material that adopts of Shooting Technique be polymer composites.
Further, described polymer composites comprises the one in the epoxy resin of band filler and the Epocryl of band filler.
As a kind of preferred version of wafer stage chip encapsulation method of the present invention, step 5) comprise the following steps: 5-1) adopt depositing technics to form dielectric layer in each semiconductor chip front; 5-2) adopt photoetching process and etching technics to be formed in described dielectric layer and electrically draw corresponding through hole with semiconductor chip; 5-3) in each through hole, fill metallic conductor, form connecting through hole; The re-wiring layer of described connecting through hole correspondence connection 5-4) is formed in described dielectric layer surface.
Further, step 5-4) comprise the following steps: 5-4a) make photoetching offset plate figure in described dielectric layer surface; 5-4b) deposit or sputtering seed layer in described dielectric layer surface based on described photoetching offset plate figure; 5-4c) form metal connecting line based on described Seed Layer plated metallic conductor; 5-4d) remove described photoetching offset plate figure, to form re-wiring layer.
As mentioned above, wafer stage chip encapsulation method of the present invention, there is following beneficial effect: the present invention is fixed on carrier by the semiconductor chip that plastic packaging is good, to strengthen the stability of capsulation material, avoid capsulation material in follow-up rewiring technique and plant the problem that there will be distortion in ball technical process.Adopt method for packing of the present invention, the deformation of capsulation material can obtain good control, substantially increases the yield of product, and can save the cost of product.Step of the present invention is simple, greatly can improve the rate of finished products of product, be with a wide range of applications in field of semiconductor manufacture.
Accompanying drawing explanation
Fig. 1 is shown as the steps flow chart schematic diagram of wafer stage chip encapsulation method of the present invention.
Fig. 2 ~ Figure 11 is shown as the structural representation that each step of wafer stage chip encapsulation method of the present invention presents.
Element numbers explanation
11 first carriers
12 first adhesive layers
13 semiconductor chips
14 encapsulated layers
15 Second supports
16 second adhesive layers
17 dielectric layers
18 re-wiring layers
19 micro convex point
S11 ~ S17 step 1) ~ step 7)
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 1 ~ Figure 11.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in diagram but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
As shown in Fig. 1 ~ Figure 11, the present embodiment provides a kind of wafer stage chip encapsulation method, and described wafer stage chip encapsulation method comprises step:
As shown in FIG. 1 to 3, first carry out step 1) S11, provide the first carrier 11, described first carrier 11 surface has the first adhesive layer 12, and semiconductor chip 13 face down is adhered to described first adhesive layer 12 surface.
Described first carrier 11 can provide structure or the matrix of rigidity for described first adhesive layer 12 and follow-up encapsulated layer 14, such as, described first carrier 11 can select the one in the glass for having suitable shape, transparent semi-conducting material (as silicon chip etc.) and transparent polymer.In the present embodiment, described first carrier 11 is selected as glass.
Described first adhesive layer 12 preferably selects the jointing material with smooth finish surface to make, it must have certain adhesion with semiconductor chip 13, to ensure that semiconductor chip 13 can not produce the situations such as mobile in subsequent technique, in addition, itself and the first carrier 11 can have stronger adhesion, in general, the adhesion of itself and the first carrier 11 needs to be greater than the adhesion with semiconductor chip 13, described first adhesive layer 12 in follow-up technique for the separating layer between semiconductor chip 13 and the first carrier 11.The adhesive glue that described first adhesive layer is the sticking adhesive tape of two-sided equal tool or is made by spin coating proceeding.Exemplarily, described first adhesive layer 12 is UV adhesive glue, is formed at described first carrier 11 surface by spin coating proceeding.
In the present embodiment, the front of described semiconductor chip 13 is the one side that semiconductor chip 13 is formed with device and electrode extraction.
In the present embodiment, described semiconductor chip 13 is fan-out-type semiconductor chip.Certainly, in other embodiments, method for packing of the present invention also may be used for installing as devices such as memory device, display device, input module, discrete component, power supply, pressurizers, and is not limited thereto several examples enumerated in place.
As shown in Fig. 1 and Fig. 4, then carry out step 2) S12, adopt Shooting Technique to encapsulate each semiconductor chip 13, form encapsulated layer 14.
Exemplarily, the encapsulating material that described Shooting Technique adopts is polymer composites, is specially lighttight polymer composites.Further, described polymer composites comprises the epoxy resin of band filler and the Epocryl of band filler.In the present embodiment, described encapsulating material is the epoxy resin of band filler.Described encapsulated layer 14 in subsequent technique for fixing described semiconductor chip 13.
As shown in Figures 1 and 5, then carry out step 3) S13, provide Second support 15, described Second support 15 surface has the second adhesive layer 16, and described encapsulated layer 14 is bonded in described second adhesive layer 16.
Described Second support 15 can provide structure or the matrix of rigidity for described second adhesive layer 16 and follow-up encapsulated layer 14, such as, described Second support 15 can select the one in the glass for having suitable shape, transparent semi-conducting material (as silicon chip etc.) and transparent polymer.In the present embodiment, described Second support 15 is selected as glass.
Described second adhesive layer 16 preferably selects the jointing material with smooth finish surface to make, it must have certain adhesion with described encapsulated layer 14, in addition, itself and Second support 15 can have stronger adhesion, in general, the adhesion of itself and Second support 15 needs to be greater than the adhesion with described encapsulated layer 14, described second adhesive layer 16 in follow-up technique for the separating layer between described encapsulated layer 14 and Second support 15.The adhesive glue that described second adhesive layer is the sticking adhesive tape of two-sided equal tool or is made by spin coating proceeding.Exemplarily, described second adhesive layer 16 is UV adhesive glue, is formed at described Second support 15 surface by spin coating proceeding.
As shown in Figure 1 and Figure 6, then carry out step 4) S14, be separated described first adhesive layer 12 and each semiconductor chip 13, to remove described first carrier 11 and the first adhesive layer 12.
In general, the separation method of described first adhesive layer and each semiconductor chip comprises chemical-solvent method, UV light exposure method or heating and thermal insulation method.In the present embodiment, exposure method is adopted to make described first adhesive layer 12 (UV adhesive glue) reduce stickiness, to realize its being separated with each semiconductor chip, finally to remove described first carrier 11 and the first adhesive layer 12, in addition, because described encapsulated layer is made up of lighttight polymer composites, therefore, when exposing described first adhesive layer 12, can not have an impact to described second adhesive layer, to keep the stickiness of described second adhesive layer.
As shown in Fig. 1 and Fig. 7 ~ Fig. 8, then carry out step 5) S15, form dielectric layer 17 in each semiconductor chip 13 front, and based on described dielectric layer 17, re-wiring layer 18 is made to each semiconductor chip 13.
Exemplarily, specifically comprise the following steps:
Step 5-1), adopt depositing technics to form dielectric layer 17 in each semiconductor chip 13 front.Described dielectric layer 17 comprises the one in silicon dioxide and silicon nitride.In the present embodiment, described dielectric layer 17 is silicon dioxide, and it can by semiconductor chip 13 as described in being made in as methods such as vapour depositions.Certainly, other dielectric layer 17 is suitable for too, is not limited to cited example herein.
Step 5-2), adopt photoetching process and etching technics is formed in described dielectric layer 17 with semiconductor chip 13 electrical draw corresponding to through hole.
Step 5-3), in each through hole, fill metallic conductor, form connecting through hole.
Exemplarily, described metallic conductor comprises the metal materials such as Cu, Al, can by as the process fillings such as deposition, plating in as described in through hole, formation connecting through hole.In the present embodiment, described metallic conductor is Cu.
Step 5-4), the re-wiring layer 18 that described connecting through hole correspondence connects is formed in described dielectric layer 17 surface.
In the present embodiment, step 5-4) specifically comprise the following steps:
Step 5-4a), make photoetching offset plate figure in described dielectric layer 17 surface.
Step 5-4b), based on described photoetching offset plate figure in described dielectric layer 17 surface deposition or sputtering seed layer.In the present embodiment, described Seed Layer is Ti/Cu layer.
Step 5-4c), form metal connecting line based on described Seed Layer plated metallic conductor.
Step 5-4d), remove described photoetching offset plate figure, to form re-wiring layer 18.
As shown in Fig. 1 and Fig. 9, then carry out step 6) S16, carries out planting ball reflux technique, forms micro convex point 19 on described re-wiring layer 18;
As shown in Fig. 1 and Figure 10 ~ Figure 11, finally carry out step 7) S17, be separated described second adhesive layer 16 and encapsulated layer 14, to remove described Second support 15 and the second adhesive layer 16.
In general, the separation method of described second adhesive layer and described encapsulated layer comprises chemical-solvent method, UV light exposure method or heating and thermal insulation method.In the present embodiment, exposure method is adopted to make described second adhesive layer 16 (UV adhesive glue) reduce stickiness, to realize its being separated, finally to remove described Second support 15 and the second adhesive layer 16 with described encapsulated layer 14.
As mentioned above, the invention provides a kind of wafer stage chip encapsulation method, described wafer stage chip encapsulation method comprises step: 1) provide the first carrier 11, described first carrier 11 surface has the first adhesive layer 12, and semiconductor chip 13 face down is adhered to described first adhesive layer 12 surface; 2) adopt Shooting Technique to encapsulate each semiconductor chip 13, form encapsulated layer 14; 3) provide Second support 15, described Second support 15 surface has the second adhesive layer 16, and described encapsulated layer 14 is bonded in described second adhesive layer 16; 4) described first adhesive layer 12 and each semiconductor chip 13 is separated, to remove described first carrier 11 and the first adhesive layer 12; 5) form dielectric layer 17 in each semiconductor chip 13 front, and based on described dielectric layer 17, re-wiring layer 18 is made to each semiconductor chip 13; 6) carry out planting ball reflux technique on described re-wiring layer 18, form micro convex point 19; 7) described second adhesive layer 16 and encapsulated layer 14 is separated, to remove described Second support 15 and the second adhesive layer 16.The present invention, by being fixed on carrier by semiconductor chip 13 good for plastic packaging, to strengthen the stability of capsulation material, avoiding capsulation material in follow-up rewiring technique and plants the problem that there will be distortion in ball technical process.Adopt method for packing of the present invention, the deformation of capsulation material can obtain good control, substantially increases the yield of product, and can save the cost of product.Step of the present invention is simple, greatly can improve the rate of finished products of product, be with a wide range of applications in field of semiconductor manufacture.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (10)
1. a wafer stage chip encapsulation method, is characterized in that, described wafer stage chip encapsulation method comprises step:
1) provide the first carrier, described first carrier surface has the first adhesive layer, and semiconductor chip face down is adhered to described first adhesive layer surface;
2) adopt Shooting Technique to encapsulate each semiconductor chip, form encapsulated layer;
3) provide Second support, described Second support surface has the second adhesive layer, and described encapsulated layer is bonded in described second adhesive layer;
4) described first adhesive layer and each semiconductor chip is separated, to remove described first carrier and the first adhesive layer;
5) dielectric layer is formed in each semiconductor chip front, and based on described dielectric layer to each semiconductor chip fabrication re-wiring layer;
6) carry out planting ball reflux technique on described re-wiring layer, form micro convex point;
7) described second adhesive layer and encapsulated layer is separated, to remove described Second support and the second adhesive layer.
2. wafer stage chip encapsulation method according to claim 1, is characterized in that: described semiconductor chip is fan-out-type semiconductor chip.
3. wafer stage chip encapsulation method according to claim 1, is characterized in that: described first carrier comprises the polymer of glass ,-semi-conducting material, metal and rigidity.
4. wafer stage chip encapsulation method according to claim 1, it is characterized in that: the adhesive glue that described first adhesive layer is the sticking adhesive tape of two-sided equal tool or is made by spin coating proceeding, the separation method of described first adhesive layer and each semiconductor chip comprises chemical-solvent method, UV light exposure method or heating and thermal insulation method.
5. wafer stage chip encapsulation method according to claim 1, is characterized in that: described Second support comprises the one in the polymer of glass, semiconductor, metal and rigidity.
6. wafer stage chip encapsulation method according to claim 1, it is characterized in that: the adhesive glue that described second adhesive layer is the sticking adhesive tape of two-sided equal tool or is made by spin coating proceeding, the separation method of described second adhesive layer and described encapsulated layer comprises chemical-solvent method, UV light exposure method or heating and thermal insulation method.
7. wafer stage chip encapsulation method according to claim 1, is characterized in that: step 2) Shooting Technique adopt encapsulating material be polymer composites.
8. wafer stage chip encapsulation method according to claim 7, is characterized in that: described polymer composites comprises the one in the epoxy resin of band filler and the Epocryl of band filler.
9. wafer stage chip encapsulation method according to claim 1, is characterized in that: step 5) comprise the following steps:
Depositing technics 5-1) is adopted to form dielectric layer in each semiconductor chip front;
5-2) adopt photoetching process and etching technics to be formed in described dielectric layer and electrically draw corresponding through hole with semiconductor chip;
5-3) in each through hole, fill metallic conductor, form connecting through hole;
The re-wiring layer of described connecting through hole correspondence connection 5-4) is formed in described dielectric layer surface.
10. wafer stage chip encapsulation method according to claim 9, is characterized in that: step 5-4) comprise the following steps:
5-4a) make photoetching offset plate figure in described dielectric layer surface;
5-4b) deposit or sputtering seed layer in described dielectric layer surface based on described photoetching offset plate figure;
5-4c) form metal connecting line based on described Seed Layer plated metallic conductor;
5-4d) remove described photoetching offset plate figure, to form re-wiring layer.
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| CN201510492479.XA CN105185717A (en) | 2015-08-12 | 2015-08-12 | Wafer level chip encapsulation method |
| PCT/CN2016/082848 WO2017024847A1 (en) | 2015-08-12 | 2016-05-20 | Wafer level chip packaging method |
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