CN207977309U - Fan-out-type semiconductor package with antenna module - Google Patents
Fan-out-type semiconductor package with antenna module Download PDFInfo
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- CN207977309U CN207977309U CN201721686212.5U CN201721686212U CN207977309U CN 207977309 U CN207977309 U CN 207977309U CN 201721686212 U CN201721686212 U CN 201721686212U CN 207977309 U CN207977309 U CN 207977309U
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- material layer
- interstitital texture
- capsulation material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
The utility model provides a kind of fan-out-type semiconductor package with antenna module, including：Semiconductor chip；Capsulation material layer, capsulation material layer plastic packaging is in the periphery of semiconductor chip；Interstitital texture is located in capsulation material layer, and positioned at semiconductor chip periphery；Interstitital texture is lost caused by aerial signal to be lost less than capsulation material layer caused by aerial signal；Antenna module is located at the first surface of capsulation material layer, and orthographic projection of the antenna module in interstitital texture is fully located in interstitital texture；Re-wiring layer is located at the second surface of capsulation material layer；Solder projection is located on surface of the re-wiring layer far from capsulation material layer.The utility model is less than the interstitital texture that the capsulation material layer is lost caused by aerial signal by the way that the loss caused by aerial signal is arranged in the capsulation material layer below antenna module, the loss to aerial signal can be effectively reduced, to significantly improve the performance of device.
Description
Technical field
The utility model is related to technical field of semiconductors, more particularly to a kind of fan-out-type semiconductor with antenna module
Encapsulating structure.
Background technology
Currently, the considerations of for communication efficiency, antenna, the fan-out-type of radio frequency chip can be all arranged in radio frequency chip when in use
Wafer-level packaging method is generally：Carrier is provided, adhesive layer is formed in carrier surface；On adhesive layer photoetching, be electroplated out again
Wiring layer (Redistribution Layers, RDL)；Radio frequency chip is installed to by re-wiring layer using chip bonding process
On；Using Shooting Technique by chip plastic packaging in capsulation material layer；Antenna is formed on the surface of the capsulation material layer；Removal carries
Body and adhesive layer；Photoetching, plating form Underbump metallization layer (UBM) on re-wiring layer；It carries out planting ball reflux on UBM,
Form soldered ball convex block；Then it carries out wafer and sticks piece, cutting scribing.From the foregoing, it will be observed that in existing radio frequency chip encapsulating structure, radio frequency
Chip plastic packaging is in capsulation material layer, and antenna is made in the surface of capsulation material layer and radio frequency chip is used cooperatively, the encapsulation knot
There are the following problems for structure：The lower section of antenna is capsulation material layer, and capsulation material layer can cause antenna signal larger loss, from
And influence the performance of structure.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of with antenna module
Fan-out-type semiconductor package is formed directly into capsulation material layer for solving antenna in the prior art, is below antenna
It is larger for antenna signal is lost caused by re-wiring layer, the problem of performance to influence structure.
In order to achieve the above objects and other related objects, the utility model provides a kind of fan-out-type with antenna module half
Conductor package structure, the fan-out-type semiconductor package with antenna module include：
Semiconductor chip；
Capsulation material layer, including opposite first surface and second surface, the capsulation material layer plastic packaging are partly led in described
The periphery of body chip, and expose the front of the semiconductor chip；
Interstitital texture is located in the capsulation material layer, and positioned at semiconductor chip periphery；The interstitital texture pair
Loss is lost less than the capsulation material layer caused by aerial signal caused by aerial signal；
Antenna module is located at the first surface of the capsulation material layer, and the antenna module is in the interstitital texture
Orthographic projection be fully located in the interstitital texture；
Re-wiring layer, is located at the second surface of the capsulation material layer, and is electrically connected with the semiconductor chip；
Solder projection, be located at surface of the re-wiring layer far from the capsulation material layer on, and with the cloth again
Line layer is electrically connected.
Preferably, the semiconductor chip includes：
Bare chip；
Contact pad is located on the bare chip, and is electrically connected with the bare chip；Wherein, where the contact pad
Surface be the semiconductor chip front.
Preferably, the interstitital texture includes：Glass-filled structure, silicon interstitital texture, 5880 interstitital textures of Roger, height
Molecular material interstitital texture or composite material interstitital texture.
Preferably, the interstitital texture is loop configuration, and the interstitital texture is surrounded on the semiconductor chip periphery, and
There is spacing with the semiconductor chip.
Preferably, the antenna module includes several antenna elements, several described antenna elements are in the plastic packaging material
Circumferentially-spaced arrangement of the first surface of the bed of material along the interstitital texture.
Preferably, the antenna element includes patch antenna or helical antenna.
Preferably, the antenna module include one along the interstitital texture circumferentially around helical antenna.
Preferably, the fan-out-type semiconductor package with antenna module further includes interconnection structure, the interconnection
Structure is electrically connected between the antenna module and the re-wiring layer, and with the antenna module and the re-wiring layer
It connects.
Preferably, the re-wiring layer includes：
Insulating layer is located at the second surface of the capsulation material layer；
At least one layer of metal line layer is located in the insulating layer；
Underbump metallization layer, be located at surface of the insulating layer far from the capsulation material layer, and with the metal line layer
Electrical connection.
The utility model also provides a kind of preparation method of the fan-out-type semiconductor package with antenna module, described
The preparation method of fan-out-type semiconductor package with antenna module includes the following steps：
1) carrier is provided, peeling layer is formed in the upper surface of the carrier；
2) semiconductor chip is provided, the semiconductor chip face down is installed in the surface of the peeling layer；
3) interstitital texture is provided, the interstitital texture is installed in the surface of the peeling layer, the interstitital texture position
In the periphery of the semiconductor chip；
4) capsulation material layer is formed in the surface of the peeling layer, the capsulation material layer is by the semiconductor chip and institute
State interstitital texture plastic packaging；The capsulation material layer includes opposite first surface and second surface, and the of the capsulation material layer
Two surfaces are in contact with the peeling layer；It is right less than the capsulation material layer that the interstitital texture is lost caused by aerial signal
Loss caused by aerial signal；
5) carrier and the peeling layer are removed；
6) re-wiring layer, the re-wiring layer and the semiconductor are formed in the second surface of the capsulation material layer
Chip is electrically connected；
7) antenna module is formed in the first surface of the capsulation material layer, the antenna module is in the interstitital texture
Orthographic projection be fully located in the interstitital texture；
8) in the re-wiring layer, surface far from the capsulation material layer forms soldered ball convex block, the soldered ball convex block with
The re-wiring layer electrical connection.
Preferably, the interstitital texture being supplied in step 3) includes：Glass-filled structure, silicon interstitital texture, Roger
5880 interstitital textures, high molecular material interstitital texture or composite material interstitital texture.
Preferably, the interstitital texture provided in step 3) is loop configuration, and the interstitital texture is surrounded on described half
Conductor chip periphery, and there is spacing with the semiconductor chip.
Preferably, in step 7), the specific method that antenna module is formed in the first surface of the capsulation material layer is：
Several antennas along the circumferentially-spaced arrangement of the interstitital texture are formed in the first surface of the capsulation material layer
Unit, several described antenna elements are collectively as the antenna module；Wherein, the antenna element includes patch antenna or spiral shell
Revolve shape antenna.
Preferably, in step 7), the specific method that antenna module is formed in the first surface of the capsulation material layer is：
In the capsulation material layer first surface formed one along the interstitital texture circumferentially around helical antenna make
For the antenna module.
Preferably, further include following steps between step 6) and step 7)：It is formed up and down in the interstitital texture
The interconnection structure of the interstitital texture and the capsulation material layer, the interconnection structure are electrically connected with the re-wiring layer；Step
Rapid 7) the middle antenna formed is electrically connected with the interconnection structure.
As described above, the fan-out-type semiconductor package with antenna module of the utility model, has beneficial below
Effect：The fan-out-type semiconductor package with antenna module of the utility model passes through the plastic packaging material below antenna module
The loss caused by aerial signal is set in the bed of material and is less than the filling knot that the capsulation material layer is lost caused by aerial signal
Structure can effectively reduce the loss to aerial signal, to significantly improve the performance of device.
Description of the drawings
Fig. 1 is shown as the fan-out-type semiconductor package with antenna module provided in the utility model embodiment one
Preparation method flow chart.
Fig. 2~Figure 17 is shown as the fan-out-type semiconductor package with antenna module provided in the utility model embodiment one
The structural schematic diagram that each step of preparation method of assembling structure is presented, wherein Figure 16 and Figure 17 is shown as the tool of the utility model
There is the structural schematic diagram of the fan-out-type semiconductor package of antenna module.
Component label instructions
10 carriers
11 peeling layers
12 semiconductor chips
121 bare chips
122 contact pads
13 interstitital textures
14 capsulation material layers
15 re-wiring layers
151 insulating layers
152 metal line layers
153 Underbump metallization layers
16 antenna modules
161 antenna elements
17 soldered ball convex blocks
18 interconnection structures
Specific implementation mode
Illustrate that the embodiment of the utility model, those skilled in the art can be by this theorys below by way of specific specific example
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different specific implementation modes are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Please refer to Fig.1~Figure 17.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, though when only display is with related component in the utility model rather than according to actual implementation in diagram
Component count, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can be a kind of random change
Become, and its assembly layout form may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the present embodiment provides a kind of preparation sides of the fan-out-type semiconductor package with antenna module
The preparation method of method, the fan-out-type semiconductor package with antenna module includes the following steps：
1) carrier is provided, peeling layer is formed in the upper surface of the carrier；
2) semiconductor chip is provided, the semiconductor chip face down is installed in the surface of the peeling layer；
3) interstitital texture is provided, the interstitital texture is installed in the surface of the peeling layer, the interstitital texture position
In the periphery of the semiconductor chip；
4) capsulation material layer is formed in the surface of the peeling layer, the capsulation material layer is by the semiconductor chip and institute
State interstitital texture plastic packaging；The capsulation material layer includes opposite first surface and second surface, and the of the capsulation material layer
Two surfaces are in contact with the peeling layer；It is right less than the capsulation material layer that the interstitital texture is lost caused by aerial signal
Loss caused by aerial signal；
5) carrier and the peeling layer are removed；
6) re-wiring layer, the re-wiring layer and the semiconductor are formed in the second surface of the capsulation material layer
Chip is electrically connected；
7) antenna module is formed in the first surface of the capsulation material layer, the antenna module is in the interstitital texture
Orthographic projection be fully located in the interstitital texture；
8) in the re-wiring layer, surface far from the capsulation material layer forms soldered ball convex block, the soldered ball convex block with
The re-wiring layer electrical connection.
In step 1), the S1 steps in please referring to Fig.1 and Fig. 2 and Fig. 3 provide a carrier 10, in the carrier 10
Upper surface forms peeling layer 11.
As an example, as shown in Fig. 2, the material of the carrier 10 includes but not limited to silicon, glass, silica, ceramics, gathers
Close the composite material of one or more of object and metal, shape can be wafer shape, rectangular or other arbitrary institutes
Need shape；The present embodiment prevents semiconductor chip in subsequent preparation process from rupture, warpage, fracture occurs by the carrier 10
The problems such as.
As an example, as shown in figure 3, the peeling layer 11 is in the subsequent process as the semiconductor core being subsequently formed
Separating layer between piece 12, the interstitital texture 13 and the capsulation material layer 14 and the carrier 10, preferably selecting has
The jointing material of smooth finish surface is made, must be with the semiconductor chip 12, the interstitital texture 13 and the capsulation material
Layer 14 has certain binding force, to ensure the semiconductor chip 12, the interstitital texture 13 and the capsulation material layer 14
Situations such as mobile is not will produce in the subsequent process, in addition, it also has stronger binding force with the carrier 10；It is general next
It says, the peeling layer 11 and the binding force of carrier 10 should be greater than itself and the semiconductor chip 12, the interstitital texture 13 and institute
State the binding force of capsulation material layer 14.As an example, the material of the peeling layer 11 be selected from it is two-sided all have viscosity adhesive tape or
The adhesive glue etc. made by spin coating proceeding.Adhesive tape preferably uses UV adhesive tapes, is easy to pull off after the irradiation of UV light.At it
In its embodiment, the other materials that physical vaporous deposition or chemical vapour deposition technique are formed also can be selected in the peeling layer 11
Layer, such as epoxy resin (Epoxy), silicon rubber (silicone rubber), polyimides (PI), polybenzoxazoles (PBO), benzene
And cyclobutane (BCB) etc..The methods of described in later separation when carrier 10, wet etching, chemical mechanical grinding can be used, remove
Remove the peeling layer 11.
In step 2), the S2 steps in please referring to Fig.1 and Fig. 4 provide semiconductor chip 12, by the semiconductor chip
12 face downs are installed in the surface of the peeling layer 11.
As an example, the semiconductor chip 12 can be any one chip, for example, radio frequency chip etc..Described half
Conductor chip 12 includes bare chip 121 and contact pad 122；Wherein, the contact pad 122 is located on the bare chip 121,
And it is electrically connected with the function element inside the bare chip 121；Surface where the contact pad 122 is the semiconductor core
The front of piece 12.
It should be noted that the semiconductor chip 12 can be existing any radio communication chip, for send and
Receive the communication information.The thickness of the semiconductor chip 12 can be set according to actual needs, it is preferable that the present embodiment
In, the thickness of the semiconductor chip 12 can be but be not limited only to 100 μm~200 μm.
As an example, the quantity of the semiconductor chip 12 can be filled according to actually being set on the peeling layer 11
If the semiconductor chip 12 quantity can be one, two or more.
In step 3), the S3 steps in please referring to Fig.1 and Fig. 5 provide an interstitital texture 13, by the interstitital texture 13
It is installed in the surface of the peeling layer 11, the interstitital texture 13 is located at the periphery of the semiconductor chip 12.
As an example, the interstitital texture 13 includes：Glass-filled structure, silicon interstitital texture, the filling knots of Roger 5880
Structure, high molecular material interstitital texture or composite material interstitital texture；That is the material of the interstitital texture 13 may include：Glass,
Silicon, Roger 5880, high molecular material or composite material etc..
As an example, the shape of the interstitital texture 13 can be set according to actual needs, it is preferable that the present embodiment
In, the interstitital texture 13 can be loop configuration, at this point, the interstitital texture 13 is surrounded on outside the semiconductor chip 12
It encloses.The interstitital texture 13 can be close to the side wall of the semiconductor chip 12, can also have with the semiconductor chip 12
Spacing, it is preferable that in the present embodiment, the interstitital texture 13 has spacing with the semiconductor chip 12.
As an example, the interstitital texture 13 be loop configuration when, the interstitital texture 13 can be cirque structure or
Rectangular loop structure etc..
It should be noted that when the interstitital texture 13 is loop configuration, the interstitital texture 13 can be continuous circular shape
Structure, or there is the loop configuration being intervally arranged including several fills units.
As an example, the height of the interstitital texture 13 can be identical as the height of the semiconductor chip 12, it can also
Less than the height of the semiconductor chip 12, the height of the semiconductor chip 12 can also be more than；That is the interstitital texture 13
Upper surface can with the upper surface flush of the semiconductor chip 12, can also be less than the semiconductor chip 12 upper table
Face can be above the upper surface of the semiconductor chip 12.With the height of the interstitital texture 13 and the semiconductor in Fig. 5
The height of chip 12 is identical to be used as example.
In step 4), the S4 steps in please referring to Fig.1 and Fig. 6 form capsulation material in the surface of the peeling layer 11
Layer 14, the capsulation material layer 14 is by 13 plastic packaging of the semiconductor chip 12 and the interstitital texture；The capsulation material layer 14
Including opposite first surface and second surface, the second surface of the capsulation material layer 14 is in contact with the peeling layer 11；
The interstitital texture 13 is lost caused by aerial signal to be lost less than the capsulation material layer 14 caused by aerial signal.
As an example, compressing and forming process, transfer shaping technology, hydraulic seal moulding process, molding bottom may be used
Fill process, capillary underfill technique, vacuum lamination process or spin coating proceeding form institute in the upper surface of the peeling layer 11
State capsulation material layer 14.Preferably, in the present embodiment, using molded underfill technique in the upper surface shape of the peeling layer 11
At the capsulation material layer 14.
As an example, the material of the capsulation material layer 14 can be but be not limited only to polyimide layer, layer of silica gel, epoxy
Resin layer, the curable polymeric substrate bed of material or the curable resin base material bed of material.
In one example, as shown in fig. 6, the capsulation material layer 14 formed in the upper surface of the peeling layer 11 is by institute
State semiconductor chip 12 and the interstitital texture 13 enveloping plastic packaging completely, i.e. the first surface of the capsulation material layer 14 is higher than institute
State the back side of semiconductor chip 12 and the upper surface of the interstitital texture 13.
In another example, it can also be formed according to the height of the semiconductor chip 12 or/and the interstitital texture 13
The capsulation material layer 14 so that the height of the capsulation material layer 14 of formation just with the height of the semiconductor chip 12
Or/and the height of the interstitital texture 13 is identical, i.e., so that the first surface of the capsulation material layer 14 is just partly led with described
The upper surface flush of the back side of body chip 12 or/and the interstitital texture 13.
In step 5), the S5 steps in please referring to Fig.1 and Fig. 7 remove the carrier 10 and the peeling layer 11.
As an example, grinding technics, reduction process etc., which may be used, is removed the carrier 10 and the peeling layer 11.
Preferably, it in the present embodiment, uses and tears the mode of the peeling layer 11 to remove the carrier 10.
As an example, when the upper surface of the capsulation material layer 14 it is as shown in FIG. 6 and 7 be higher than the semiconductor chip
Further include to the capsulation material as shown in figure 8, after step 5) when 12 back side and the upper surface of the interstitital texture 13
The first surface of layer 14 carries out the step of grinding is thinned, and the first surface to obtain the capsulation material layer 14 is just partly led with described
The upper surface flush of the back side of body chip 12 or/and the interstitital texture 13.Specifically, chemically mechanical polishing may be used
(CMP) technique carries out the first surface of the capsulation material layer 14 grinding is thinned.
The first surface of the capsulation material layer 14 is subtracted it is of course also possible to be executed between step 4) and step 5)
The step of thin grinding, executes before removing the carrier 10 and the peeling layer 11 to the first of the capsulation material layer 14
Surface carries out the step of grinding is thinned.
In step 6), the S6 steps in please referring to Fig.1 and Fig. 9 are formed in the second surface of the capsulation material layer 14
Re-wiring layer 15, the re-wiring layer 15 are electrically connected with the semiconductor chip 12.
In one example, as shown in figure 9, including one layer of metal line layer 152 in the re-wiring layer 15, at least one layer of exhausted
Edge layer 151 and Underbump metallization layer 153, forming the re-wiring layer 15 in the second surface of the capsulation material layer 14 includes
Following steps：
6-1) one layer of metal line layer 152, the metal are formed in the second surface of the capsulation material layer 14
Line layer 152 is electrically connected with the semiconductor chip 12；
The insulating layer 151 6-2) is formed in the second surface of the capsulation material layer 14, the insulating layer 151 will be described
Metal line layer 152 encapsulates, and the upper surface of the insulating layer 151 is higher than the upper surface of the metal line layer 152；
6-3) form opening in the insulating layer 151, the opening exposes the part metal line layer 152；
6-4) in forming the lower protruding block metal layer 153 in the opening.
In another example, as shown in figure 9, including one layer of metal line layer 152 in the re-wiring layer 15, at least one layer of
Insulating layer 151 and Underbump metallization layer 153 form the re-wiring layer 15 in the second surface of the capsulation material layer 14 and wrap
Include following steps：
6-1) insulating layer 151 described in first layer is formed in the second surface of the capsulation material layer 14；
The first opening 6-2) is formed in the insulating layer 151 described in first layer, first opening exposes part described half
The contact pad 122 of conductor chip 12；
The metal line layer 152 is formed in 6-3) being open in described first；
6-4) upper surface of the insulating layer 151 described in first layer forms insulating layer 151 described in the second layer；
65) the second opening is formed in the insulating layer 151 described in the second layer, second opening exposes the metal line layer
152；
The lower protruding block metal layer 153 is formed in 6-6) being open in described second.
As an example, in above-mentioned example, the material of the metal line layer 152 can be but be not limited only to copper, aluminium, nickel, only,
Silver or a kind of material in titanium or two or more combined materials, and the works such as PVD, CVD, sputtering, plating or chemical plating can be used
Skill forms the metal line layer 152.The material of the insulating layer 121 can be low k dielectric, specifically, the insulating layer
151 material may include a kind of material in epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass
Material, and the techniques such as spin coating, CVD, plasma enhanced CVD may be used and form the insulating layer 151.
As an example, can also include a following steps after step 6) as shown in Figure 10：In in the interstitital texture 13
Form the interconnection structure 18 of the interstitital texture 13 and the capsulation material layer 14 up and down, the interconnection structure 18 with it is described
Re-wiring layer 15 is electrically connected；Specifically, the interconnection structure 18 and the metal line layer 152 in the re-wiring layer 15
Electrical connection.The material of the interconnection structure 18 can be but be not limited only to copper, aluminium, nickel, only, silver or a kind of material in titanium or two
Kind or more combined material.
In step 7), the S7 steps in please referring to Fig.1 and Figure 11 to Figure 15, wherein described mutual not formed in Figure 11
Link the example of structure 18, Figure 12 is the example for being formed with the interconnection structure 18, in the first surface of the capsulation material layer 14
Antenna module 16 is formed, orthographic projection of the antenna module 16 in the interstitital texture 13 is fully located at the interstitital texture 13
On.
In one example, as shown in FIG. 13 and 14, Figure 13 and Figure 14 is the vertical view knot of Figure 11 and Figure 12 in different examples
Structure schematic diagram, the specific method that antenna module 16 is formed in the first surface of the capsulation material layer 14 are：In the plastic packaging material
The first surface of the bed of material 14 forms several antenna elements 161 along 13 circumferentially-spaced arrangement of the interstitital texture, several institutes
Antenna element 161 is stated collectively as the antenna module 16；Wherein, the antenna element 161 can be block as shown in fig. 13 that
Shape antenna, or helical antenna as shown in figure 14.
As an example, when the antenna element 161 is patch antenna as shown in fig. 13 that, the patch antenna can be
Metal derby；When the antenna element 161 is helical antenna as shown in figure 14, the helical antenna can be metal wire
Coiling is spiral and is formed, and other than rectangular coil shape antenna as shown in figure 14, the antenna element 161 can also be it
His arbitrary helical antenna, for example, round spiral antenna etc..
In another example, as shown in figure 15, antenna module 16 is formed in the first surface of the capsulation material layer 14
Specific method is：In the capsulation material layer 14 first surface formed one along the interstitital texture 13 circumferentially around helical form
Antenna is as the antenna module 16；The i.e. described antenna module 16 for one along metal antenna, described in fill out by the metal antenna
Fill structure 13 circumferentially around spiral.
As an example, in above-mentioned example, the material of the antenna module 16 may include but be not limited only to copper, aluminium, nickel,
One or more of gold, silver, tin, titanium；Wherein, the antenna module 16 can pass through physical gas-phase deposition
(PVD), one kind in chemical vapor deposition method (CVD), sputtering, plating or chemical plating is prepared.
As an example, as shown in figure 12, it is described when being formed with the interconnection structure 18 in the semiconductor package
Antenna module 16 is electrically connected with the interconnection structure 18, i.e., the described antenna module 16 via the interconnection structure 18 with it is described again
Wiring layer 15 is electrically connected.
It should be noted that when surface of the interstitital texture 13 far from the re-wiring layer 15 and the capsulation material
When the first surface flush of layer 14, the antenna module 16 is formed directly into the interstitital texture 13 far from the rewiring
On the surface of layer 15.
It should be further noted that in other examples, the sequence of step 6) and step 7) can be interchanged, i.e., can also
First surface prior to the capsulation material layer 14 forms the antenna module 16, then then at the of the capsulation material layer 14
Two surfaces form the re-wiring layer 15.
In step 8), the S8 steps in please referring to Fig.1 and Figure 16 to Figure 17, in the re-wiring layer 15 far from described
The surface of capsulation material layer 14 forms soldered ball convex block 17, and the soldered ball convex block 17 is electrically connected with the re-wiring layer 15.
In one example, to form the soldered ball in surface of the re-wiring layer 15 far from the capsulation material layer 14 convex
Block 17 includes the following steps：
Metal column (not shown) 8-1) is formed in the surface far from the capsulation material layer 14 of the re-wiring layer 15,
The metal column is electrically connected with the metal line layer 152 in the re-wiring layer 15；
8-2) soldered ball is formed in the surface far from the re-wiring layer 15 of the metal column.
As an example, the material of the metal column can be copper, aluminium, nickel, gold, silver, a kind of material in titanium or two kinds and
Two or more combined materials, can by physical gas-phase deposition (PVD), chemical vapor deposition method (CVD), sputtering,
Any one of plating or chemical plating technique form the metal column.The material of the soldered ball can be copper, aluminium, nickel, gold, silver,
A kind of material in titanium or two kinds and two or more combined materials can form the soldered ball by planting ball reflux technique.
In another example, as shown in FIG. 16 and 17, the soldered ball convex block 17 is a soldered ball, can be returned by planting ball
Stream technique directly forms soldered ball as the soldered ball convex block 17, the soldered ball convex block 17 directly in the re-wiring layer 15
The metal line layer 152 is electrically connected.As an example, the height of the soldered ball convex block 17 can be but be not limited only to 190 μm.
The fan-out-type semiconductor package with antenna module prepared by the utility model passes through in the antenna
The loss caused by aerial signal is set in the capsulation material layer 14 of 16 lower section of component and is less than 14 pairs of the capsulation material layer
The interstitital texture 13 being lost caused by aerial signal can effectively reduce the loss to aerial signal, to significantly improve
The performance of device.
Embodiment two
Please continue to refer to Figure 13 to Figure 17, the present embodiment also provides a kind of fan-out-type semiconductor packages with antenna module
The preparation method as described in embodiment one may be used in structure, the fan-out-type semiconductor package with antenna module
It is prepared, the fan-out-type semiconductor package with antenna module includes：Semiconductor chip 12；Capsulation material layer
14, the capsulation material layer 14 includes opposite first surface and second surface, and 14 plastic packaging of capsulation material layer is in described half
The periphery of conductor chip 12, and expose the front of the semiconductor chip 12；Interstitital texture 13, the interstitital texture 13 are located at
In the capsulation material layer 14, and positioned at 12 periphery of the semiconductor chip；The interstitital texture 13 is caused by aerial signal
Loss is lost less than the capsulation material layer 14 caused by aerial signal；Antenna module 16, the antenna module 16 are located at institute
The first surface of capsulation material layer 14 is stated, and orthographic projection of the antenna module 16 in the interstitital texture 13 is fully located at institute
It states in interstitital texture 13；Re-wiring layer 15, the re-wiring layer 15 are located at the second surface of the capsulation material layer 14, and
It is electrically connected with the semiconductor chip 12；Solder projection 17, the solder projection 17 are located at the re-wiring layer 15 far from institute
On the surface for stating capsulation material layer 14, and it is electrically connected with the re-wiring layer 15.
As an example, the semiconductor chip 12 can be any one chip, for example, radio frequency chip etc..Described half
Conductor chip 12 includes bare chip 121 and contact pad 122；Wherein, the contact pad 122 is located on the bare chip 121,
And it is electrically connected with the function element inside the bare chip 121；Surface where the contact pad 122 is the semiconductor core
The front of piece 12.
It should be noted that the semiconductor chip 12 can be existing any radio communication chip, for send and
Receive the communication information.The thickness of the semiconductor chip 12 can be set according to actual needs, it is preferable that the present embodiment
In, the thickness of the semiconductor chip 12 can be but be not limited only to 100 μm~200 μm.
As an example, the quantity of the semiconductor chip 12 can be filled according to actually being set on the peeling layer 11
If the semiconductor chip 12 quantity can be one, two or more.
As an example, the material of the capsulation material layer 14 can be but be not limited only to polyimide layer, layer of silica gel, epoxy
Resin layer, the curable polymeric substrate bed of material or the curable resin base material bed of material.
As an example, the first surface of the capsulation material layer 14 can with the back side of the semiconductor chip 12 or/and
Surface flush of the interstitital texture 13 far from the re-wiring layer 15 can also be higher than the back of the body of the semiconductor chip 12
The surface of face or/and the interstitital texture 13 far from the re-wiring layer 15.
As an example, the interstitital texture 13 includes：Glass-filled structure, silicon interstitital texture, the filling knots of Roger 5880
Structure, high molecular material interstitital texture or composite material interstitital texture；That is the material of the interstitital texture 13 may include：Glass,
Silicon, Roger 5880, high molecular material or composite material etc..
As an example, the shape of the interstitital texture 13 can be set according to actual needs, it is preferable that the present embodiment
In, the interstitital texture 13 can be loop configuration, at this point, the interstitital texture 13 is surrounded on outside the semiconductor chip 12
It encloses.The interstitital texture 13 can be close to the side wall of the semiconductor chip 12, can also have with the semiconductor chip 12
Spacing, it is preferable that in the present embodiment, the interstitital texture 13 has spacing with the semiconductor chip 12.
As an example, the interstitital texture 13 be loop configuration when, the interstitital texture 13 can be cirque structure or
Rectangular loop structure etc..
It should be noted that when the interstitital texture 13 is loop configuration, the interstitital texture 13 can be continuous circular shape
Structure, or there is the loop configuration being intervally arranged including several fills units.
As an example, the height of the interstitital texture 13 can be identical as the height of the semiconductor chip 12, it can also
Less than the height of the semiconductor chip 12, the height of the semiconductor chip 12 can also be more than；That is the interstitital texture 13
Upper surface can with the upper surface flush of the semiconductor chip 12, can also be less than the semiconductor chip 12 upper table
Face can be above the upper surface of the semiconductor chip 12.With the height of the interstitital texture 13 and the semiconductor in Fig. 5
The height of chip 12 is identical to be used as example.
In one example, the antenna module 16 includes several antenna elements 161, several described antenna elements 161
The capsulation material layer 14 first surface along the interstitital texture 13 circumferentially-spaced arrangement.Specifically, the antenna list
Member 161 can be patch antenna as shown in fig. 13 that, or helical antenna as described in Figure 14.When the antenna element
161 for patch antenna as shown in fig. 13 that when, the patch antenna can be metal derby；When the antenna element 161 is as schemed
Shown in 14 when helical antenna, the helical antenna can be formed for metal wire coiling is spiral, in addition to such as Figure 14
Shown in outside rectangular coil shape antenna, the antenna element 161 can also be any other helical antenna, for example, round spiral shell
Revolve shape antenna etc..
In another example, as shown in figure 15, the antenna module 16 include one along the interstitital texture circumferentially around
Helical antenna.The i.e. described antenna module 16 is one along metal antenna, week of the metal antenna along the interstitital texture 13
To around spiral.
As an example, in above-mentioned example, the material of the antenna module 16 may include but be not limited only to copper, aluminium, nickel,
One or more of gold, silver, tin, titanium；Wherein, the antenna module 16 can pass through physical gas-phase deposition
(PVD), one kind in chemical vapor deposition method (CVD), sputtering, plating or chemical plating is prepared.
As an example, the re-wiring layer 15 includes：Insulating layer 151, the insulating layer 151 are located at the capsulation material
The second surface of layer 14；At least one layer of metal line layer 152, the metal line layer 152 are located in the insulating layer 151；Under convex block
Metal layer 153, the Underbump metallization layer 153 are located at surface of the insulating layer 151 far from the capsulation material layer 14, and with
The metal line layer 152 is electrically connected.
As an example, the material of the metal line layer 152 can be but be not limited only to copper, aluminium, nickel, only, silver or titanium in
A kind of material or two or more combined materials, and can be used the techniques such as PVD, CVD, sputtering, plating or chemical plating formed it is described
Metal line layer 152.The material of the insulating layer 121 can be low k dielectric, specifically, the material of the insulating layer 151 can
With including a kind of material in epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass, and can adopt
The insulating layer 151 is formed with techniques such as spin coating, CVD, plasma enhanced CVDs.
As an example, as shown in figure 17, the fan-out-type semiconductor package with antenna module further includes interconnection
Structure 18, the interconnection structure 18 between the antenna module 16 and the re-wiring layer 15, and with the antenna sets
Part 16 and the re-wiring layer 15 are electrically connected.The material of the interconnection structure 18 can be but be not limited only to copper, aluminium, nickel, only,
Silver or a kind of material in titanium or two or more combined materials.
In one example, the soldered ball convex block 17 includes：Metal column, it is remote that the metal column is located at the re-wiring layer 15
Surface from the capsulation material layer 14, and be electrically connected with the re-wiring layer 15；Soldered ball, the soldered ball are located at the metal
The surface far from the capsulation material layer 14 of column.
In another example, as shown in FIG. 16 and 17, the soldered ball convex block 17 is soldered ball.
In conclusion the fan-out-type semiconductor package with antenna module of the utility model, described to have antenna
The fan-out-type semiconductor package of component includes：Semiconductor chip；Capsulation material layer, including opposite first surface and second
Surface, the capsulation material layer plastic packaging expose the front of the semiconductor chip in the periphery of the semiconductor chip；It fills out
Structure is filled, is located in the capsulation material layer, and positioned at semiconductor chip periphery；The interstitital texture makes aerial signal
At loss be lost caused by aerial signal less than the capsulation material layer；Antenna module is located at the capsulation material layer
First surface, and orthographic projection of the antenna module in the interstitital texture is fully located in the interstitital texture；Again cloth
Line layer, is located at the second surface of the capsulation material layer, and is electrically connected with the semiconductor chip；Solder projection is located at described
On surface of the re-wiring layer far from the capsulation material layer, and it is electrically connected with the re-wiring layer.The tool of the utility model
There is the fan-out-type semiconductor package of antenna module to believe antenna by being arranged in the capsulation material layer below antenna module
Loss is less than the interstitital texture that the capsulation material floor is lost caused by aerial signal caused by number, can effectively reduce to day
The loss of line signal, to significantly improve the performance of device.
The above embodiments are only illustrative of the principle and efficacy of the utility model, new not for this practicality is limited
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications completed under refreshing and technological thought or change, should be covered by the claim of the utility model.
Claims (9)
1. a kind of fan-out-type semiconductor package with antenna module, which is characterized in that the fan with antenna module
Going out type semiconductor package includes：
Semiconductor chip；
Capsulation material layer, including opposite first surface and second surface, the capsulation material layer plastic packaging is in the semiconductor core
The periphery of piece, and expose the front of the semiconductor chip；
Interstitital texture is located in the capsulation material layer, and positioned at semiconductor chip periphery；The interstitital texture is to antenna
Loss is lost less than the capsulation material layer caused by aerial signal caused by signal；
Antenna module, be located at the capsulation material layer first surface, and the antenna module in the interstitital texture just
Projection is fully located in the interstitital texture；
Re-wiring layer, is located at the second surface of the capsulation material layer, and is electrically connected with the semiconductor chip；
Solder projection, be located at surface of the re-wiring layer far from the capsulation material layer on, and with the re-wiring layer
Electrical connection.
2. the fan-out-type semiconductor package according to claim 1 with antenna module, which is characterized in that described half
Conductor chip includes：
Bare chip；
Contact pad is located on the bare chip, and is electrically connected with the bare chip；Wherein, the table where the contact pad
Face is the front of the semiconductor chip.
3. the fan-out-type semiconductor package according to claim 1 with antenna module, which is characterized in that described to fill out
Filling structure includes：Glass-filled structure, silicon interstitital texture, 5880 interstitital textures of Roger, high molecular material interstitital texture or multiple
Condensation material interstitital texture.
4. the fan-out-type semiconductor package according to claim 1 with antenna module, which is characterized in that described to fill out
It is loop configuration to fill structure, and the interstitital texture is surrounded on the semiconductor chip periphery, and has with the semiconductor chip
Spacing.
5. the fan-out-type semiconductor package according to claim 4 with antenna module, which is characterized in that the day
Line component includes several antenna elements, several described antenna elements are filled out in the first surface of the capsulation material layer described in
Fill the circumferentially-spaced arrangement of structure.
6. the fan-out-type semiconductor package according to claim 5 with antenna module, which is characterized in that the day
Line unit includes patch antenna or helical antenna.
7. the fan-out-type semiconductor package according to claim 4 with antenna module, which is characterized in that the day
Line component include one along the interstitital texture circumferentially around helical antenna.
8. the fan-out-type semiconductor package according to claim 1 with antenna module, which is characterized in that the tool
It further includes interconnection structure to have the fan-out-type semiconductor package of antenna module, the interconnection structure be located at the antenna module with
Between the re-wiring layer, and it is electrically connected with the antenna module and the re-wiring layer.
9. the fan-out-type semiconductor package according to claim 1 with antenna module, which is characterized in that described heavy
New route layer includes：
Insulating layer is located at the second surface of the capsulation material layer；
At least one layer of metal line layer is located in the insulating layer；
Underbump metallization layer is located at surface of the insulating layer far from the capsulation material layer, and is electrically connected with the metal line layer
It connects.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721686212.5U CN207977309U (en) | 2017-12-07 | 2017-12-07 | Fan-out-type semiconductor package with antenna module |
| US16/212,487 US10770394B2 (en) | 2017-12-07 | 2018-12-06 | Fan-out semiconductor packaging structure with antenna module and method making the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721686212.5U CN207977309U (en) | 2017-12-07 | 2017-12-07 | Fan-out-type semiconductor package with antenna module |
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| CN207977309U true CN207977309U (en) | 2018-10-16 |
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| CN201721686212.5U Active CN207977309U (en) | 2017-12-07 | 2017-12-07 | Fan-out-type semiconductor package with antenna module |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107910312A (en) * | 2017-12-07 | 2018-04-13 | 中芯长电半导体（江阴）有限公司 | Fan-out-type semiconductor package with antenna module and preparation method thereof |
| CN111668116A (en) * | 2019-03-08 | 2020-09-15 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method |
-
2017
- 2017-12-07 CN CN201721686212.5U patent/CN207977309U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107910312A (en) * | 2017-12-07 | 2018-04-13 | 中芯长电半导体（江阴）有限公司 | Fan-out-type semiconductor package with antenna module and preparation method thereof |
| CN111668116A (en) * | 2019-03-08 | 2020-09-15 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method |
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Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |
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