CN107910312A - Fan-out-type semiconductor package with antenna module and preparation method thereof - Google Patents
Fan-out-type semiconductor package with antenna module and preparation method thereof Download PDFInfo
- Publication number
- CN107910312A CN107910312A CN201711282005.8A CN201711282005A CN107910312A CN 107910312 A CN107910312 A CN 107910312A CN 201711282005 A CN201711282005 A CN 201711282005A CN 107910312 A CN107910312 A CN 107910312A
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- material layer
- interstitital texture
- antenna module
- capsulation material
- layer
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
- H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q19/00—Combinations of primary active antenna elements and units with secondary devices, e.g. with quasi-optical devices, for giving the antenna a desired directional characteristic
- H01Q19/10—Combinations of primary active antenna elements and units with secondary devices, e.g. with quasi-optical devices, for giving the antenna a desired directional characteristic using reflecting surfaces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
The present invention provides a kind of fan-out-type semiconductor package with antenna module and preparation method thereof, including：Semiconductor chip；Capsulation material layer, capsulation material layer plastic packaging is in the periphery of semiconductor chip；Interstitital texture, in capsulation material layer, and positioned at semiconductor chip periphery；Interstitital texture is lost caused by aerial signal to be lost less than capsulation material layer caused by aerial signal；Antenna module, positioned at the first surface of capsulation material layer, and orthographic projection of the antenna module in interstitital texture is fully located in interstitital texture；Re-wiring layer, positioned at the second surface of capsulation material layer；Solder projection, on surface of the re-wiring layer away from capsulation material layer.The present invention is by setting the loss caused by aerial signal to be less than the interstitital texture that the capsulation material layer is lost caused by aerial signal in the capsulation material layer below antenna module, the loss to aerial signal can be effectively reduced, so as to significantly improve the performance of device.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of fan-out-type semiconductor packages with antenna module
Structure and preparation method thereof.
Background technology
At present, for the consideration of communication efficiency, radio frequency chip can all set antenna, the fan-out-type of radio frequency chip when in use
Wafer-level packaging method is generally：Carrier is provided, adhesive layer is formed in carrier surface；On adhesive layer photoetching, electroplate out again
Wiring layer (Redistribution Layers, RDL)；Radio frequency chip is installed to by re-wiring layer using chip bonding process
On；Using Shooting Technique by chip plastic packaging in capsulation material layer；Antenna is formed on the surface of the capsulation material layer；Remove and carry
Body and adhesive layer；Photoetching, plating form Underbump metallization layer (UBM) on re-wiring layer；Carry out planting ball reflux on UBM,
Form soldered ball convex block；Then carry out wafer and stick piece, cutting scribing.From the foregoing, it will be observed that in existing radio frequency chip encapsulating structure, radio frequency
Chip plastic packaging is in capsulation material layer, and antenna is made in the surface of capsulation material layer and radio frequency chip is used cooperatively, the encapsulation knot
There are the following problems for structure：The lower section of antenna is capsulation material layer, and capsulation material layer can cause antenna signal larger loss, from
And influence the performance of structure.
The content of the invention
In view of the foregoing deficiencies of prior art, it is an object of the invention to provide a kind of being fanned out to antenna module
Type semiconductor package and preparation method thereof, capsulation material layer, day are formed directly into for solving antenna in the prior art
It is larger to the loss of antenna signal caused by the as re-wiring layer of line lower section, so that the problem of influencing the performance of structure.
In order to achieve the above objects and other related objects, the present invention provides a kind of fan-out-type semiconductor with antenna module
Encapsulating structure, the fan-out-type semiconductor package with antenna module include：
Semiconductor chip；
Capsulation material layer, including opposite first surface and second surface, the capsulation material layer plastic packaging are partly led in described
The periphery of body chip, and expose the front of the semiconductor chip；
Interstitital texture, in the capsulation material layer, and positioned at semiconductor chip periphery；The interstitital texture pair
Loss is lost less than the capsulation material layer caused by aerial signal caused by aerial signal；
Antenna module, positioned at the first surface of the capsulation material layer, and the antenna module is in the interstitital texture
Orthographic projection be fully located in the interstitital texture；
Re-wiring layer, is electrically connected positioned at the second surface of the capsulation material layer, and with the semiconductor chip；
Solder projection, on surface of the re-wiring layer away from the capsulation material layer, and with the cloth again
Line layer is electrically connected.
Preferably, the semiconductor chip includes：
Bare chip；
Contact pad, is electrically connected on the bare chip, and with the bare chip；Wherein, where the contact pad
Surface be the semiconductor chip front.
Preferably, the interstitital texture includes：Glass-filled structure, silicon interstitital texture, 5880 interstitital textures of Roger, height
Molecular material interstitital texture or composite material interstitital texture.
Preferably, the interstitital texture is loop configuration, and the interstitital texture is surrounded on the semiconductor chip periphery, and
There is spacing with the semiconductor chip.
Preferably, the antenna module includes several antenna elements, several described antenna elements are in the plastic packaging material
Circumferentially-spaced arrangement of the first surface of the bed of material along the interstitital texture.
Preferably, the antenna element includes patch antenna or helical antenna.
Preferably, the antenna module include one along the interstitital texture circumferentially around helical antenna.
Preferably, the fan-out-type semiconductor package with antenna module further includes interconnection structure, the interconnection
Structure is electrically connected between the antenna module and the re-wiring layer, and with the antenna module and the re-wiring layer
Connect.
Preferably, the re-wiring layer includes：
Insulating layer, positioned at the second surface of the capsulation material layer；
At least one layer of metal line layer, in the insulating layer；
Underbump metallization layer, positioned at surface of the insulating layer away from the capsulation material layer, and with the metal line layer
It is electrically connected.
It is described to have the present invention also provides a kind of preparation method of the fan-out-type semiconductor package with antenna module
The preparation method of the fan-out-type semiconductor package of antenna module includes the following steps：
1) carrier is provided, peel ply is formed in the upper surface of the carrier；
2) semiconductor chip is provided, the semiconductor chip face down is installed in the surface of the peel ply；
3) interstitital texture is provided, the interstitital texture is installed in the surface of the peel ply, the interstitital texture position
In the periphery of the semiconductor chip；
4) capsulation material layer is formed in the surface of the peel ply, the capsulation material layer is by the semiconductor chip and institute
State interstitital texture plastic packaging；The capsulation material layer includes opposite first surface and second surface, and the of the capsulation material layer
Two surfaces are in contact with the peel ply；It is right less than the capsulation material layer that the interstitital texture is lost caused by aerial signal
Loss caused by aerial signal；
5) carrier and the peel ply are removed；
6) re-wiring layer, the re-wiring layer and the semiconductor are formed in the second surface of the capsulation material layer
Chip is electrically connected；
7) antenna module is formed in the first surface of the capsulation material layer, the antenna module is in the interstitital texture
Orthographic projection be fully located in the interstitital texture；
8) form soldered ball convex block in surface of the re-wiring layer away from the capsulation material layer, the soldered ball convex block with
The re-wiring layer is electrically connected.
Preferably, the interstitital texture being supplied in step 3) includes：Glass-filled structure, silicon interstitital texture, Roger
5880 interstitital textures, high molecular material interstitital texture or composite material interstitital texture.
Preferably, the interstitital texture provided in step 3) is loop configuration, and the interstitital texture is surrounded on described half
Conductor chip periphery, and there is spacing with the semiconductor chip.
Preferably, in step 7), the specific method that antenna module is formed in the first surface of the capsulation material layer is：
Several antennas along the circumferentially-spaced arrangement of the interstitital texture are formed in the first surface of the capsulation material layer
Unit, several described antenna elements are collectively as the antenna module；Wherein, the antenna element includes patch antenna or spiral shell
Revolve shape antenna.
Preferably, in step 7), the specific method that antenna module is formed in the first surface of the capsulation material layer is：
In the capsulation material layer first surface formed one along the interstitital texture circumferentially around helical antenna make
For the antenna module.
Preferably, following steps are further included between step 6) and step 7)：In forming up/down perforation in the interstitital texture
The interconnection structure of the interstitital texture and the capsulation material layer, the interconnection structure are electrically connected with the re-wiring layer；Step
Rapid 7) the middle antenna formed is electrically connected with the interconnection structure.
As described above, fan-out-type semiconductor package with antenna module of the present invention and preparation method thereof, has
Following beneficial effect：The fan-out-type semiconductor package with antenna module of the present invention passes through the modeling below antenna module
The loss caused by aerial signal is set to be filled out less than what the capsulation material layer was lost caused by aerial signal in closure material layer
Structure is filled, can effectively reduce the loss to aerial signal, so as to significantly improve the performance of device.
Brief description of the drawings
Fig. 1 is shown as the system of the fan-out-type semiconductor package with antenna module provided in the embodiment of the present invention one
The flow chart of Preparation Method.
Fig. 2~Figure 17 is shown as the fan-out-type semiconductor packages knot with antenna module provided in the embodiment of the present invention one
The structure diagram that each step of preparation method of structure is presented, wherein, what Figure 16 and Figure 17 were shown as the present invention has antenna sets
The structure diagram of the fan-out-type semiconductor package of part.
Component label instructions
10 carriers
11 peel plies
12 semiconductor chips
121 bare chips
122 contact pads
13 interstitital textures
14 capsulation material layers
15 re-wiring layers
151 insulating layers
152 metal line layers
153 Underbump metallization layers
16 antenna modules
161 antenna elements
17 soldered ball convex blocks
18 interconnection structures
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Please refer to Fig.1~Figure 17.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though package count when only display is with related component in the present invention rather than according to actual implementation in diagram
Mesh, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout form may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the present embodiment provides a kind of preparation side of the fan-out-type semiconductor package with antenna module
Method, the preparation method of the fan-out-type semiconductor package with antenna module include the following steps：
1) carrier is provided, peel ply is formed in the upper surface of the carrier；
2) semiconductor chip is provided, the semiconductor chip face down is installed in the surface of the peel ply；
3) interstitital texture is provided, the interstitital texture is installed in the surface of the peel ply, the interstitital texture position
In the periphery of the semiconductor chip；
4) capsulation material layer is formed in the surface of the peel ply, the capsulation material layer is by the semiconductor chip and institute
State interstitital texture plastic packaging；The capsulation material layer includes opposite first surface and second surface, and the of the capsulation material layer
Two surfaces are in contact with the peel ply；It is right less than the capsulation material layer that the interstitital texture is lost caused by aerial signal
Loss caused by aerial signal；
5) carrier and the peel ply are removed；
6) re-wiring layer, the re-wiring layer and the semiconductor are formed in the second surface of the capsulation material layer
Chip is electrically connected；
7) antenna module is formed in the first surface of the capsulation material layer, the antenna module is in the interstitital texture
Orthographic projection be fully located in the interstitital texture；
8) form soldered ball convex block in surface of the re-wiring layer away from the capsulation material layer, the soldered ball convex block with
The re-wiring layer is electrically connected.
In step 1), S1 steps and Fig. 2 and Fig. 3 in please referring to Fig.1, there is provided a carrier 10, in the carrier 10
Upper surface forms peel ply 11.
As an example, as shown in Fig. 2, the material of the carrier 10 includes but not limited to silicon, glass, silica, ceramics, poly-
Composite material more than one or both of compound and metal, its shape can be wafer shape, square or other any institutes
Need shape；The present embodiment prevents that rupture, warpage, fracture occur for semiconductor chip in subsequent preparation process by the carrier 10
The problems such as.
As an example, as shown in figure 3, the peel ply 11 in subsequent technique as the semiconductor core being subsequently formed
Separating layer between piece 12, the interstitital texture 13 and the capsulation material layer 14 and the carrier 10, it, which is preferably selected, has
The jointing material of smooth finish surface is made, it must be with the semiconductor chip 12, the interstitital texture 13 and the capsulation material
Layer 14 has certain combination power, to ensure the semiconductor chip 12, the interstitital texture 13 and the capsulation material layer 14
Situations such as mobile will not be produced in subsequent technique, in addition, it also has stronger combination power with the carrier 10；It is general next
Say, the combination power of the peel ply 11 and carrier 10 should be greater than itself and the semiconductor chip 12, the interstitital texture 13 and institute
State the combination power of capsulation material layer 14.As an example, the material of the peel ply 11 be selected from it is two-sided be respectively provided with viscosity adhesive tape or
Adhesive glue made by spin coating proceeding etc..Adhesive tape preferably uses UV adhesive tapes, it is easy to pull off after the irradiation of UV light.At it
In its embodiment, the other materials that physical vaporous deposition or chemical vapour deposition technique are formed also can be selected in the peel ply 11
Layer, such as epoxy resin (Epoxy), silicon rubber (silicone rubber), polyimides (PI), polybenzoxazoles (PBO), benzene
And cyclobutane (BCB) etc..In carrier 10 described in later separation, the methods of wet etching, chemical mechanical grinding can be used, removed
Remove the peel ply 11.
In step 2), S2 steps and Fig. 4 in please referring to Fig.1, there is provided semiconductor chip 12, by the semiconductor chip
12 face downs are installed in the surface of the peel ply 11.
As an example, the semiconductor chip 12 can be any one chip, for example, radio frequency chip etc..Described half
Conductor chip 12 includes bare chip 121 and contact pad 122；Wherein, the contact pad 122 is located on the bare chip 121,
And it is electrically connected with the function element inside the bare chip 121；Surface where the contact pad 122 is the semiconductor core
The front of piece 12.
It should be noted that the semiconductor chip 12 can be existing any radio communication chip, for sending and
Receive the communication information.The thickness of the semiconductor chip 12 can be set according to actual needs, it is preferable that the present embodiment
In, the thickness of the semiconductor chip 12 can be but be not limited only to 100 μm~200 μm.
As an example, the quantity of the semiconductor chip 12 can be filled according to actually being set on the peel ply 11
If the semiconductor chip 12 quantity can be one, two or more.
In step 3), S3 steps and Fig. 5 in please referring to Fig.1, there is provided an interstitital texture 13, by the interstitital texture 13
The surface of the peel ply 11 is installed in, the interstitital texture 13 is located at the periphery of the semiconductor chip 12.
As an example, the interstitital texture 13 includes：Glass-filled structure, silicon interstitital texture, the filling knots of Roger 5880
Structure, high molecular material interstitital texture or composite material interstitital texture；The material of i.e. described interstitital texture 13 can include：Glass,
Silicon, Roger 5880, high molecular material or composite material etc..
As an example, the shape of the interstitital texture 13 can be set according to actual needs, it is preferable that the present embodiment
In, the interstitital texture 13 can be loop configuration, and at this time, the interstitital texture 13 is surrounded on outside the semiconductor chip 12
Enclose.The interstitital texture 13 can be close to the side wall of the semiconductor chip 12, can also have with the semiconductor chip 12
Spacing, it is preferable that in the present embodiment, the interstitital texture 13 has spacing with the semiconductor chip 12.
As an example, when the interstitital texture 13 is loop configuration, the interstitital texture 13 can be cirque structure or
Rectangular loop structure etc..
It should be noted that when the interstitital texture 13 is loop configuration, the interstitital texture 13 can be continuous circular shape
Structure, or there is the loop configuration being intervally arranged including several fills units.
As an example, the height of the interstitital texture 13 can be identical with the height of the semiconductor chip 12, can also
, can also be more than the height of the semiconductor chip 12 less than the height of the semiconductor chip 12；I.e. described interstitital texture 13
Upper surface can with the upper surface flush of the semiconductor chip 12, can also be less than the semiconductor chip 12 upper table
Face, can be above the upper surface of the semiconductor chip 12.With the height of the interstitital texture 13 and the semiconductor in Fig. 5
The height of chip 12 is identical to be used as example.
In step 4), S4 steps and Fig. 6 in please referring to Fig.1, capsulation material is formed in the surface of the peel ply 11
Layer 14, the capsulation material layer 14 is by 13 plastic packaging of the semiconductor chip 12 and the interstitital texture；The capsulation material layer 14
Including opposite first surface and second surface, the second surface of the capsulation material layer 14 is in contact with the peel ply 11；
The interstitital texture 13 is lost caused by aerial signal to be lost less than the capsulation material layer 14 caused by aerial signal.
As an example, compressing and forming process, transfer shaping technology, hydraulic seal moulding process, molding bottom can be used
Fill process, capillary underfill technique, vacuum lamination process or spin coating proceeding form institute in the upper surface of the peel ply 11
State capsulation material layer 14.Preferably, in the present embodiment, using molded underfill technique in the upper surface shape of the peel ply 11
Into the capsulation material layer 14.
As an example, the material of the capsulation material layer 14 can be but be not limited only to polyimide layer, layer of silica gel, epoxy
Resin bed, the curable polymeric substrate bed of material or the curable resin base material bed of material.
In one example, as shown in fig. 6, the capsulation material layer 14 formed in the upper surface of the peel ply 11 is by institute
State semiconductor chip 12 and the interstitital texture 13 encapsulates plastic packaging completely, i.e., the first surface of described capsulation material layer 14 is higher than institute
State the back side of semiconductor chip 12 and the upper surface of the interstitital texture 13.
In another example, can also be formed according to the height of the semiconductor chip 12 or/and the interstitital texture 13
The capsulation material layer 14 so that the height of the capsulation material layer 14 of formation just with the height of the semiconductor chip 12
Or/and the height of the interstitital texture 13 is identical, i.e., so that the first surface of the capsulation material layer 14 is just partly led with described
The back side of body chip 12 or/and the upper surface flush of the interstitital texture 13.
In step 5), S5 steps and Fig. 7 in please referring to Fig.1, remove the carrier 10 and the peel ply 11.
As an example, grinding technics, reduction process etc. can be used to be removed the carrier 10 and the peel ply 11.
Preferably, in the present embodiment, use and tear the mode of the peel ply 11 to remove the carrier 10.
As an example, when the capsulation material layer 14 upper surface as shown in FIG. 6 and 7 be higher than the semiconductor chip
When 12 back side and the upper surface of the interstitital texture 13, as shown in figure 8, after step 5), further include to the capsulation material
The step of first surface of layer 14 carries out that grinding is thinned, is just partly led with obtaining the first surface of the capsulation material layer 14 with described
The back side of body chip 12 or/and the upper surface flush of the interstitital texture 13.Specifically, chemically mechanical polishing can be used
(CMP) technique carries out the first surface of the capsulation material layer 14 grinding is thinned.
The first surface of the capsulation material layer 14 is subtracted it is of course also possible to be performed between step 4) and step 5)
The step of thin grinding, i.e., perform to the first of the capsulation material layer 14 before the carrier 10 and the peel ply 11 is removed
The step of surface carries out that grinding is thinned.
In step 6), S6 steps and Fig. 9 in please referring to Fig.1, form in the second surface of the capsulation material layer 14
Re-wiring layer 15, the re-wiring layer 15 are electrically connected with the semiconductor chip 12.
In one example, as shown in figure 9, including one layer of metal line layer 152, at least one layer in the re-wiring layer 15 absolutely
Edge layer 151 and Underbump metallization layer 153, forming the re-wiring layer 15 in the second surface of the capsulation material layer 14 includes
Following steps：
6-1) the described one layer metal line layer 152, the metal are formed in the second surface of the capsulation material layer 14
Line layer 152 is electrically connected with the semiconductor chip 12；
The insulating layer 151 6-2) is formed in the second surface of the capsulation material layer 14, the insulating layer 151 is by described in
Metal line layer 152 encapsulates, and the upper surface of the insulating layer 151 is higher than the upper surface of the metal line layer 152；
6-3) in forming opening in the insulating layer 151, the opening exposes the part metal line layer 152；
6-4) in forming the lower protruding block metal layer 153 in the opening.
In another example, as shown in figure 9, including one layer of metal line layer 152, at least one layer in the re-wiring layer 15
Insulating layer 151 and Underbump metallization layer 153, form the re-wiring layer 15 in the second surface of the capsulation material layer 14 and wrap
Include following steps：
6-1) insulating layer 151 described in first layer is formed in the second surface of the capsulation material layer 14；
6-2) in forming the first opening in insulating layer described in first layer 151, first opening exposes part described half
The contact pad 122 of conductor chip 12；
6-3) in the formation metal line layer 152 in the described first opening；
6-4) insulating layer 151 described in the second layer is formed in the upper surface of insulating layer described in first layer 151；
65) in forming the second opening in insulating layer described in the second layer 151, second opening exposes the metal line layer
152；
6-6) in the formation lower protruding block metal layer 153 in the described second opening.
As an example, in above-mentioned example, the material of the metal line layer 152 can be but be not limited only to copper, aluminium, nickel, only,
Silver or a kind of material in titanium or two or more combined materials, and the works such as PVD, CVD, sputtering, plating or chemical plating can be used
Skill forms the metal line layer 152.The material of the insulating layer 121 can be low k dielectric, specifically, the insulating layer
151 material can include a kind of material in epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass
Material, and the techniques such as spin coating, CVD, plasma enhanced CVD can be used to form the insulating layer 151.
As an example, as shown in Figure 10, a following steps can also be included after step 6)：In in the interstitital texture 13
Formed up/down perforation described in the interconnection structure 18 of interstitital texture 13 and the capsulation material layer 14, the interconnection structure 18 with it is described
Re-wiring layer 15 is electrically connected；Specifically, the interconnection structure 18 and the metal line layer 152 in the re-wiring layer 15
It is electrically connected.The material of the interconnection structure 18 can be but be not limited only to copper, aluminium, nickel, only, silver or titanium in a kind of material or two
The combined material of the kind above.
In step 7), the S7 steps and Figure 11 in please referring to Fig.1 to Figure 15, wherein, in Figure 11 for do not formed it is described mutually
Link the example of structure 18, Figure 12 is the example formed with the interconnection structure 18, in the first surface of the capsulation material layer 14
Antenna module 16 is formed, orthographic projection of the antenna module 16 in the interstitital texture 13 is fully located at the interstitital texture 13
On.
In one example, as shown in FIG. 13 and 14, Figure 13 and Figure 14 is the vertical view knot of Figure 11 and Figure 12 in different examples
Structure schematic diagram, the specific method that antenna module 16 is formed in the first surface of the capsulation material layer 14 are：In the plastic packaging material
The first surface of the bed of material 14 forms several antenna elements 161 along the 13 circumferentially-spaced arrangement of interstitital texture, several institutes
Antenna element 161 is stated collectively as the antenna module 16；Wherein, the antenna element 161 can be block as shown in fig. 13 that
Shape antenna, or helical antenna as shown in figure 14.
As an example, when the antenna element 161 is patch antenna as shown in fig. 13 that, the patch antenna can be
Metal derby；When the antenna element 161 is helical antenna as shown in figure 14, the helical antenna can be metal wire
Coiling curl and formed, in addition to rectangular coil shape antenna as shown in figure 14, the antenna element 161 can also be it
His any helical antenna, for example, round spiral antenna etc..
In another example, as shown in figure 15, antenna module 16 is formed in the first surface of the capsulation material layer 14
Specific method is：In the capsulation material layer 14 first surface formed one along the interstitital texture 13 circumferentially around helical form
Antenna is as the antenna module 16；I.e. described antenna module 16 is filled out for one along metal antenna, the metal antenna described in
Fill structure 13 circumferentially around curl.
As an example, in above-mentioned example, the material of the antenna module 16 can include but are not limited to copper, aluminium, nickel,
It is more than one or both of gold, silver, tin, titanium；Wherein, the antenna module 16 can pass through physical gas-phase deposition
(PVD), one kind in chemical vapor deposition method (CVD), sputtering, plating or chemical plating is prepared.
As an example, as shown in figure 12, it is described when in the semiconductor package formed with the interconnection structure 18
Antenna module 16 is electrically connected with the interconnection structure 18, i.e., described antenna module 16 via the interconnection structure 18 with it is described again
Wiring layer 15 is electrically connected.
It should be noted that when surface of the interstitital texture 13 away from the re-wiring layer 15 and the capsulation material
During the first surface flush of layer 14, the antenna module 16 is formed directly into the interstitital texture 13 away from the rewiring
On the surface of layer 15.
It should be further noted that in other examples, the order of step 6) and step 7) can exchange, i.e., can also
First surface prior to the capsulation material layer 14 forms the antenna module 16, then then at the of the capsulation material layer 14
Two surfaces form the re-wiring layer 15.
In step 8), S8 steps and Figure 16 to Figure 17 in please referring to Fig.1, in the re-wiring layer 15 away from described
The surface of capsulation material layer 14 forms soldered ball convex block 17, and the soldered ball convex block 17 is electrically connected with the re-wiring layer 15.
In one example, to form the soldered ball in surface of the re-wiring layer 15 away from the capsulation material layer 14 convex
Block 17 includes the following steps：
Metal column (not shown) 8-1) is formed in the surface of the remote capsulation material layer 14 of the re-wiring layer 15,
The metal column is electrically connected with the metal line layer 152 in the re-wiring layer 15；
8-2) soldered ball is formed in the surface of the remote re-wiring layer 15 of the metal column.
As an example, the material of the metal column can be copper, aluminium, nickel, gold, silver, a kind of material in titanium or two kinds and
Two or more combined materials, can by physical gas-phase deposition (PVD), chemical vapor deposition method (CVD), sputtering,
Any of plating or chemical plating technique form the metal column.The material of the soldered ball can be copper, aluminium, nickel, gold, silver,
A kind of material or two kinds and two or more combined materials in titanium, can form the soldered ball by planting ball reflux technique.
In another example, as shown in FIG. 16 and 17, the soldered ball convex block 17 is a soldered ball, can be returned by planting ball
Stream technique directly forms soldered ball as the soldered ball convex block 17, the soldered ball convex block 17 directly with the re-wiring layer 15
The metal line layer 152 is electrically connected.As an example, the height of the soldered ball convex block 17 can be but be not limited only to 190 μm.
The fan-out-type semiconductor package with antenna module prepared by the present invention passes through in the antenna module
The loss caused by aerial signal is set to be less than described 14 pairs of antenna of capsulation material layer in the capsulation material layer 14 of 16 lower sections
The interstitital texture 13 being lost caused by signal, can effectively reduce the loss to aerial signal, so as to significantly improve device
Performance.
Embodiment two
Please continue to refer to Figure 13 to Figure 17, the present embodiment also provides a kind of fan-out-type semiconductor packages with antenna module
Structure, the fan-out-type semiconductor package with antenna module can use the preparation method as described in embodiment one
It is prepared, the fan-out-type semiconductor package with antenna module includes：Semiconductor chip 12；Capsulation material layer
14, the capsulation material layer 14 includes opposite first surface and second surface, and 14 plastic packaging of capsulation material layer is in described half
The periphery of conductor chip 12, and expose the front of the semiconductor chip 12；Interstitital texture 13, the interstitital texture 13 are located at
In the capsulation material layer 14, and positioned at the periphery of semiconductor chip 12；The interstitital texture 13 is caused by aerial signal
Loss is lost less than the capsulation material layer 14 caused by aerial signal；Antenna module 16, the antenna module 16 are located at institute
The first surface of capsulation material layer 14 is stated, and orthographic projection of the antenna module 16 in the interstitital texture 13 is fully located at institute
State in interstitital texture 13；Re-wiring layer 15, the re-wiring layer 15 are located at the second surface of the capsulation material layer 14, and
It is electrically connected with the semiconductor chip 12；Solder projection 17, the solder projection 17 are located at the re-wiring layer 15 away from institute
On the surface for stating capsulation material layer 14, and it is electrically connected with the re-wiring layer 15.
As an example, the semiconductor chip 12 can be any one chip, for example, radio frequency chip etc..Described half
Conductor chip 12 includes bare chip 121 and contact pad 122；Wherein, the contact pad 122 is located on the bare chip 121,
And it is electrically connected with the function element inside the bare chip 121；Surface where the contact pad 122 is the semiconductor core
The front of piece 12.
It should be noted that the semiconductor chip 12 can be existing any radio communication chip, for sending and
Receive the communication information.The thickness of the semiconductor chip 12 can be set according to actual needs, it is preferable that the present embodiment
In, the thickness of the semiconductor chip 12 can be but be not limited only to 100 μm~200 μm.
As an example, the quantity of the semiconductor chip 12 can be filled according to actually being set on the peel ply 11
If the semiconductor chip 12 quantity can be one, two or more.
As an example, the material of the capsulation material layer 14 can be but be not limited only to polyimide layer, layer of silica gel, epoxy
Resin bed, the curable polymeric substrate bed of material or the curable resin base material bed of material.
As an example, the first surface of the capsulation material layer 14 can with the back side of the semiconductor chip 12 or/and
Surface flush of the interstitital texture 13 away from the re-wiring layer 15, can also be higher than the back of the body of the semiconductor chip 12
The surface of face or/and the interstitital texture 13 away from the re-wiring layer 15.
As an example, the interstitital texture 13 includes：Glass-filled structure, silicon interstitital texture, the filling knots of Roger 5880
Structure, high molecular material interstitital texture or composite material interstitital texture；The material of i.e. described interstitital texture 13 can include：Glass,
Silicon, Roger 5880, high molecular material or composite material etc..
As an example, the shape of the interstitital texture 13 can be set according to actual needs, it is preferable that the present embodiment
In, the interstitital texture 13 can be loop configuration, and at this time, the interstitital texture 13 is surrounded on outside the semiconductor chip 12
Enclose.The interstitital texture 13 can be close to the side wall of the semiconductor chip 12, can also have with the semiconductor chip 12
Spacing, it is preferable that in the present embodiment, the interstitital texture 13 has spacing with the semiconductor chip 12.
As an example, when the interstitital texture 13 is loop configuration, the interstitital texture 13 can be cirque structure or
Rectangular loop structure etc..
It should be noted that when the interstitital texture 13 is loop configuration, the interstitital texture 13 can be continuous circular shape
Structure, or there is the loop configuration being intervally arranged including several fills units.
As an example, the height of the interstitital texture 13 can be identical with the height of the semiconductor chip 12, can also
, can also be more than the height of the semiconductor chip 12 less than the height of the semiconductor chip 12；I.e. described interstitital texture 13
Upper surface can with the upper surface flush of the semiconductor chip 12, can also be less than the semiconductor chip 12 upper table
Face, can be above the upper surface of the semiconductor chip 12.With the height of the interstitital texture 13 and the semiconductor in Fig. 5
The height of chip 12 is identical to be used as example.
In one example, the antenna module 16 includes several antenna elements 161, several described antenna elements 161
In circumferentially-spaced arrangement of the first surface along the interstitital texture 13 of the capsulation material layer 14.Specifically, the antenna list
Member 161 can be patch antenna as shown in fig. 13 that, or helical antenna as described in Figure 14.When the antenna element
161 for patch antenna as shown in fig. 13 that when, the patch antenna can be metal derby；When the antenna element 161 is as schemed
During helical antenna shown in 14, the helical antenna can be formed for metal wire coiling curl, except such as Figure 14
Outside shown rectangular coil shape antenna, the antenna element 161 can also be any other helical antenna, for example, circular spiral shell
Revolve shape antenna etc..
In another example, as shown in figure 15, the antenna module 16 include one along the interstitital texture circumferentially around
Helical antenna.I.e. described antenna module 16 is for one along metal antenna, week of the metal antenna along the interstitital texture 13
To around curl.
As an example, in above-mentioned example, the material of the antenna module 16 can include but are not limited to copper, aluminium, nickel,
It is more than one or both of gold, silver, tin, titanium；Wherein, the antenna module 16 can pass through physical gas-phase deposition
(PVD), one kind in chemical vapor deposition method (CVD), sputtering, plating or chemical plating is prepared.
As an example, the re-wiring layer 15 includes：Insulating layer 151, the insulating layer 151 are located at the capsulation material
The second surface of layer 14；At least one layer of metal line layer 152, the metal line layer 152 are located in the insulating layer 151；Under convex block
Metal layer 153, the Underbump metallization layer 153 are located at surface of the insulating layer 151 away from the capsulation material layer 14, and with
The metal line layer 152 is electrically connected.
As an example, the material of the metal line layer 152 can be but be not limited only to copper, aluminium, nickel, only, silver or titanium in
A kind of material or two or more combined materials, and it is described that the techniques such as PVD, CVD, sputtering, plating or chemical plating can be used to be formed
Metal line layer 152.The material of the insulating layer 121 can be low k dielectric, specifically, the material of the insulating layer 151 can
With including a kind of material in epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass, and can adopt
The insulating layer 151 is formed with techniques such as spin coating, CVD, plasma enhanced CVDs.
As an example, as shown in figure 17, the fan-out-type semiconductor package with antenna module further includes interconnection
Structure 18, the interconnection structure 18 between the antenna module 16 and the re-wiring layer 15, and with the antenna sets
Part 16 and the re-wiring layer 15 are electrically connected.The material of the interconnection structure 18 can be but be not limited only to copper, aluminium, nickel, only,
Silver or a kind of material in titanium or two or more combined materials.
In one example, the soldered ball convex block 17 includes：Metal column, it is remote that the metal column is located at the re-wiring layer 15
It is electrically connected from the surface of the capsulation material layer 14, and with the re-wiring layer 15；Soldered ball, the soldered ball are located at the metal
The surface of the remote capsulation material layer 14 of column.
In another example, as shown in FIG. 16 and 17, the soldered ball convex block 17 is soldered ball.
In conclusion fan-out-type semiconductor package with antenna module of the present invention and preparation method thereof, described
Fan-out-type semiconductor package with antenna module includes：Semiconductor chip；Capsulation material layer, including the first opposite table
Face and second surface, the capsulation material layer plastic packaging expose the semiconductor chip in the periphery of the semiconductor chip
Front；Interstitital texture, in the capsulation material layer, and positioned at semiconductor chip periphery；The interstitital texture pair
Loss is lost less than the capsulation material layer caused by aerial signal caused by aerial signal；Antenna module, positioned at the modeling
The first surface of closure material layer, and orthographic projection of the antenna module in the interstitital texture is fully located at the interstitital texture
On；Re-wiring layer, is electrically connected positioned at the second surface of the capsulation material layer, and with the semiconductor chip；Solder projection,
On surface of the re-wiring layer away from the capsulation material layer, and it is electrically connected with the re-wiring layer.The present invention
The fan-out-type semiconductor package with antenna module by the capsulation material layer below antenna module set to day
Loss is less than the interstitital texture that the capsulation material layer is lost caused by aerial signal caused by line signal, can effectively reduce
Loss to aerial signal, so as to significantly improve the performance of device.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (15)
- A kind of 1. fan-out-type semiconductor package with antenna module, it is characterised in that the fan with antenna module Going out type semiconductor package includes：Semiconductor chip；Capsulation material layer, including opposite first surface and second surface, the capsulation material layer plastic packaging is in the semiconductor core The periphery of piece, and expose the front of the semiconductor chip；Interstitital texture, in the capsulation material layer, and positioned at semiconductor chip periphery；The interstitital texture is to antenna Loss is lost less than the capsulation material layer caused by aerial signal caused by signal；Antenna module, positioned at the first surface of the capsulation material layer, and the antenna module in the interstitital texture just Projection is fully located in the interstitital texture；Re-wiring layer, is electrically connected positioned at the second surface of the capsulation material layer, and with the semiconductor chip；Solder projection, on surface of the re-wiring layer away from the capsulation material layer, and with the re-wiring layer It is electrically connected.
- 2. fan-out-type antenna packages structure according to claim 1, it is characterised in that the semiconductor chip includes：Bare chip；Contact pad, is electrically connected on the bare chip, and with the bare chip；Wherein, the table where the contact pad Face is the front of the semiconductor chip.
- 3. the fan-out-type semiconductor package according to claim 1 with antenna module, it is characterised in that described to fill out Filling structure includes：Glass-filled structure, silicon interstitital texture, 5880 interstitital textures of Roger, high molecular material interstitital texture or multiple Condensation material interstitital texture.
- 4. the fan-out-type semiconductor package according to claim 1 with antenna module, it is characterised in that described to fill out It is loop configuration to fill structure, and the interstitital texture is surrounded on the semiconductor chip periphery, and has with the semiconductor chip Spacing.
- 5. the fan-out-type semiconductor package according to claim 4 with antenna module, it is characterised in that the day Line component includes several antenna elements, several described antenna elements are filled out in the first surface of the capsulation material layer described in Fill the circumferentially-spaced arrangement of structure.
- 6. the fan-out-type semiconductor package according to claim 5 with antenna module, it is characterised in that the day Line unit includes patch antenna or helical antenna.
- 7. the fan-out-type semiconductor package according to claim 4 with antenna module, it is characterised in that the day Line component include one along the interstitital texture circumferentially around helical antenna.
- 8. the fan-out-type semiconductor package according to claim 1 with antenna module, it is characterised in that the tool The fan-out-type semiconductor package for having antenna module further includes interconnection structure, the interconnection structure be located at the antenna module with Between the re-wiring layer, and it is electrically connected with the antenna module and the re-wiring layer.
- 9. the fan-out-type semiconductor package according to claim 1 with antenna module, it is characterised in that described heavy New route layer includes：Insulating layer, positioned at the second surface of the capsulation material layer；At least one layer of metal line layer, in the insulating layer；Underbump metallization layer, is electrically connected positioned at surface of the insulating layer away from the capsulation material layer, and with the metal line layer Connect.
- 10. a kind of preparation method of the fan-out-type semiconductor package with antenna module, it is characterised in that described that there is day The preparation method of the fan-out-type semiconductor package of line component includes the following steps：1) carrier is provided, peel ply is formed in the upper surface of the carrier；2) semiconductor chip is provided, the semiconductor chip face down is installed in the surface of the peel ply；3) interstitital texture is provided, the interstitital texture is installed in the surface of the peel ply, the interstitital texture is located at institute State the periphery of semiconductor chip；4) capsulation material layer is formed in the surface of the peel ply, the capsulation material layer is by the semiconductor chip and described fills out Fill structure plastic packaging；The capsulation material layer includes opposite first surface and second surface, the second table of the capsulation material layer Face is in contact with the peel ply；The interstitital texture is lost less than the capsulation material layer caused by aerial signal to antenna Loss caused by signal；5) carrier and the peel ply are removed；6) re-wiring layer, the re-wiring layer and the semiconductor chip are formed in the second surface of the capsulation material layer It is electrically connected；7) in the capsulation material layer first surface formed antenna module, the antenna module in the interstitital texture just Projection is fully located in the interstitital texture；8) form soldered ball convex block in surface of the re-wiring layer away from the capsulation material layer, the soldered ball convex block with it is described Re-wiring layer is electrically connected.
- 11. the preparation method of the fan-out-type semiconductor package according to claim 10 with antenna module, it is special Sign is that the interstitital texture being supplied in step 3) includes：Glass-filled structure, silicon interstitital texture, Roger 5880 are filled out Fill structure, high molecular material interstitital texture or composite material interstitital texture.
- 12. the preparation method of the fan-out-type semiconductor package according to claim 10 with antenna module, it is special Sign is that the interstitital texture provided in step 3) is loop configuration, and the interstitital texture is surrounded on the semiconductor chip Periphery, and there is spacing with the semiconductor chip.
- 13. the preparation method of the fan-out-type semiconductor package according to claim 10 with antenna module, it is special Sign is, in step 7), the specific method that antenna module is formed in the first surface of the capsulation material layer is：Several antenna elements along the circumferentially-spaced arrangement of the interstitital texture are formed in the first surface of the capsulation material layer, Several described antenna elements are collectively as the antenna module；Wherein, the antenna element includes patch antenna or helical form Antenna.
- 14. the preparation method of the fan-out-type semiconductor package according to claim 10 with antenna module, it is special Sign is, in step 7), the specific method that antenna module is formed in the first surface of the capsulation material layer is：In the capsulation material layer first surface formed one along the interstitital texture circumferentially around helical antenna as institute State antenna module.
- 15. the preparation method of the fan-out-type semiconductor package according to claim 10 with antenna module, it is special Sign is, following steps are further included between step 6) and step 7)：Filled in being formed in the interstitital texture described in up/down perforation The interconnection structure of structure and the capsulation material layer, the interconnection structure are electrically connected with the re-wiring layer；Shape in step 7) Into the antenna be electrically connected with the interconnection structure.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711282005.8A CN107910312A (en) | 2017-12-07 | 2017-12-07 | Fan-out-type semiconductor package with antenna module and preparation method thereof |
| US16/212,487 US10770394B2 (en) | 2017-12-07 | 2018-12-06 | Fan-out semiconductor packaging structure with antenna module and method making the same |
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| CN201711282005.8A CN107910312A (en) | 2017-12-07 | 2017-12-07 | Fan-out-type semiconductor package with antenna module and preparation method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3557608A1 (en) * | 2018-04-19 | 2019-10-23 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Packaged integrated circuit with interposing functionality and method for manufacturing such a packaged integrated circuit |
| CN111668116A (en) * | 2019-03-08 | 2020-09-15 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method |
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| US20190326188A1 (en) * | 2018-04-19 | 2019-10-24 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Packaged Integrated Circuit With Interposing Functionality and Method for Manufacturing Such a Packaged Integrated Circuit |
| CN110391194A (en) * | 2018-04-19 | 2019-10-29 | 奥特斯奥地利科技与系统技术有限公司 | Encapsulation integrated circuit with interpolation functions and the method for manufacturing this encapsulation integrated circuit |
| US11605569B2 (en) * | 2018-04-19 | 2023-03-14 | AT&SAustria Technologie & Systemtechnik AG | Packaged integrated circuit with interposing functionality and method for manufacturing such a packaged integrated circuit |
| CN111668116A (en) * | 2019-03-08 | 2020-09-15 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method |
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