CN117242555A

CN117242555A - Fan-out chip packaging structure and preparation method

Info

Publication number: CN117242555A
Application number: CN202180097862.9A
Authority: CN
Inventors: 蔡崇宣; 赵南; 洪瑞斌
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-08-11
Filing date: 2021-08-11
Publication date: 2023-12-15
Also published as: WO2023015480A1

Abstract

The embodiment of the application provides a fan-out type packaging structure and a preparation method thereof, wherein the fan-out type packaging structure comprises a first chip and a first rewiring layer; the first surface of the first chip is provided with a plurality of conductive posts, and the first chip is arranged on the first surface of the first rewiring layer through the plurality of conductive posts; the gaps of the plurality of conductive posts are filled with insulating materials, the insulating materials are arranged between the first surface of the first chip and the first surface of the first rewiring layer, orthographic projection of the insulating materials to the first chip is positioned in the boundary range of the first chip, and the boundary of orthographic projection is a preset distance from the boundary of the first chip; the side edges of the first chip and the parts of the first surface of the first chip, which are not covered by the insulating material and the conductive posts, are wrapped by the plastic packaging material deposited on the first surface of the first rewiring layer, so that support and protection can be provided for the edge area of the first chip, delamination or fracture of the first chip is avoided, and the reliability of the chip is improved.

Description

Fan-out chip packaging structure and preparation method

Technical Field

The embodiment of the application relates to the technical field of semiconductor packaging, in particular to a fan-out type chip packaging structure and a preparation method.

Background

With the development of communication, artificial intelligence and other technologies, a great deal of data flow and transfer demands are increasing, and hardware supporting applications such as 5G applications, artificial intelligence and the like is required to have functions of high-speed computing, low latency, multiple bandwidths, system integration and the like. In order to meet the functional requirements of hardware devices, it is proposed in the industry to package a plurality of chips together by using a carrier-free package structure to improve the electrical performance of the packaged chips. The carrier-free Package structure includes a Fan-in Package structure (Fan-in Wafer Level Package), a Fan-out Package structure (Fan-out Package), and the like. The fan-out package structure may provide a greater number of I/O connection points than the fan-in package structure, becoming the dominant direction.

In the current fan-out package structure, a plurality of chips to be packaged are required to be placed on a carrier plate with temporary bonding glue for wafer reconstruction. In the process of wafer reconstruction or in the process of reliability test, warpage of chips is usually caused, delamination or fracture is caused in a region with larger stress between every two chips, and due to the fact that a circuit for communicating a plurality of chips is arranged in the region with larger stress between every two chips, the circuit is broken due to the fracture in the region, so that connection failure between the chips is caused, and further, the function of the chips is disabled. Thus, how to improve the reliability of the packaged chip becomes a problem to be solved.

Disclosure of Invention

The fan-out type packaging structure and the preparation method provided by the application can improve the reliability of the packaged chip.

In order to achieve the above purpose, the application adopts the following technical scheme:

in a first aspect, an embodiment of the present application provides a fan-out package structure, including: a first chip and a first rewiring layer; the first surface of the first chip is provided with a plurality of conductive posts, and the first chip is arranged on the first surface of the first rewiring layer through the plurality of conductive posts; the gaps of the plurality of conductive columns are filled with insulating materials, the insulating materials are arranged between the first surface of the first chip and the first surface of the first rewiring layer, orthographic projection of the insulating materials to the first chip is located in the boundary range of the first chip, and the boundary of the orthographic projection and the boundary of the first chip have a preset distance; the side edges of the first chip and the parts of the first surface of the first chip not covered by the insulating material and the conductive posts are wrapped by plastic packaging materials deposited on the first surface of the first rewiring layer.

According to the fan-out type packaging structure provided by the embodiment of the application, a plurality of first chips can be packaged in the same packaging body, and the plurality of first chips can be arranged in parallel at intervals in the packaging body. It should be noted that the plurality of first chips refer to chips that are manufactured by using a synchronous process and are packaged in the same package. The plurality of first chips may be different types of chips. For example, one of the first chips may be a processor and the other first chip may be a transistor.

According to the embodiment of the application, the orthographic projection of the insulating material to the first chip is arranged in the boundary range of the first chip, and the boundary of the orthographic projection and the boundary of the first chip have a preset distance, so that the part of the first surface of the first chip, which is close to the edge of the first chip, is not deposited with the insulating material, and the part is exposed in the packaging process. When the plastic packaging material is arranged outside the first chips, the plastic packaging material can wrap the side edges and the corners of the first chips in the plastic packaging material, so that the thickness of the plastic packaging material between every two first chips can be increased, support and protection are provided for the area between every two first chips, the area between every two first chips is prevented from being broken along the thickness direction of the first chips, and the reliability of chip packaging is improved.

The insulating material provided by the embodiment of the application can be an organic polymer material, including but not limited to: polyimide, polybenzazole, benzocyclobutene, or epoxy molding materials, etc.

The plastic packaging material provided by the embodiment of the application can be one or a combination of more of epoxy resin, polyethylene, polypropylene, polyolefin, polyamide and polyurethane.

Based on the first aspect, in a possible implementation manner, a surface of the plurality of conductive pillars, which is in contact with the first redistribution layer, is located at the same level as a surface of the insulating material, which is in contact with the first redistribution layer.

By arranging the surfaces of the conductive posts and the surfaces of the insulating material on the same horizontal plane, the plane formed by the surfaces of the conductive posts and the surfaces of the insulating material can be smoother, thereby being more beneficial to realizing subsequent manufacturing processes.

Based on the first aspect, in a possible implementation manner, a second surface opposite to the first surface in the first redistribution layer is provided with a plurality of bumps, and the terminals of the first chip are communicated with at least part of the bumps in the plurality of bumps through the plurality of conductive pillars and the first redistribution layer.

The fan-out type packaging structure provided by the embodiment of the application can be various types of packaging structures.

In a first possible package structure, the fan-out package structure is a wafer level chip scale package. In this possible implementation, the molding material also covers a second surface of the first chip opposite the first surface.

Further, the wafer level chip scale package may further include a build-up package structure. In this possible implementation, the fan-out package structure further includes a second chip; the second chip is arranged on one side, away from the first rewiring layer, of the first chip.

In the case that the fan-out package structure is a stacked package structure, the fan-out package structure further includes a second redistribution layer, where the second redistribution layer is disposed on a side of the plastic package material away from the first chip; the second chip is arranged on one side of the second rerouting layer far away from the first rerouting layer through a plurality of bonding pads.

In the case that the fan-out package structure is a stacked package structure, a through hole for communicating the first redistribution layer and the second redistribution layer is further formed in a region of the plastic package material away from the first chip; the second chip is connected with the first chip through the second redistribution layer, the through hole and the first redistribution layer.

In a second possible package structure, the fan-out package structure is a board level chip scale package. In this possible implementation, the fan-out package structure further comprises a printed circuit board; the second surface of the rewiring layer is arranged on the first surface of the printed circuit board through the plurality of bumps.

In the case that the fan-out package structure is a board-level chip-scale package structure, in one possible implementation manner, the fan-out package structure further includes a heat sink; the heat sink is disposed over the second surface of the first chip.

Based on the first aspect, the first redistribution layer provided by the embodiment of the application includes at least one layer of patterned conductive line and an insulating material for isolating the patterned conductive line, in addition, the first redistribution layer is further provided with a via hole filled with the conductive material, and the first chip is led to the second surface from the first surface of the first redistribution layer through the conductive line on the first redistribution layer and the via hole arranged on the first redistribution layer so as to be communicated with the plurality of bumps.

Based on the first aspect, the second redistribution layer provided by the embodiment of the application comprises at least one layer of patterned conductive line and an insulating material for isolating the patterned conductive line, in addition, the second redistribution layer is further provided with a via hole filled with the conductive material, and the second chip is communicated with the first chip through the conductive line on the second redistribution layer, the via hole arranged on the second redistribution layer, the through hole and the first redistribution layer.

In a second aspect, an embodiment of the present application provides an electronic device, which includes the fan-out package structure according to the first aspect.

The chips packaged by the fan-out package structure may include, but are not limited to: system on chip (soc), memory (Memory), discrete devices, application processing chips (Application Processor, AP), microelectromechanical systems (Micro-Electro-Mechanical System, MEMS), microwave radio frequency chips, application specific integrated circuits (ApplicationSpecific Integrated Circuit, ASIC for short), and the like. The application processing chip or application specific integrated circuit may be a central processing unit (Central Processing Unit, CPU), an image processor (Graphics Processing Unit, GPU), an artificial intelligence processor, such as a neural network processor (Network Processing Unit, NPU), etc. in a specific application. The Memory may be a cache, random access Memory (Random Access Memory, RAM), read Only Memory (ROM), or other Memory. Discrete devices may include, for example, but are not limited to, field effect transistors, bipolar transistors, integrated operational amplifiers, and the like. The electronic device may also be an integrated circuit product, where the integrated circuit product may further include other integrated circuits in addition to the fan-out package structure described in the embodiments of the present application, so that the fan-out package structure and other integrated circuits shown in the embodiments of the present application cooperate with each other to implement various circuit functions.

In a third aspect, an embodiment of the present application provides a method for manufacturing a fan-out package structure, where the method includes: forming a plurality of conductive pillars on a first surface of a first chip; depositing an insulating material on the first surface of the first chip, wherein the insulating material fills gaps of the conductive posts, orthographic projection of the insulating material to the first chip is positioned in the boundary range of the first chip, and the orthographic projection boundary is a preset distance from the boundary of the first chip; forming a plastic package material on the first chip, wherein the plastic package material wraps the side edge of the first chip and the exposed part of the first surface of the first chip; and forming a first rewiring layer on the plane formed by the conductive posts, the insulating material and the plastic packaging material.

Based on the third aspect, in a possible implementation manner, the plastic package material further wraps a second surface opposite to the first surface in the first chip.

Based on the third aspect, in a possible implementation manner, the preparation method further includes: forming a second redistribution layer on one side of the plastic packaging material away from the first redistribution layer; forming a plurality of bonding pads on one side of the second redistribution layer away from the plastic packaging material; and disposing a second chip over the second redistribution layer through the plurality of pads.

Based on the third aspect, in a possible implementation manner, the preparation method further includes: a through hole for communicating the first rewiring layer and the second rewiring layer is formed in the area, away from the chip, of the plastic packaging material; the second chip is communicated with the first chip through the first rerouting layer, the through hole and the second rerouting layer.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments of the present application will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a fan-out package structure according to an embodiment of the present application;

FIG. 2 is a top view of the fan-out package structure shown in FIG. 1, taken along AA', according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a fan-out package structure in the conventional art;

FIG. 4 is a top view of the fan-out package structure shown in FIG. 3 with the rewiring layer removed;

fig. 5 is a schematic diagram of another structure of a fan-out package according to an embodiment of the present application;

fig. 6 is a schematic diagram of another structure of a fan-out package according to an embodiment of the present application;

fig. 7 is a schematic diagram of another structure of a fan-out package according to an embodiment of the present application;

fig. 8 is a flowchart of a method for manufacturing the fan-out package structure shown in fig. 1 according to an embodiment of the present application;

fig. 9A to 9G are schematic views of structures during the fabrication of the fan-out package structure shown in fig. 1.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terms "first," "second," and the like, herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

In embodiments of the application, words such as "exemplary" or "such as" are used to mean examples, illustrations, or descriptions. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion. In the description of the embodiments of the present application, unless otherwise indicated, the meaning of "a plurality" means two or more. For example, a plurality of chips refers to two or more chips.

The fan-out type packaging structure provided by the embodiment of the application can package a plurality of chips in the same packaging body. The chips can be arranged at horizontal intervals, and each chip is connected with the rest chips, a public power supply and a public ground through the conductive posts and the rewiring layers which are arranged on the chips so as to realize signal communication among the chips. The chip in the embodiment of the application may be a bare chip (Die), a chip formed by simply packaging the bare chip and other chips or components (active devices or passive devices, etc.), or a chip packaging structure formed by packaging, which is not limited herein. The fan-out package structure according to the embodiment of the present application will be described below with reference to fig. 1 by taking an example in which two chips disposed horizontally are included in the same package.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a fan-out package structure according to an embodiment of the application. In fig. 1, a fan-out package structure 100 includes a chip 10, a chip 11, a rewiring layer 20, a plurality of conductive pillars 30, and a plurality of conductive pillars 31. The chip 10 includes opposing surfaces S1 and S2, with a plurality of terminals formed on the surface S1. The plurality of terminals on the chip 10 are connected to the chip 11, the common power source, and the common ground through the conductive posts 30 and the rewiring layer 20. The chip 11 includes opposed surfaces S3 and S4, and the surface S3 has a plurality of terminals formed thereon. The plurality of terminals on the chip 11 are connected to the chip 10, the common power source, and the common ground through the conductive posts 31 and the rewiring layer 20. The plurality of conductive pillars 30 are disposed between the chip 10 and the wiring layer 20, and the lead-out terminal of the chip 10 is led out to the surface D1 of the redistribution layer 20 through the plurality of conductive pillars 30; the plurality of conductive pillars 31 are disposed between the chip 11 and the wiring layer 20, and the lead-out terminal of the chip 11 is led out to the surface D1 of the redistribution layer 20 through the plurality of conductive pillars 31. The terminals on the surface S1 of the chip 10 and the terminals on the surface S3 of the chip 11 may be one of pads, micro-bumps (micro-bumps), and copper stud bumps (Cu bumps).

The number of the conductive posts 30 may be the same as the number of the terminals of the chips 10, that is, each of the terminals of the chips 10 is provided with one conductive post 30; the number of conductive studs 31 may be the same as the number of terminals of the chips 11, i.e. one conductive stud 31 is provided for each terminal of the chip 11. The conductive pillars 30 and 31 may be metal pillars formed of a metal material, such as copper pillars (copper pillars), aluminum pillars, silver pillars, or palladium pillars, or may be pillars formed of other conductive materials, which is not limited in the embodiment of the present application. Gaps are formed between the plurality of conductive posts 30, and gaps are also formed between the plurality of conductive posts 31. The gaps of the plurality of conductive pillars 30 and the gaps of the plurality of conductive pillars 31 are filled with an insulating material 40, and the insulating material 40 may be an organic polymer material. The organic polymeric material may include, but is not limited to: polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), or epoxy molding compound (Epoxy Molding Compound, EMC), and the like.

Insulating material 40 is deposited on surface S1 of chip 10 and surface S3 of chip 11, respectively. The height of the insulating material 40 is the same as the height of the conductive pillars 30 and 31, respectively, in the direction x shown in fig. 1, i.e., the thickness direction of the chip. In addition, the insulating material 40 deposited on the surface S1 of the chip 10, the first orthographic projection onto the surface S1 of the chip 10 is located within the boundary range of the chip 10, and the boundary of the first orthographic projection has a first preset distance from the boundary of the chip 10; the insulating material 40 deposited on the surface S3 of the chip 11, the second orthographic projection onto the surface S3 of the chip 11 is located within the boundary of the chip 11, and the boundary of the second orthographic projection is also a second predetermined distance from the boundary of the chip 11. The first preset distance and the second preset distance may be the same or different, and are set according to the requirements of the application scene. As shown in fig. 2, fig. 2 is a top view of the fan-out package structure 100 shown in fig. 1, taken along AA'. As can be seen in fig. 2, the area A1 of the surface S1 of the chip 10 near the edge of the chip 10 is not deposited with the insulating material 40, and the area A2 of the surface S3 of the chip 11 near the edge of the chip 11 is not deposited with the insulating material 40. Thus, the fan-out package structure 300 exposes the sides of the chips 10 and 11, the portion of the surface S1 of the chip 10 near the edge, and the portion of the surface S3 of the chip 20 near the edge before the plastic package material is not provided.

In the fan-out package structure shown in fig. 1, a plastic molding material 50 is further included. The molding material may include, for example, one or more combinations of epoxy (Epoxy Molding Compound, EMC), polyethylene, polypropylene, polyolefin, polyamide, polyurethane. After the fan-out package structure 100 deposits the molding compound 50, the molding compound 50 encapsulates the portions of the chip 10 and the chip 11 that are not covered by the insulating material 40, the conductive pillars 30, and the conductive pillars 31.

In conventional fan-out First Chip (Chip-First) packaging technology, the insulating material 40 is generally completely covered on the surface S1 of the Chip 10 and the surface S3 of the Chip 11, the plastic package material 50 wraps the surface S2 and the side of the Chip 10, the plastic package material 50 also wraps the surface S4 and the side of the Chip 11, as shown in fig. 3 and 4, fig. 3 is a schematic diagram of a fan-out package structure in the conventional technology, and fig. 4 is a top view of the fan-out package structure shown in fig. 3 after the redistribution layer 20 is removed. In a fan-out package structure comprising multiple chips, the area between each two chips has a large stress. When the package structure shown in fig. 3 is used, the edge of the molding material 50 is weak due to the influence of the etching process in the process, that is, the portion of the molding material 50 disposed between the chip 10 and the chip 11 is weak. The weak molding compound 50 is insufficient to support the stress of the middle region of the chip 10 and the chip 11, resulting in the breakage of the region between the chip 10 and the chip 11 in the x-direction. As can be seen from fig. 3, when the region between the chip 10 and the chip 11 breaks in the x-direction, the H region of the rewiring layer 20 is also likely to break. Since the H region of the rewiring layer 20 is provided with conductive lines for connecting the chips 10 and 11 and connecting the chips 10 and 11 with a common power source and a common ground, the H region of the wiring layer 20 breaks to cause the conductive lines to break, thereby causing failure of connection between the chips, connection between the chips and the common power source, or connection between the chips and the common ground, and further causing failure of chip functions.

The embodiment of the present application does not deposit insulating material 40 at the portion of surface S1 of chip 10 near the edge of chip 10 and the portion of surface S3 of chip 11 near the edge of chip 11, which is exposed during the packaging process. When the plastic packaging material 50 is arranged outside the chip 1, the plastic packaging material 50 can wrap the side edges and corners of the chip 10 and the chip 11 in the plastic packaging material 50, so that the thickness of the plastic packaging material 50 between the chip 10 and the chip 11 can be increased, the area between the chip 10 and the chip 11 is supported and protected, the area between the chip 10 and the chip 11 is prevented from being broken along the x direction, and the reliability of chip packaging is improved.

With continued reference to fig. 1, in fig. 1, the redistribution layer 20 may include at least one layer of patterned conductive lines and an insulating material for isolating the patterned conductive lines, the conductive material used to form the patterned conductive lines may be one or more of copper (Cu), silver (Ag), aluminum (Al), and the like, and the conductive material used to form the patterned conductive lines may also be oxide Niu Xi (ITO), graphite, graphene, and the like; the insulating material may be an inorganic insulating material, an organic insulating material, or the like. The rewiring layer 20 may also be provided with vias (Via) that may include, but are not limited to: through holes or buried holes, etc. The vias may be filled with a conductive material. Further, pads (Pad) 21 are further disposed on the surface D2 of the redistribution layer 20, and a plurality of bumps 60 are disposed on each Pad 21, and materials of the bumps 60 may include, but are not limited to: tin materials or tin-silver mixed materials, and the like. The lead-out terminal of the chip 10 is led from the surface D1 of the rewiring layer 20 to the surface D2 through the conductive line on the rewiring layer 20 and the via hole provided on the rewiring layer 20, so as to be communicated with a part of the bump 60; the terminals of the chip 11 are led from the surface D1 of the rewiring layer 20 to the surface D2 through the conductive traces on the rewiring layer 20 and the vias provided on the rewiring layer 20, so as to communicate with another part of the bumps 60. The communication between the chip 10 and the chip 20 can also be achieved by wiring connections on the rewiring layer 20.

In the fan-out package structure 100 shown in fig. 1, two chips arranged in parallel and spaced apart are shown packaged in the same package. The Fan-Out package structure according to the embodiments of the present application may also be a Fan-Out package stack (FO-PoP, fan Out-Package on Package) package structure. Referring to fig. 5, fig. 5 is a schematic diagram of a fan-out package structure 200 according to an embodiment of the application. In fig. 5, the fan-out type package structure 200 includes a chip 12 in addition to the chips 10 and 11 disposed at a horizontal interval. In the direction x shown in fig. 5, the chip 12 is disposed above the chip 10 and the chip 11. Specifically, the fan-out package structure 200 further includes the rewiring layer 70 in addition to the fan-out package structure 100 shown in fig. 1. The re-wiring layer 70 may include at least one layer of patterned conductive lines and an insulating material isolating the patterned conductive lines, the conductive material for forming the patterned conductive lines may be a metal such as one or more of copper (Cu), silver (Ag), aluminum (Al), etc., and the conductive material for forming the patterned conductive lines may also be oxide Niu Xi (ITO), graphite, graphene, etc.; the insulating material may be an inorganic insulating material, an organic insulating material, or the like. The redistribution layer 70 is disposed over the molding material 50. A plurality of pads (Pad) 71 are further provided on the rewiring layer 70, and the terminals of the chip 12 are soldered with the pads 71 so that the terminals of the chip 12 are led out to the surface of the rewiring layer 70. In addition, along the direction x shown in fig. 5, a plurality of through holes 51 penetrating the upper surface and the lower surface of the molding material 50 are further provided on the molding material 50, and the through holes 51 are filled with a conductive material, and the through holes 51 are used for communicating the re-wiring layer 20 and the re-wiring layer 70. The lead-out terminal of the chip 12 is led to the surface D1 of the rewiring layer 20 through the conductive line on the rewiring layer 70 and the through hole 51, and then is communicated with the chip 10 and the chip 11 through the conductive line arranged on the rewiring layer 20, so that signal communication between the chip 12 and the chip 10 and between the chip 11 is realized.

In the fan-out package structure shown in fig. 4, one chip is stacked on top of the chips 10 and 11; in other possible implementations, a plurality of chips may be stacked sequentially on the chip 10 and the chip 11, and the chips are communicated through the through holes provided on the insulating layer, which is not particularly limited in the embodiment of the present application.

The Fan-Out package structure shown in fig. 1 and 5 is a Fan-Out wafer level chip size package (FO-WLCSP, fan Out-Wafe Level Chip Scale Package). The Fan-Out package structure shown in the embodiments of the present application may also be a Fan-Out board level package (FO-PLP, fan Out-Panel Level Package). In particular, the board level package may be a flip chip ball grid array (FCBGA, flip Chip Ball Grid Array). Referring to fig. 6, fig. 6 is a schematic diagram of a fan-out type board level package 300 according to an embodiment of the application. In fig. 6, the fan-out type board level package 300 includes a printed circuit board (PCB, print Circuit Board) 80 in addition to the fan-out type package structure 100 shown in fig. 1. The PCB80 may include a plurality of wiring layers. The surface P1 of the PCB80, the surface P2 opposite to the surface P1, and the intermediate wiring layer between the surface P1 and the surface P2 are all provided with patterned conductive traces. The PCB80 is also provided with vias (Via) that may include, but are not limited to: through holes or buried holes, etc. The conductive traces on surface P1, the conductive traces on the intermediate routing layer, and the conductive traces on surface P2 of PCB80 may communicate through vias. In addition, the surface P2 of the PCB80 is also provided with a ball grid array 81. The fan-out package structure 100 is attached to the surface P1 of the PCB80 through the bump 60, and then the terminals of the chip 10 and the terminals of the chip 11 packaged in the fan-out package structure 100 are led to the ball grid array 81 on the surface P2 of the PCB80 through the bump 60.

Further, on the basis of the fan-out type board level package structure 300 shown in fig. 6, the fan-out type board level package structure provided in the embodiment of the present application may further include a heat sink 90. At this time, the plastic package material 50 is not disposed on the surface S2 of the chip 10 and the surface S4 of the chip 11, the heat dissipation material is coated on the surface S2 of the chip 10 and the surface S4 of the chip 11, the heat dissipation material 91 may be coated on the area of the PCB80 where the fan-out package structure 100 is not disposed, and the heat sink 90 is attached to the surface S2 of the chip 10, the surface S4 of the chip 11, and the surface P1 of the PCB by the heat dissipation material 91. During operation, the chips 10 and 11 may dissipate heat through the heat sink. In addition, the heat sink 90 may also provide physical protection for the fan-out package structure 100.

The embodiment of the application also comprises electronic equipment, wherein the electronic equipment comprises the fan-out type packaging structure shown in each embodiment. The chips packaged by the fan-out package structure may include, but are not limited to: system on chip (soc), memory (Memory), discrete devices, application processing chips (Application Processor, AP), microelectromechanical systems (Micro-Electro-Mechanical System, MEMS), microwave radio frequency chips, application specific integrated circuits (ApplicationSpecific Integrated Circuit, ASIC for short), and the like. The application processing chip or application specific integrated circuit may be a central processing unit (Central Processing Unit, CPU), an image processor (Graphics Processing Unit, GPU), an artificial intelligence processor, such as a neural network processor (Network Processing Unit, NPU), etc. in a specific application. The Memory may be a cache, random access Memory (Random Access Memory, RAM), read Only Memory (ROM), or other Memory. Discrete devices may include, for example, but are not limited to, field effect transistors, bipolar transistors, integrated operational amplifiers, and the like. For example, when the fan-out package structure shown in fig. 1 or 6 is employed, the chips 10 and 11 packaged in the fan-out package structure may be application processing chips and discrete devices, respectively; for another example, when the fan-out package structure shown in fig. 5 is used, the chip 10 and the chip 11 packaged in the fan-out package structure may be application processing chips and discrete devices, respectively, and the chip 12 may be a memory. The electronic device may also be an integrated circuit product, where the integrated circuit product may further include other integrated circuits in addition to the fan-out package structure described in the embodiments of the present application, so that the fan-out package structure and other integrated circuits shown in the embodiments of the present application cooperate with each other to implement various circuit functions.

Based on the fan-out package structure described in the above embodiments, the embodiment of the present application further provides a method for preparing a fan-out package structure, and the structure of the prepared fan-out package structure is shown in fig. 1, and the process flow for preparing the fan-out package structure is described in detail with reference to the flow 800 shown in fig. 8. The process 800 includes the steps of:

in step 801, conductive pillars 30 are formed at the terminals of the chip 10 to be packaged, and conductive pillars 31 are formed at the terminals of the chip 11 to be packaged.

In the embodiment of the application, the process of forming the conductive pillars 30 at the lead-out ends of the chips 10 is the same as the process of forming the conductive pillars 31 at the lead-out ends of the chips 11. This step is described below by taking a process of forming the conductive pillars 30 at the terminals of the chip 10 as an example.

It is assumed that the surface S1 of the chip 10 is formed with terminals. First, a metal material is deposited on the surface S1 of the chip 10 by a vapor deposition method (e.g., physical vapor deposition or chemical vapor deposition). The metallic material may include, but is not limited to: copper, aluminum, silver, gold, or an alloy of metals. Next, a photoresist is deposited on the surface of the metal material. Then, a portion of the metal material, which does not cover the terminals of the chip 10, is etched using a mask plate, thereby forming conductive pillars 30 on the surface S1 of the chip 10, as shown in fig. 9A. The etching of the metal material may be dry etching or wet etching. Taking the metal material deposited by the chip 10 as copper material as an example, when wet etching is used, etching liquid such as ferric chloride etching liquid or hydrochloric acid-cupric chloride etching liquid can be used to etch the copper material.

To better protect the chip 10, the metal material is etched to avoid partially etching the chip 10 to affect the electrical performance of the chip 10, and in one possible implementation, before depositing the metal material on the surface S1 of the chip 10, another metal material different from the metal material described above may be first deposited on the surface S1 of the chip 10 to form a barrier layer. The etch rate of the barrier layer is slower than the etch rate of the metallic material. For example, when the metal material is a copper material, the material forming the barrier layer may be, for example, a titanium material. When the barrier layer is formed on the chip 10, after etching the metal material in step 801, the exposed barrier layer needs to be further etched.

The process of forming the conductive pillars 31 at the terminals of the chip 11 refers to the process of forming the conductive pillars 30 at the terminals of the chip 10, and will not be described in detail.

At step 802, insulating material 40 is deposited on surface S1 of die 10 and surface S3 of die 11, respectively.

After the conductive pillars 30 are formed at the terminals of the chip 10, an insulating material 40 may be deposited on the surface S1 of the chip 10. The thickness of the insulating material 40 deposited is higher than the height of the conductive pillars 30 along the deposition direction of the insulating material 40. Thus, the insulating material 40 deposited on the surface S1 of the chip 10 also encapsulates the conductive pillars 30. Then, a photoresist is deposited over the insulating material 40, and the insulating material 40 located at the boundary is etched using a reticle such that a position on the surface S1 of the chip 10 at a predetermined distance from the edge of the chip 10 is exposed. After the conductive posts 31 are formed at the terminals of the chip 11, the insulating material 40 may be deposited on the surface S3 of the chip 11 by the same process. Also, a position on the surface S3 of the chip 11 at a predetermined distance from the edge of the chip 11 is exposed. The structure formed after this step is shown in fig. 9B.

In step 803, the chip 10 and the chip 11 are mounted upside down on the carrier board b. The structure formed after this step is shown in fig. 9C.

The material of the carrier plate b may include, but is not limited to: silicon material, glass material, or a mixture thereof, and the carrier b may be of a wafer level or board level size.

In one possible implementation, the surface of the organic polymer 40 on which the chip 10 is deposited is coated with the bonding adhesive a, and the side of the chip 10 coated with the bonding adhesive a is mounted on the carrier board b. Also, a bonding adhesive a is coated on the surface of the organic polymer 40 deposited on the chip 11, and the surface of the chip 11 coated with the bonding adhesive a is mounted on the carrier b. The chip 10 and the chip 11 are arranged side by side at intervals on the carrier plate b.

In another possible implementation, the bonding glue a may be first coated on the surface of the carrier plate b. Then, the chip 10 and the chip 11 are adhered to the carrier board b side by side at a spacing. Wherein, the insulating material 40 deposited on the chip 10 contacts with the bonding glue, and the surface S2 of the chip 10 exposed outside is disposed at one side far away from the carrier b; the insulating material 40 deposited on the chip 11 is in contact with the bonding glue a, and the surface S4 of the chip 11 exposed to the outside is disposed on the side away from the carrier plate b.

In step 804, a molding material is deposited on the surface of the carrier b, the surface S2 of the chip 11, and the surface S4 of the chip 12. The structure formed after this step is shown in fig. 9D.

As can be seen in fig. 9D, the surface S2, the side surface, and the portion of the surface S1 of the chip 10 not covered by the insulating material 40 are all wrapped with the molding material 50; the surface S4, the side surfaces and the portions of the surface S3 of the chip 11 not covered by the insulating material 40 are all covered with the molding material 50. Likewise, the space between the chip 10 and the chip 11 is filled with the molding material 50. Thus, the thickness of the molding material 50 between the chip 10 and the chip 11 can be increased to provide support and protection for the area between the chip 10 and the chip 11, avoid breakage of the area between the chip 10 and the chip 11 in the x-direction, and improve the reliability of the chip package.

In step 805, carrier b is removed from chip 10 and chip 11. The structure of the carrier b after removal is shown in fig. 9E.

In step 806, a planarization process is performed on the side of the package structure where the bonding adhesive is disposed, so as to expose the conductive pillars 30 and 31. The structure formed after the planarization process of the package structure is shown in fig. 9F.

After step 806, the bond paste a is etched away. The conductive pillars 30, 31 and the insulating material 40 are exposed on the sides away from the chips 10 and 11.

In step 807, the redistribution layer 20 is formed on the exposed surfaces formed by the conductive pillars 30, conductive pillars 31, insulating material 40, and molding material 50.

In this step, the redistribution layer 20 may be prepared on the exposed surface formed by the conductive pillars 30, the conductive pillars 31, the insulating material 40, and the molding material 50 using standard processes such as photolithography, development, and etching. The rewiring layer 20 is a double-sided wiring, and a plurality of intermediate wiring layers are further provided between the two sides of the rewiring layer 20. The wiring layers are communicated through the through holes.

At step 808, a plurality of pads 21 are formed on a side of the redistribution layer 20 remote from the chip 10 and the chip 11. The package structure after the pads 21 are provided is shown in fig. 9G.

The conductive pillars 30 and 31 are connected to the pads 21 through the multi-layered wiring layers and vias on the rewiring layer 20, respectively, via step 808. The material of the pad 21 may be copper, aluminum, gold, a mixed metal material, or the like.

In step 809, bumps are formed on the plurality of pads 21. The bump may be a tin bump.

Through steps 801-809, the fan-out wafer level package structure shown in fig. 1 can be formed.

Furthermore, on the basis of the fan-out wafer level packaging structure shown in fig. 1, the fan-out wafer level packaging structure can be further subjected to board level packaging. Steps 810-816 may also be included when board level packaging is desired. At step 810, the PCB is first prepared using standard processes. The PCB is double-sided wiring, and a plurality of middle wiring layers are arranged between two sides of the PCB. The wiring layers are communicated through the through holes. In step 811, a ball grid array, which may be tin, is pre-soldered to the surface P2 of the PCB. In step 812, the bump 60 on the fan-out package structure 100 shown in fig. 1 is attached to the surface P1 of the PCB. Thus, the terminals of the chip 10 and the chip 11 packaged in the fan-out package structure 100 are led to the ball grid array on the surface P2 of the PCB through the bumps 60. Step 813 etches the molding compound 50 over the chip 10 and the chip 11 to expose the wafer back of the chip 10 and the chip 11. At step 815, a heat sink material is deposited over the exposed wafer backs of chips 10 and 11 and areas of the PCB where the chips are not located. In step 816, the heat sink 90 is attached to the surface of the chip 10 with the heat sink material 91, the surface of the chip 11, and the surface of the PCB. The board level package structure 300 prepared through steps 810-816 is shown in fig. 7.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims

A fan-out type packaging structure is characterized by comprising a first chip and a first rewiring layer;

the first surface of the first chip is provided with a plurality of conductive posts, and the first chip is arranged on the first surface of the first rewiring layer through the plurality of conductive posts;

the gaps of the plurality of conductive columns are filled with insulating materials, the insulating materials are arranged between the first surface of the first chip and the first surface of the first rewiring layer, orthographic projection of the insulating materials to the first chip is located in the boundary range of the first chip, and the boundary of the orthographic projection and the boundary of the first chip have a preset distance;

the side edges of the first chip and the parts of the first surface of the first chip not covered by the insulating material and the conductive posts are wrapped by plastic packaging materials deposited on the first surface of the first rewiring layer.
The fan-out package structure of claim 1, wherein a surface of the plurality of conductive posts that contacts the first redistribution layer is flush with a surface of the insulating material that contacts the first redistribution layer.
The fan-out package structure according to claim 1 or 2, wherein a second surface of the first redistribution layer opposite to the first surface is provided with a plurality of bumps, and the terminals of the first chip are in communication with at least some of the plurality of bumps through the plurality of conductive pillars and the first redistribution layer.
The fan-out package structure of any of claims 1-3, wherein the plastic encapsulant further covers a second surface of the first chip opposite the first surface.
The fan-out package structure of claim 4, further comprising a second die;

the second chip is arranged on one side, away from the first rewiring layer, of the first chip.
The fan-out package structure of claim 5, further comprising a second redistribution layer disposed on a side of the plastic package material remote from the first chip;

the second chip is arranged on one side, far away from the first rerouting layer, of the second rerouting layer through a plurality of bonding pads.
The fan-out package structure of claim 6, wherein a region of the plastic package material away from the first chip is provided with a through hole communicating the first redistribution layer and the second redistribution layer;

the second chip is connected with the first chip through the second redistribution layer, the through hole and the first redistribution layer.
The fan-out package structure of claim 3, further comprising a printed circuit board;

the second surface of the first rewiring layer is arranged on the surface of the printed circuit board through the plurality of bumps.
The fan-out package structure of any of claims 1-3, further comprising a heat sink;

the heat sink is disposed over the second surface of the first chip.
An electronic device comprising the fan-out package structure of any of claims 1-9.
The preparation method of the fan-out type packaging structure is characterized by comprising the following steps of:

forming a plurality of conductive pillars on a first surface of a first chip;

depositing an insulating material on the first surface of the first chip, wherein the insulating material fills gaps of the conductive posts, orthographic projection of the insulating material to the first chip is positioned in the boundary range of the first chip, and the orthographic projection boundary is a preset distance from the boundary of the first chip;

forming a plastic package material on the first chip, wherein the plastic package material wraps the side edge of the first chip and the exposed part of the first surface of the first chip;

and forming a first rewiring layer on the plane formed by the conductive posts, the insulating material and the plastic packaging material.
The method of claim 11, wherein the molding material further encapsulates a second surface of the first chip opposite the first surface.
The method of manufacturing according to claim 12, characterized in that the method of manufacturing further comprises:

forming a second redistribution layer on one side of the plastic packaging material away from the first redistribution layer;

forming a plurality of bonding pads on one side of the second redistribution layer away from the plastic packaging material;

and disposing a second chip over the second redistribution layer through the plurality of pads.
The method of manufacturing according to claim 13, further comprising:

a through hole for communicating the first rewiring layer and the second rewiring layer is formed in the area, away from the chip, of the plastic packaging material;

the second chip is communicated with the first chip through the first rerouting layer, the through hole and the second rerouting layer.