WO2023015480A1

WO2023015480A1 - Fan-out chip package structure and preparation method

Info

Publication number: WO2023015480A1
Application number: PCT/CN2021/112021
Authority: WO
Inventors: 蔡崇宣; 赵南; 洪瑞斌
Original assignee: 华为技术有限公司
Priority date: 2021-08-11
Filing date: 2021-08-11
Publication date: 2023-02-16
Also published as: CN117242555A

Abstract

Embodiments of the present application provide a fan-out package structure and a preparation method. The fan-out package structure comprises a first chip and a first redistribution layer; a first surface of the first chip is provided with a plurality of conductive pillars, and the first chip is disposed on a first surface of the first redistribution layer by means of the plurality of conductive pillars; gaps of the plurality of conductive pillars are filled with an insulating material, the insulating material is disposed between the first surface of the first chip and the first surface of the first redistribution layer, and the orthographic projection of the insulating material to the first chip is located at the boundary range of the first chip, and the boundary of the orthographic projection has a preset distance from the boundary of the first chip; the side of the first chip and the part of the first surface of the first chip that is not covered by the insulating material and the plurality of conductive pillars are wrapped by a plastic package material deposited on the first surface of the first redistribution layer. Thus, support and protection can be provided for the edge area of the first chip, avoiding delamination or fracture of the first chip, thereby improving the reliability of the chip.

Description

Fan-out chip packaging structure and manufacturing method

technical field

The embodiments of the present application relate to the technical field of semiconductor packaging, and in particular to a fan-out chip packaging structure and manufacturing method.

Background technique

With the development of communication, artificial intelligence and other technologies, the demand for a large amount of data flow and transfer is increasing. The hardware supporting applications such as 5G applications and artificial intelligence needs to have high-speed computing, low latency, multi-bandwidth and system integration. Function. In order to meet the functional requirements of hardware devices, the industry proposes to use a substrate-less packaging structure to package multiple chips together to improve the electrical performance of the packaged chips. Substrate-less packaging structures include Fan-in Wafer Level Package and Fan-out Package. Compared with the fan-in packaging structure, the fan-out packaging structure can provide more I/O connection points and become the mainstream direction.

In the current fan-out packaging structure, it is necessary to place multiple chips to be packaged on a carrier with temporary bonding glue for wafer reconfiguration. Chip warpage is usually caused during wafer reconfiguration or reliability testing, resulting in delamination or fracture in the area with greater stress between each two chips. Since the area with greater stress between each two chips is provided with For the circuit connecting multiple chips, the fracture of this area will cause the circuit to break, which will lead to the failure of the connection between the chips, and then lead to the failure of the function of the chip. Therefore, how to improve the reliability of the packaged chip becomes a problem to be solved.

Contents of the invention

The fan-out packaging structure and preparation method provided in the present application can improve the reliability of the packaged chip.

In order to achieve the above object, the application adopts the following technical solutions:

In the first aspect, the embodiment of the present application provides a fan-out packaging structure, the fan-out packaging structure includes: a first chip and a first redistribution layer; the first surface of the first chip is provided with a plurality of conductive pillars , the first chip is disposed on the first surface of the first redistribution layer through the plurality of conductive pillars; the gaps between the plurality of conductive pillars are filled with insulating material, and the insulating material is disposed on the first Between the first surface of the chip and the first surface of the first redistribution layer, the orthographic projection of the insulating material to the first chip is located within the boundary range of the first chip, and the orthographic projection of the There is a predetermined distance between the boundary and the boundary of the first chip; the side of the first chip and the part of the first surface of the first chip not covered by the insulating material and the plurality of conductive pillars, Wrapped by the molding material deposited on the first surface of the first redistribution layer.

In the fan-out packaging structure provided by the embodiment of the present application, multiple first chips can be packaged in the same package, and the multiple first chips can be arranged in parallel and spaced apart in the package. It should be noted that, the plurality of first chips refer to chips manufactured by using a synchronous process and packaged in a same package. The plurality of first chips may be different types of chips. For example, one of the first chips may be a processor, and the other first chip may be a transistor.

In the embodiment of the present application, the orthographic projection of the insulating material to the first chip is set within the boundary range of the first chip, and the boundary of the orthographic projection has a preset distance from the boundary of the first chip, so that the first chip of the first chip No insulating material is deposited on the part of the surface close to the edge of the first chip, and this part is exposed during the packaging process. When the plastic packaging material is arranged outside the first chip, the plastic packaging material can wrap the sides and corners of the first chip in the plastic packaging material, and the thickness of the plastic packaging material between every two first chips can be increased so that every two first chips The area between the chips provides support and protection, preventing the area between every two first chips from breaking along the thickness direction of the first chips, thereby improving the reliability of chip packaging.

The insulating material provided in the embodiment of the present application may be an organic polymer material, including but not limited to: polyimide, polybenzoxazole, benzocyclobutene, or epoxy molding compound.

The molding material provided in the embodiment of the present application may be one or a combination of epoxy resin, polyethylene, polypropylene, polyolefin, polyamide, and polyimide.

Based on the first aspect, in a possible implementation manner, the surface of the plurality of conductive pillars in contact with the first redistribution layer is located at the same surface as the surface of the insulating material in contact with the first redistribution layer. level.

By arranging the surfaces of the plurality of conductive columns and the surface of the insulating material on the same level, the plane formed by the surfaces of the conductive columns and the surface of the insulating material can be made smoother, which is more conducive to the realization of subsequent manufacturing processes.

Based on the first aspect, in a possible implementation manner, the second surface of the first redistribution layer opposite to the first surface is provided with a plurality of bumps, and the lead-out end of the first chip passes through the plurality of bumps. A conductive pillar and the first redistribution layer communicate with at least some of the plurality of bumps.

The fan-out packaging structure provided in the embodiment of the present application may be various types of packaging structures.

In a first possible packaging structure, the fan-out packaging structure is wafer-level chip-scale packaging. In this possible implementation manner, the molding material also covers a second surface of the first chip opposite to the first surface.

Further, the wafer-level chip size package may also include building a package-on-package structure. In this possible implementation manner, the fan-out packaging structure further includes a second chip; the second chip is disposed on a side of the first chip away from the first redistribution layer.

In the case that the fan-out packaging structure is a package-on-package structure, the fan-out packaging structure further includes a second redistribution layer, and the second redistribution layer is disposed on the molding material away from all One side of the first chip; the second chip is disposed on a side of the second redistribution layer away from the first redistribution layer through a plurality of pads.

In the case that the fan-out packaging structure is a package-on-package structure, further, the area of the molding material away from the first chip is provided with a connection between the first rewiring layer and the second rewiring layer. through holes in layers; the second chip is connected to the first chip through the second redistribution layer, the through holes and the first redistribution layer.

In a second possible package structure, the fan-out package structure is a board-level chip size package. In this possible implementation manner, the fan-out packaging structure further includes a printed circuit board; the second surface of the redistribution layer is disposed on the first surface of the printed circuit board through the plurality of bumps.

In the case where the fan-out packaging structure is a board-level chip size packaging structure, in a possible implementation manner, the fan-out packaging structure further includes a heat sink; the heat sink is arranged on the first on the second surface of the chip.

Based on the first aspect, the first redistribution layer provided by the embodiment of the present application includes at least one layer of patterned conductive lines and an insulating material for isolating the patterned conductive lines. In addition, the first redistribution layer is also provided with via holes , the via hole is filled with conductive material, and the first chip passes through the conductive circuit on the first redistribution layer and the via hole provided on the first redistribution layer, and is formed by the first redistribution layer of the first redistribution layer. The surface leads to the second surface to communicate with the plurality of bumps.

Based on the first aspect, the second redistribution layer provided by the embodiment of the present application includes at least one layer of patterned conductive lines and an insulating material for isolating the patterned conductive lines. In addition, the second redistribution layer is also provided with via holes , the via hole is filled with conductive material, and the second chip passes through the conductive circuit on the second redistribution layer, the via hole provided on the second redistribution layer, the via hole and the first redistribution layer layer, communicated with the first chip.

In a second aspect, an embodiment of the present application provides an electronic device, where the electronic device includes the fan-out packaging structure described in the first aspect.

The chip packaged by the fan-out packaging structure may include but not limited to: System on chip (System on chip), memory (Memory), discrete device, application processing chip (Application Processor, AP), micro-electromechanical system (Micro-Electro- Mechanical System, MEMS), microwave radio frequency chip, application specific integrated circuit (Application Specific Integrated Circuit, referred to as ASIC) and other chips. The above-mentioned application processing chip or application-specific integrated circuit may be a central processing unit (Central Processing Unit, CPU), an image processor (Graphics Processing Unit, GPU), an artificial intelligence processor, for example, a neural network processor (Network Processing Unit, NPU), etc. The memory may be a cache memory (cache), a random access memory (Random Access Memory, RAM), a read-only memory (Read Only Memory, ROM), or other memory. Discrete devices may include, but are not limited to, eg, field effect transistors, bipolar transistors, integrated operational amplifiers, and the like, for example. The electronic device may also be an integrated circuit product, wherein, in addition to the fan-out packaging structure described in the embodiment of the present application, the integrated circuit product may also include other integrated circuits, so that the fan-out package structure shown in the embodiment of the present application The type package structure cooperates with other integrated circuits to realize various circuit functions.

In a third aspect, an embodiment of the present application provides a method for preparing a fan-out packaging structure, the preparation method comprising: forming a plurality of conductive pillars on the first surface of the first chip; depositing an insulating material, the insulating material fills the gaps of the plurality of conductive columns, the orthographic projection of the insulating material to the first chip is located within the boundary range of the first chip, and the boundary of the orthographic projection is in line with the The boundary of the first chip has a preset distance; a plastic encapsulation material is formed on the first chip, and the plastic encapsulation material wraps the side of the first chip and the exposed part of the first surface of the first chip ; forming a first redistribution layer on the plane formed by the plurality of conductive pillars, the insulating material and the molding material.

Based on the third aspect, in a possible implementation manner, the molding material further wraps a second surface of the first chip opposite to the first surface.

Based on the third aspect, in a possible implementation manner, the preparation method further includes: forming a second redistribution layer on a side of the molding material away from the first redistribution layer; A plurality of welding pads are formed on the side of the wiring layer away from the plastic encapsulation material; the second chip is arranged on the second rewiring layer through the plurality of welding pads.

Based on the third aspect, in a possible implementation manner, the preparation method further includes: opening a hole for connecting the first redistribution layer and the second redistribution layer in a region of the molding material far away from the chip; Through holes: the second chip communicates with the first chip through the first redistribution layer, the through holes and the second redistribution layer.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments of the present application. Obviously, the accompanying drawings in the following description are only some embodiments of the present application , for those skilled in the art, other drawings can also be obtained according to these drawings without paying creative labor.

FIG. 1 is a schematic structural diagram of a fan-out packaging structure provided by an embodiment of the present application;

Fig. 2 is a top view of the fan-out packaging structure shown in Fig. 1 provided by the embodiment of the present application after being cut along AA';

FIG. 3 is a schematic structural diagram of a fan-out packaging structure in the conventional technology;

FIG. 4 is a top view of the fan-out packaging structure shown in FIG. 3 after the redistribution layer is removed;

FIG. 5 is another structural schematic diagram of the fan-out packaging structure provided by the embodiment of the present application;

FIG. 6 is another structural schematic diagram of the fan-out packaging structure provided by the embodiment of the present application;

FIG. 7 is another structural schematic diagram of the fan-out packaging structure provided by the embodiment of the present application;

FIG. 8 is a flowchart of a method for preparing the fan-out packaging structure shown in FIG. 1 provided in the embodiment of the present application;

FIGS. 9A-9G are schematic diagrams of various structures during the preparation process of the fan-out packaging structure shown in FIG. 1 .

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

"First", "second" and similar words mentioned herein do not indicate any order, quantity or importance, but are only used to distinguish different components. Likewise, words like "a" or "one" do not denote a limitation in number, but indicate that there is at least one.

In the embodiments of the present application, words such as "exemplary" or "for example" are used to represent examples, illustrations or descriptions. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application shall not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete manner. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more. For example, a plurality of chips refers to two or more chips.

The fan-out packaging structure provided in the embodiment of the present application can package multiple chips in the same package. The multiple chips can be arranged at intervals horizontally, and each chip is connected to other chips, a common power supply and a common ground through a conductive column and a redistribution layer arranged on the chip, so as to realize signal exchange between the multiple chips. The chip described in the embodiment of the present application may be a bare chip (Die), or a chip formed by simple packaging of a bare chip and other chips or components (active devices or passive devices, etc.), or may be packaged The subsequent chip packaging structure is not limited here. Taking two horizontally arranged chips in the same package as an example, the fan-out package structure described in the embodiment of the present application will be described below with reference to FIG. 1 .

Please refer to FIG. 1 . FIG. 1 is a schematic structural diagram of a fan-out packaging structure provided by an embodiment of the present application. In FIG. 1 , a fan-out package structure 100 includes a chip 10 , a chip 11 , a redistribution layer 20 , a plurality of conductive pillars 30 and a plurality of conductive pillars 31 . The chip 10 includes opposite surfaces S1 and S2, and a plurality of lead terminals are formed on the surface S1. Multiple leads on the chip 10 are connected to the chip 11, the common power supply and the common ground through the conductive pillar 30 and the redistribution layer 20. The chip 11 includes opposite surfaces S3 and S4, and a plurality of lead terminals are formed on the surface S3. Multiple leads on the chip 11 are connected to the chip 10 , the common power supply and the common ground through the conductive pillar 31 and the redistribution layer 20 . A plurality of conductive pillars 30 are arranged between the chip 10 and the wiring layer 20, and the leads of the chip 10 are drawn out to the surface D1 of the rewiring layer 20 through the plurality of conductive pillars 30; a plurality of conductive pillars 31 are arranged between the chip 11 and the wiring layer 20 , the leading end of the chip 11 is led out to the surface D1 of the redistribution layer 20 through a plurality of conductive pillars 31 . It should be noted that the leads on the surface S1 of the chip 10 and the leads on the surface S3 of the chip 11 can be one of pads, micro-bumps and copper pillar bumps (Cu pillar) .

The number of conductive pillars 30 can be the same as the number of lead ends of the chip 10, that is, each lead end of the chip 10 is provided with a conductive pillar 30; the number of conductive pillars 31 can be the same as the number of lead ends of the chip 11, that is, every Each lead-out end of a chip 11 is provided with a conductive post 31 . The conductive pillars 30 and the conductive pillars 31 can be metal pillars formed of metal materials, such as copper pillars, aluminum pillars, silver pillars or palladium pillars, etc., and can also be pillars formed of other conductive materials. This is not limited. Gaps are formed between the plurality of conductive columns 30 , and gaps are also formed between the plurality of conductive columns 31 . The gaps between the plurality of conductive pillars 30 and the gaps between the plurality of conductive pillars 31 are filled with an insulating material 40 , and the insulating material 40 may be an organic polymer material. The organic polymer material may include but not limited to: polyimide (PI, Polyimide), polybenzoxazole (ploybenzoxazole, PBO), benzocyclobutene (BCB), or epoxy molding compound (Epoxy Molding Compound , EMC) etc.

The insulating material 40 is deposited on the surface S1 of the chip 10 and the surface S3 of the chip 11 respectively. Along the direction x shown in FIG. 1 , that is, the thickness direction of the chip, the height of the insulating material 40 is the same as that of the conductive pillars 30 and the conductive pillars 31 . In addition, the first orthographic projection of the insulating material 40 deposited on the surface S1 of the chip 10 to the surface S1 of the chip 10 is located within the boundary range of the chip 10, and the boundary of the first orthographic projection and the boundary of the chip 10 have a first predetermined relationship. Suppose the distance; the insulating material 40 deposited on the surface S3 of the chip 11, the second orthographic projection to the surface S3 of the chip 11 is located within the boundary range of the chip 11, and the boundary of the second orthographic projection and the boundary of the chip 11 have the same Two preset distances. The above-mentioned first preset distance and second preset distance may be the same or different, and are set according to the requirements of the application scenario. As shown in FIG. 2 , FIG. 2 is a top view of the fan-out packaging structure 100 shown in FIG. 1 cut along AA'. It can be seen from FIG. 2 that no insulating material 40 is deposited on the area A1 near the edge of the chip 10 on the surface S1 of the chip 10 , and no insulating material 40 is deposited on the area A2 near the edge of the chip 11 on the surface S3 of the chip 11 . Therefore, in the fan-out packaging structure 300 , before the molding compound is provided, the sides of the chip 10 and the chip 11 , the portion of the surface S1 of the chip 10 near the edge, and the portion of the surface S3 of the chip 20 near the edge are all exposed.

In the fan-out packaging structure shown in FIG. 1 , a plastic encapsulation material 50 is also included. The molding material may include, for example, one or more combinations of epoxy resin (Epoxy Molding Compound, EMC), polyethylene, polypropylene, polyolefin, polyamide, and polyimide. After the plastic encapsulation material 50 is deposited in the fan-out packaging structure 100 , the plastic encapsulation material 50 wraps the parts of the chip 10 and the chip 11 that are not covered by the insulating material 40 , the conductive pillars 30 and the conductive pillars 31 .

In the traditional fan-out chip-first (Chip-First) packaging technology, the insulating material 40 is usually used to completely cover the surface S1 of the chip 10 and the surface S3 of the chip 11, and the surface S2 and the side surfaces of the chip 10 are wrapped by the plastic packaging material 50. Wrap the surface S4 and the side of the chip 11, as shown in Figure 3 and Figure 4, Figure 3 is a schematic diagram of the fan-out packaging structure in the traditional technology, Figure 4 is the fan-out packaging structure shown in Figure 3 with heavy The top view after the wiring layer 20. In a fan-out packaging structure including multiple chips, the area between every two chips has relatively large stress. When the packaging structure shown in FIG. 3 is adopted, due to the influence of etching and other process steps in the process, the edge of the molding material 50 is relatively weak, that is, the part of the molding material 50 disposed between the chip 10 and the chip 11 is relatively weak. The weak plastic encapsulation material 50 is not enough to support the stress in the middle area of the chip 10 and the chip 11 , causing the area between the chip 10 and the chip 11 to fracture along the x direction. It can be seen from FIG. 3 that when the area between the chip 10 and the chip 11 is broken along the x direction, the H area of the redistribution layer 20 may also be broken. Since the H area of the rewiring layer 20 is provided with conductive lines for connecting the chip 10 and the chip 11, and connecting the chip 10 and the chip 11 with the common power supply and the common ground, the break of the H area of the wiring layer 20 causes the breakage of the conductive line, thereby causing The connection between the chips, the connection between the chip and the public power supply, or the connection between the chip and the common ground fails, which leads to the failure of the function of the chip.

In this embodiment of the present application, no insulating material 40 is deposited on the part of the surface S1 of the chip 10 near the edge of the chip 10 and the part of the surface S3 of the chip 11 near the edge of the chip 11 , and these parts are exposed during the packaging process. When the plastic packaging material 50 is arranged outside the chip 1, the plastic packaging material 50 can wrap the sides and corners of the chip 10 and the chip 11 in the plastic packaging material 50, thereby increasing the thickness of the plastic packaging material 50 between the chip 10 and the chip 11, Provide support and protection for the area between the chip 10 and the chip 11, prevent the area between the chip 10 and the chip 11 from breaking along the x direction, and improve the reliability of the chip package.

Please continue to refer to FIG. 1. In FIG. 1, the redistribution layer 20 may include at least one patterned conductive circuit and an insulating material for isolating the patterned conductive circuit. The conductive material used to form the patterned conductive circuit may be metal, such as A combination of one or more of copper (Cu), silver (Ag), aluminum (Al) and other metals, the conductive material used to form patterned conductive lines can also be button tin oxide (ITO), graphite, graphene etc.; the insulating material can be an inorganic insulating material or an organic insulating material, etc. The redistribution layer 20 may also be provided with vias (Via), which may include but not limited to: through holes or buried holes. The vias may be filled with conductive material. In addition, pads (Pad) 21 are also provided on the surface D2 of the redistribution layer 20, and a plurality of bumps 60 are arranged on each pad 21. The material of the bumps 60 may include but not limited to: tin material or tin Silver mixed materials, etc. The lead-out end of the chip 10 is led from the surface D1 of the redistribution layer 20 to the surface D2 through the conductive lines on the redistribution layer 20 and the via holes provided on the redistribution layer 20, thereby communicating with a part of the bumps 60; the lead out of the chip 11 The end is led from the surface D1 to the surface D2 of the redistribution layer 20 through the conductive lines on the redistribution layer 20 and the via holes provided on the redistribution layer 20 , so as to communicate with another part of the bump 60 . The chip 10 and the chip 20 can also be connected through the lines on the redistribution layer 20 , so as to realize the signal communication between the chip 10 and the chip 20 .

In the fan-out packaging structure 100 shown in FIG. 1 , it is shown that two parallel and spaced chips are packaged in the same package. The fan-out package structure described in the embodiment of the present application may also be a fan-out package stack (FO-PoP, Fan Out-Package on Package) package structure. Please refer to FIG. 5 , which is a schematic diagram of a fan-out packaging structure 200 provided by an embodiment of the present application. In FIG. 5 , the fan-out packaging structure 200 includes not only the

chips

10 and 11 arranged horizontally apart, but also the chip 12 . Along the direction x shown in FIG. 5 , the chip 12 is disposed on the chip 10 and the chip 11 . Specifically, the fan-out packaging structure 200 further includes a redistribution layer 70 on the basis of the fan-out packaging structure 100 shown in FIG. 1 . The redistribution layer 70 can include at least one layer of patterned conductive lines and an insulating material that isolates the patterned conductive lines. The conductive material used to form the patterned conductive lines can be metal, such as copper (Cu), silver (Ag), aluminum A combination of one or more of metals such as (Al), the conductive material used to form patterned conductive lines can also be button tin oxide (ITO), graphite, graphene, etc.; the insulating material can be an inorganic insulating material or an organic insulating materials, etc. The redistribution layer 70 is disposed on the molding compound 50 . A plurality of pads (Pad) 71 are also arranged on the redistribution layer 70 , and the leads of the chip 12 are soldered to the pads 71 , so that the leads of the chip 12 are led out to the surface of the redistribution layer 70 . In addition, along the direction x shown in FIG. 5 , the molding compound 50 is also provided with a plurality of through holes 51 penetrating through the upper surface and the lower surface of the molding material 50, and the through holes 51 are filled with conductive materials. The through holes 51 are used for The redistribution layer 20 and the redistribution layer 70 are connected. The lead-out end of the chip 12 is led to the surface D1 of the redistribution layer 20 through the conductive circuit on the redistribution layer 70 and the through hole 51, and then communicates with the chip 10 and the chip 11 through the conductive circuit provided on the redistribution layer 20 to realize the chip. 12 and the signal exchange between the chip 10 and the chip 11.

In the fan-out package structure shown in FIG. 4 , one chip is stacked on the chip 10 and the chip 11; The chips are communicated with each other through a through hole provided on the insulating layer, which is not specifically limited in this embodiment of the present application.

The fan-out package structure shown in Figure 1 and Figure 5 is Fan Out-Wafer Level Chip Scale Package (FO-WLCSP, Fan Out-Wafe Level Chip Scale Package). The fan-out packaging structure shown in the embodiment of the present application may also be a Fan Out-Panel Level Package (FO-PLP, Fan Out-Panel Level Package). Specifically, the board-level package may be a Flip Chip Ball Grid Array (FCBGA, Flip Chip Ball Grid Array). Please refer to FIG. 6 , which is a schematic structural diagram of a fan-out board-level package 300 provided by an embodiment of the present application. In FIG. 6 , the fan-out board-level package 300 includes a printed circuit board (PCB, Print Circuit Board) 80 in addition to the fan-out package structure 100 shown in FIG. 1 . The PCB 80 may include multiple wiring layers. The surface P1 of the PCB 80 , the surface P2 opposite to the surface P1 , and the intermediate wiring layer between the surface P1 and the surface P2 are all provided with patterned conductive lines. The PCB 80 is also provided with vias (Via), which may include but not limited to: through holes or buried holes. The conductive lines on the surface P1 of the PCB 80 , the conductive lines on the intermediate wiring layer and the conductive lines on the surface P2 can be connected through via holes. In addition, the surface P2 of the PCB 80 is also provided with a ball grid array 81 . The fan-out packaging structure 100 is attached to the surface P1 of the PCB 80 through the bumps 60, and then the leads of the chip 10 and the lead-out ends of the chips 11 packaged in the fan-out packaging structure 100 are led to the surface P2 of the PCB 80 through the bumps 60. Ball grid array 81 on.

Further, on the basis of the fan-out board-level packaging structure 300 shown in FIG. 6 , the fan-out board-level packaging structure provided in the embodiment of the present application may further include a heat sink 90 . At this time, neither the surface S2 of the chip 10 nor the surface S4 of the chip 11 is provided with the plastic encapsulation material 50, the surface S2 of the chip 10 and the surface S4 of the chip 11 are coated with a heat dissipation material, and no fan-out package is provided on the PCB 80 The area of the structure 100 may also be coated with a heat dissipation material 91 , and the heat dissipation sheet 90 is mounted on the surface S2 of the chip 10 , the surface S4 of the chip 11 and the surface P1 of the PCB through the heat dissipation material 91 . During the working process, the chip 10 and the chip 11 can dissipate heat through the heat sink. In addition, the heat sink 90 can also provide physical protection for the fan-out packaging structure 100 .

The embodiment of the present application also includes an electronic device, where the electronic device includes the fan-out packaging structure shown in the above-mentioned embodiments. The chip packaged by the fan-out packaging structure may include but not limited to: System on chip (System on chip), memory (Memory), discrete device, application processing chip (Application Processor, AP), micro-electromechanical system (Micro-Electro- Mechanical System, MEMS), microwave radio frequency chip, application specific integrated circuit (Application Specific Integrated Circuit, referred to as ASIC) and other chips. The above-mentioned application processing chip or application-specific integrated circuit may be a central processing unit (Central Processing Unit, CPU), an image processor (Graphics Processing Unit, GPU), an artificial intelligence processor, for example, a neural network processor (Network Processing Unit, NPU), etc. The memory may be a cache memory (cache), a random access memory (Random Access Memory, RAM), a read-only memory (Read Only Memory, ROM), or other memory. Discrete devices may include, but are not limited to, eg, field effect transistors, bipolar transistors, integrated operational amplifiers, and the like, for example. For example, when the fan-out packaging structure shown in FIG. 1 or FIG. 6 is adopted, the chip 10 and the chip 11 packaged in the fan-out packaging structure can be application processing chips and discrete devices respectively; In the fan-out packaging structure shown, the

chips

10 and 11 packaged in the fan-out packaging structure may be application processing chips and discrete devices respectively, and the chip 12 may be a memory. The electronic device may also be an integrated circuit product, wherein, in addition to the fan-out packaging structure described in the embodiment of the present application, the integrated circuit product may also include other integrated circuits, so that the fan-out package structure shown in the embodiment of the present application The type package structure cooperates with other integrated circuits to realize various circuit functions.

Based on the fan-out packaging structure described in the above embodiments, the embodiment of the present application also provides a method for preparing a fan-out packaging structure. The structure of the prepared fan-out packaging structure is shown in Figure 1 below As an example, with reference to the process 800 shown in FIG. 8 , the process flow of preparing the fan-out packaging structure will be described in detail. The process flow 800 includes the following steps:

Step 801 , forming conductive pillars 30 at the leading end of the chip 10 to be packaged, and forming conductive pillars 31 at the leading end of the chip 11 to be packaged.

In the embodiment of the present application, the process of forming the conductive pillar 30 at the lead-out end of the chip 10 is the same as the process of forming the conductive pillar 31 at the lead-out end of the chip 11 . This step will be described below by taking the process of forming the conductive pillar 30 at the leading end of the chip 10 as an example.

Assume that the surface S1 of the chip 10 is formed with leads. Firstly, a metal material is deposited on the surface S1 of the chip 10 by vapor deposition (such as physical vapor deposition or chemical vapor deposition). The metal material may include, but is not limited to: materials such as copper, aluminum, silver, gold, or metal alloy materials. Next, a photoresist is deposited on the surface of the metal material. Then, a mask is used to etch the part of the metal material that does not cover the leading end of the chip 10 , so as to form the conductive pillar 30 on the surface S1 of the chip 10 , as shown in FIG. 9A . The aforementioned etching of the metal material may be performed by dry etching or wet etching. Taking the metal material deposited on the chip 10 as copper material as an example, when wet etching is used, the copper material can be etched with an etching solution such as ferric chloride etching solution or hydrochloric acid-copper chloride etching solution.

In order to better protect the chip 10, when etching the metal material, avoid partially etching the chip 10 to affect the electrical performance of the chip 10. In a possible implementation, before depositing the metal material on the surface S1 of the chip 10 Alternatively, another metal material different from the above metal material may be deposited on the surface S1 of the chip 10 to form a barrier layer. The etching speed of the barrier layer is slower than that of the metal material. For example, when the metal material is copper material, the material forming the barrier layer may be titanium material, for example. It should be noted that, when the barrier layer is formed on the chip 10 , after the metal material is etched in step 801 , the exposed barrier layer needs to be further etched.

For the process of forming the conductive pillar 31 at the lead-out end of the chip 11 , please refer to the process of forming the conductive pillar 30 at the lead-out end of the chip 10 , which will not be repeated here.

Step 802 , deposit insulating material 40 on the surface S1 of the chip 10 and the surface S3 of the chip 11 respectively.

After the conductive pillars 30 are formed at the leads of the chip 10 , an insulating material 40 may be deposited on the surface S1 of the chip 10 . Along the deposition direction of the insulating material 40 , the thickness of the insulating material 40 deposited is higher than the height of the conductive pillar 30 . Therefore, the insulating material 40 deposited on the surface S1 of the chip 10 also wraps the conductive pillars 30 . Then, deposit a photoresist on the insulating material 40 , and use a mask to etch the insulating material 40 at the boundary, so that the position on the surface S1 of the chip 10 at a preset distance from the edge of the chip 10 is exposed. After the conductive pillars 31 are formed at the leads of the chip 11 , the insulating material 40 can be deposited on the surface S3 of the chip 11 using the same process. Likewise, a position on the surface S3 of the chip 11 at a preset distance from the edge of the chip 11 is exposed. The resulting structure after this step is shown in Figure 9B.

Step 803, flip-chip chip 10 and chip 11 on carrier b. The resulting structure after this step is shown in Figure 9C.

The material of the carrier b may include, but not limited to: silicon material, glass material, or a mixture of the two materials, etc., and the carrier b may have a wafer-level or board-level size.

In a possible implementation manner, the bonding glue a is coated on the surface of the deposited organic polymer 40 of the chip 10 , and the side of the chip 10 coated with the bonding glue a is mounted on the carrier b. Similarly, the bonding glue a is coated on the surface of the deposited organic polymer 40 of the chip 11 , and the side of the chip 11 coated with the bonding glue a is mounted on the carrier b. Wherein, the chip 10 and the chip 11 are arranged side by side and spaced apart on the carrier b.

In another possible implementation manner, the bonding glue a may be firstly coated on the surface of the carrier b. Then, the

chips

10 and 11 are pasted side by side and spaced apart on the carrier b. Wherein, the insulating material 40 deposited on the chip 10 is in contact with the bonding glue, and the exposed surface S2 of the chip 10 is arranged on the side away from the carrier b; the insulating material 40 deposited on the chip 11 is in contact with the bonding glue a, and the chip 11 The exposed surface S4 is located on the side away from the carrier b.

Step 804 , deposit molding material on the surface of the carrier b, the surface S2 of the chip 11 and the surface S4 of the chip 12 . The resulting structure after this step is shown in Figure 9D.

As can be seen from FIG. 9D , the parts of the surface S2, the side surfaces and the surface S1 of the chip 10 that are not covered by the insulating material 40 are all wrapped by the plastic encapsulation material 50; Parts are all wrapped by plastic sealing material 50 . Similarly, the plastic encapsulation material 50 is also filled between the chip 10 and the chip 11 . Thereby, the thickness of the molding material 50 between the chip 10 and the chip 11 can be increased to provide support and protection for the area between the chip 10 and the chip 11, avoiding the fracture of the area between the chip 10 and the chip 11 along the x direction, and improving the performance of the chip. package reliability.

Step 805 , removing the carrier b from the

chips

10 and 11 . The structure after removing the carrier b is shown in FIG. 9E .

Step 806 , planarize the side of the packaging structure where the bonding glue is disposed, so as to expose the conductive pillars 30 and the conductive pillars 31 . The structure formed after the package structure planarization process is shown in FIG. 9F .

After step 806, the bonding paste a is etched away. The sides of the conductive pillars 30 , the conductive pillars 31 and the insulating material 40 away from the chip 10 and the chip 11 are all exposed.

Step 807 , forming the redistribution layer 20 on the exposed surface of the conductive pillars 30 , the conductive pillars 31 , the insulating material 40 and the molding material 50 .

In this step, the rewiring layer 20 can be prepared on the surface formed by the exposed conductive pillars 30 , conductive pillars 31 , insulating material 40 and molding material 50 by using standard processes such as photolithography, developing, and etching. The redistribution layer 20 is double-sided wiring, and multiple layers of intermediate wiring layers are provided between the two sides of the redistribution layer 20 . The wiring layers are connected through via holes.

Step 808 , forming a plurality of pads 21 on the side of the redistribution layer 20 away from the chip 10 and the chip 11 . The package structure after the pads 21 are provided is shown in FIG. 9G .

After step 808 , the conductive pillar 30 and the conductive pillar 31 are respectively connected to the pad 21 through the multi-layer wiring layer and the via hole on the redistribution layer 20 . The material of the pad 21 may be copper, aluminum, gold or mixed metal materials.

Step 809 , forming bumps on a plurality of pads 21 . The bumps may be tin bumps.

After steps 801 to 809, the fan-out wafer level packaging structure as shown in FIG. 1 can be formed.

Further, on the basis of the fan-out wafer-level packaging structure shown in FIG. 1 , board-level packaging can be further performed on the fan-out wafer-level packaging structure. When board-level packaging is required, steps 810 to 816 may also be included. In step 810, the PCB is first prepared using standard techniques. The PCB is double-sided wiring, and multiple intermediate wiring layers are arranged between the two sides of the PCB. The wiring layers are connected through via holes. In step 811 , pre-solder the ball grid array on the surface P2 of the PCB, and the material of the ball grid array may be tin. Step 812 , mount the bump 60 on the fan-out packaging structure 100 shown in FIG. 1 on the surface P1 of the PCB. Therefore, the leads of the

chips

10 and 11 packaged in the fan-out packaging structure 100 are led to the ball grid array on the surface P2 of the PCB through the bumps 60 . Step 813 , etching the molding material 50 above the chip 10 and the chip 11 to expose the crystal backs of the chip 10 and the chip 11 . Step 815 , deposit heat dissipating material on the exposed crystal backs of the chip 10 and the chip 11 , and on the area of the PCB where no chip is placed. Step 816 , mount the heat sink 90 on the surface of the chip 10 with the heat dissipation material 91 , the surface of the chip 11 and the surface of the PCB. The board-level packaging structure 300 prepared through steps 810 to 816 is shown in FIG. 7 .

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit it; although the application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present application. scope.

Claims

A fan-out packaging structure, characterized in that it includes a first chip and a first redistribution layer;

The first surface of the first chip is provided with a plurality of conductive pillars, and the first chip is arranged on the first surface of the first redistribution layer through the plurality of conductive pillars;

The gaps of the plurality of conductive pillars are filled with an insulating material, the insulating material is disposed between the first surface of the first chip and the first surface of the first redistribution layer, and the insulating material faces the The orthographic projection of the first chip is located within the boundary range of the first chip, and the boundary of the orthographic projection has a preset distance from the boundary of the first chip;

The side of the first chip and the portion of the first surface of the first chip not covered by the insulating material and the plurality of conductive pillars are deposited on the first surface of the first redistribution layer Wrapped in plastic wrap.
The fan-out packaging structure according to claim 1, wherein the surface of the plurality of conductive pillars in contact with the first redistribution layer is the same as the surface of the insulating material in contact with the first redistribution layer. The surface is even.
The fan-out packaging structure according to claim 1 or 2, wherein a plurality of bumps are provided on the second surface of the first redistribution layer opposite to the first surface, and the leads of the first chip The terminal communicates with at least some of the plurality of bumps through the plurality of conductive pillars and the first redistribution layer.
The fan-out packaging structure according to any one of claims 1-3, characterized in that the plastic encapsulation material also covers a second surface of the first chip opposite to the first surface.
The fan-out packaging structure according to claim 4, wherein the fan-out packaging structure further comprises a second chip;

The second chip is disposed on a side of the first chip away from the first redistribution layer.
The fan-out packaging structure according to claim 5, characterized in that, the fan-out packaging structure further comprises a second redistribution layer, and the second redistribution layer is disposed on the molding material away from the one side of the first chip;

The second chip is disposed on a side of the second redistribution layer away from the first redistribution layer through a plurality of pads.
The fan-out packaging structure according to claim 6, wherein a through hole connecting the first redistribution layer and the second redistribution layer is opened in a region of the molding material far away from the first chip ;

The second chip is connected to the first chip through the second redistribution layer, the through hole and the first redistribution layer.
The fan-out packaging structure according to claim 3, wherein the fan-out packaging structure further comprises a printed circuit board;

The second surface of the first redistribution layer is disposed on the surface of the printed circuit board through the plurality of bumps.
The fan-out packaging structure according to any one of claims 1-3, wherein the fan-out packaging structure further comprises a heat sink;

The heat sink is disposed on the second surface of the first chip.
An electronic device, characterized by comprising the fan-out packaging structure according to any one of claims 1-9.
A preparation method of a fan-out packaging structure, characterized in that the preparation method comprises:

forming a plurality of conductive pillars on the first surface of the first chip;

An insulating material is deposited on the first surface of the first chip, the insulating material fills the gaps of the plurality of conductive pillars, and the orthographic projection of the insulating material to the first chip is located within the boundary range of the first chip , and the boundary of the orthographic projection has a preset distance from the boundary of the first chip;

forming a molding material on the first chip, the molding material wrapping the side of the first chip and the exposed part of the first surface of the first chip;

A first redistribution layer is formed on the plane formed by the plurality of conductive pillars, the insulating material and the molding material.
The preparation method according to claim 11, wherein the plastic encapsulation material further wraps the second surface of the first chip opposite to the first surface.
The preparation method according to claim 12, wherein the preparation method further comprises:

forming a second redistribution layer on a side of the molding material away from the first redistribution layer;

forming a plurality of pads on a side of the second redistribution layer away from the molding material;

The second chip is disposed on the second redistribution layer through the plurality of bonding pads.
The preparation method according to claim 13, wherein the preparation method further comprises:

opening a via hole for connecting the first redistribution layer and the second redistribution layer in a region where the molding material is away from the chip;

The second chip communicates with the first chip through the first redistribution layer, the through hole and the second redistribution layer.