CN109686716A - Wafer scale is fanned out to the wafer architecture of encapsulation and is fanned out to packaging technology using the wafer scale of the wafer architecture - Google Patents
Wafer scale is fanned out to the wafer architecture of encapsulation and is fanned out to packaging technology using the wafer scale of the wafer architecture Download PDFInfo
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- CN109686716A CN109686716A CN201811469838.XA CN201811469838A CN109686716A CN 109686716 A CN109686716 A CN 109686716A CN 201811469838 A CN201811469838 A CN 201811469838A CN 109686716 A CN109686716 A CN 109686716A
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- metal framework
- fanned out
- architecture
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- 238000005538 encapsulation Methods 0.000 title claims abstract description 24
- 238000012536 packaging technology Methods 0.000 title claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 64
- 229910052751 metal Inorganic materials 0.000 claims abstract description 64
- 238000004806 packaging method and process Methods 0.000 claims abstract description 21
- 239000005022 packaging material Substances 0.000 claims abstract description 15
- 238000001746 injection moulding Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 9
- 238000009434 installation Methods 0.000 claims description 5
- 238000003754 machining Methods 0.000 claims description 5
- 239000007769 metal material Substances 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Packaging Frangible Articles (AREA)
Abstract
The wafer architecture of encapsulation is fanned out to the present invention relates to a kind of wafer scale and packaging technology is fanned out to using the wafer scale of the wafer architecture, belongs to Wafer level packaging field.The wafer scale is fanned out to the wafer architecture of encapsulation, including metal framework unit, chip and plastic packaging material, and the metal framework unit includes main frame and connects foot, and even foot is set to the surrounding of main frame；The main frame uses closed frame structure, and main frame surrounds chip.The wafer scale is fanned out to packaging technology, comprising the following steps: (1) interim bonding film is mounted on substrate；(2) the affixed metal frame structure on interim bonding film；(3) pasting chip；(4) metal framework structure is obtained into wafer architecture together with chip injection molding；(5) substrate and interim bonding film are removed；(6) wafer scale is routed again；(7) ball is planted；(8) scribing.Metal framework structure of the invention can preferably resist chip offset problem caused by plastic packaging material trickles in injection moulding process.
Description
Technical field
The wafer architecture of encapsulation is fanned out to the present invention relates to a kind of wafer scale and envelope is fanned out to using the wafer scale of the wafer architecture
Dress technique belongs to Wafer level packaging field.
Background technique
With the rapid development of microelectronic manufacturing technology, electronic product is to thinner, smaller, lighter aspect development, using list
Chips encapsulation technology is gradually unable to satisfy industry demand, and wafer-level packaging (WLP) technology is based on BGA technology, institute
Some packaging and testing processes carry out all as unit of disk, so that package dimension as low as chip size, production cost is significantly
It reduces.This makes Wafer level packaging obtain great development and extensive use.
Wafer scale is fanned out to encapsulation and is drawn chip I/O port by the way of structure disk again, the shape on the encapsulated member of reconstruct
At soldered ball or salient point terminal arrays, the traditional encapsulation of wire bonding welded ball array or flip-chip weldering can be replaced in a certain range
Ball array encapsulating structure, especially suitable for portable consumer electronics application field.
It is fanned out in encapsulation in wafer scale, due to the thermal expansion coefficient difference between chip material and plastic packaging material, causes plastic packaging
Disk warpage afterwards is larger, simultaneously because to cause chip position to occur irregular inclined for the flowing of the plastic packaging material in injection moulding process
It moves, these can all cause again wiring technique performance difficulty to influence yield and yield.Traditional solutions are to reduce chip array number
Amount increases chip chamber spacing to achieve the effect that reduce warpage, convenient for scribing, and low efficiency, machining period are long, at high cost.
Summary of the invention
The purpose of the present invention is overcome full permutation disk plastic packaging exists in the prior art after warpage is excessive and injection moulding process
In generally existing chip offset problem, a kind of wafer scale is provided and is fanned out to the wafer architecture of encapsulation and the crystalline substance using the wafer architecture
Circle grade is fanned out to packaging technology, meets the encapsulation requirement of highly reliable plastic packaging.
According to technical solution provided by the invention, the wafer scale is fanned out to the wafer architecture of encapsulation, it is characterized in that: including gold
Belong to frame unit, chip and plastic packaging material, the metal framework unit and chip plastic packaging are in plastic packaging material；The metal framework unit
Including main frame and connect foot, even foot is set to the surrounding of main frame；The main frame uses closed frame structure, main frame packet
Enclose chip.
Further, 2-3 even foot is arranged in the every side of the main frame.
Further, the inside dimension of the main frame is greater than the size of chip.
Further, the thickness of the metal framework unit is less than the thickness of chip.
Further, the main frame uses closed polygonal frame structure or circular frame structure.
Further, the main frame uses rectangular frame structure.
Further, the metal material thermal expansion coefficient that the metal framework unit uses is higher than the thermal expansion system of plastic packaging material
Number.
Packaging technology is fanned out to using the wafer scale of above-mentioned wafer architecture, characterized in that the following steps are included:
(1) interim bonding film is mounted on substrate；
(2) the affixed metal frame structure on interim bonding film；The metal framework structure by several array arrangements metal
Frame unit is constituted, and adjacent metal frame unit is connected by even foot；The metal framework cellular array mode and to be arranged
Chip arrangement is consistent；
(3) pasting chip, the installation site of chip are located at the inside of metal framework structure, by metal framework structure by chip packet
It encloses；During load, the load of every chip piece all carries out load positioning with the metal framework unit center where the chip；
(4) wafer scale injection molding reconstruct obtains wafer architecture by metal framework structure together with chip injection molding；
(5) substrate and interim bonding film are removed；
(6) wafer scale is routed again；
(7) ball is planted；
(8) scribing obtains wafer-level packaging.
Further, in the step (2), metal framework structure is directly obtained by way of machining, Huo Zhetong
Over etching method obtains.
Compared with the prior art the present invention has the advantage that
(1) metal framework unit is carried out plastic packaging by the present invention together with chip, is faced in the prior art directly chip is fitted in
When bonding film on plastic packaging compare, metal framework structure of the invention injection moulding process can preferably resist plastic packaging material trickling causes
Chip offset problem；
(2) metal material of the metal framework using thermal expansion coefficient higher than plastic packaging material in the present invention, with existing plastic packaging scheme phase
Than metal framework structure of the invention is able to suppress the warpage issues of disk after plastic packaging.
Detailed description of the invention
Fig. 1 is the cross-sectional view for the wafer architecture that wafer scale of the present invention is fanned out to encapsulation.
Fig. 2 is the top view for the wafer architecture that wafer scale of the present invention is fanned out to encapsulation.
Fig. 3 is that the schematic diagram after metal framework structure and chip is installed on substrate.
Fig. 4 is the cross-sectional view of Fig. 3.
Description of symbols: 1- metal framework unit, 2- chip, 3- plastic packaging material, 4- main frame, 5- connect foot, 6- metal frame
Frame structure.
Specific embodiment
Below with reference to specific attached drawing, the invention will be further described.
As shown in Figure 1 and Figure 2, it includes metal framework unit 1, core that wafer scale of the present invention, which is fanned out to the wafer architecture of encapsulation,
Piece 2 and plastic packaging material 3, the metal framework unit 1 and 2 plastic packaging of chip are in plastic packaging material 3；The metal framework unit 1 includes master
Frame 4 and even foot 5, even foot 5 is set to the surrounding of main frame 4；The main frame 4 uses closed frame structure, main frame 4
Interior chamber size is greater than the size of chip 2, and main frame 4 surrounds chip 2；In the present embodiment, as shown in Fig. 2, the main frame 4 is adopted
With rectangular-ambulatory-plane structure, but it is not limited solely to rectangular-ambulatory-plane.
As shown in Fig. 2, the even foot 5 is set to the outside surrounding of main frame 4, when smaller for chip size, surrounding
Even foot 5 can be less, and 2 company's feet 5 are arranged in the every side of main frame 4；When larger for chip size, the every side of main frame 4 setting 3
A even foot 5, and suitably increase the width of each even foot 5.Specifically, the hole size parameter of the main frame 4 is according to chip 2
Size determines that the external dimensions of main frame 4 is determined according to 2 arrangement mode of chip and final encapsulation dimension synthesis, specific at one
In embodiment, using 3.3mm × 2.7mm × 0.36mm chip, the metal framework unit 1 of use is main with a thickness of 0.05mm
The frame width of frame 4 is 0.03mm, and a length of 4.5mm outside the frame of main frame 4, even the width of foot 5 is 0.03mm, after encapsulation
Encapsulating structure size be 6mm × 6mm × 0.63mm.
In a particular application, the thickness of the metal framework unit 1 is less than the thickness of chip 2, according to different chip rulers
Very little and arrangement mode, larger-size metal framework unit 1 can be obtained directly by way of machining, for smaller size
Metal framework unit 1, can pass through etching the methods of obtain.
The metal material thermal expansion coefficient that wafer-level packaging of the present invention metal framework uses is higher than plastic packaging material
Thermal expansion coefficient.
Packaging technology is fanned out to using the wafer scale of wafer architecture of the present invention, specifically includes the following steps:
(1) interim bonding film is mounted on substrate；
(2) as shown in figure 3, on interim bonding film uniform affixed metal frame structure 6, mechanical clamp, air-actuated jaw can be used
Etc. modes metal framework structure 6 is positioned after install；The metal framework structure 6 by several array arrangements metal frame
Frame unit 1 is constituted, and adjacent metal frame unit 1 is connected by even foot 5, and array manner and the arrangement mode of chip 2 are consistent；
The metal framework structure 6 can carry out another work according to chip size size, and larger-size metal framework structure 6 is directly
It is obtained by way of machining, the lesser metal framework structure 6 of size can be obtained by the methods of etching；
(3) pasting chip；The installation of chip is completed using modes such as mechanical clamp, air-actuated jaws, the installation site of chip is based on
The relative position of metal framework is installed, and can be improved the installation accuracy of chip；During load, the load of every chip piece
Load positioning is all carried out with the metal framework unit center where the chip；As shown in figure 4, to complete step (2) and step (3)
Afterwards, on substrate metal framework structure and chip layout, the mounting arrangement mode of the metal framework unit of metal framework structure
And number and the mounting arrangement mode and number of chip 2 are consistent；
(4) wafer scale injection molding reconstruct, i.e., realization metal framework is embedding, obtains wafer architecture of the present invention；
(5) substrate and interim bonding film are removed；
(6) wafer scale is routed again；
(7) ball is planted；
(8) scribing obtains the wafer-level packaging with wafer architecture of the present invention；In scribing processes, for different plastic packagings
The size of metal framework unit in disk should select the technological parameters such as suitable cutter and scribing speed.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (9)
1. a kind of wafer scale is fanned out to the wafer architecture of encapsulation, it is characterized in that: including metal framework unit (1), chip (2) and plastic packaging
Expect (3), the metal framework unit (1) and chip (2) plastic packaging are in plastic packaging material (3)；The metal framework unit (1) includes master
Frame (4) and company foot (5), even foot (5) are set to the surrounding of main frame (4)；The main frame (4) uses closed frame knot
Structure, main frame (4) surround chip (2).
2. wafer scale as described in claim 1 is fanned out to the wafer architecture of encapsulation, it is characterized in that: the main frame (4) every side
Setting 2-3 is even foot (5).
3. wafer scale as described in claim 1 is fanned out to the wafer architecture of encapsulation, it is characterized in that: the inside of the main frame (4)
Size is greater than the size of chip (2).
4. wafer scale as described in claim 1 is fanned out to the wafer architecture of encapsulation, it is characterized in that: the metal framework unit (1)
Thickness be less than chip (2) thickness.
5. wafer scale as described in claim 1 is fanned out to the wafer architecture of encapsulation, it is characterized in that: the main frame (4) is using envelope
The polygonal frame structure or circular frame structure closed.
6. wafer scale as claimed in claim 5 is fanned out to the wafer architecture of encapsulation, it is characterized in that: the main frame (4) uses square
Shape frame structure.
7. wafer scale as described in claim 1 is fanned out to the wafer architecture of encapsulation, it is characterized in that: the metal framework unit uses
Metal material thermal expansion coefficient be higher than plastic packaging material thermal expansion coefficient.
8. a kind of be fanned out to packaging technology using the wafer scale of wafer architecture as described in claim any one of 1-7, characterized in that packet
Include following steps:
(1) interim bonding film is mounted on substrate；
(2) affixed metal frame structure (6) on interim bonding film；The metal framework structure (6) is by several array arrangements
Metal framework unit (1) constitute, adjacent metal frame unit (1) by even foot (5) connect；The metal framework unit (1)
Array manner is consistent with chip (2) arrangement mode to be arranged；
(3) pasting chip, the installation site of chip are located at the inside of metal framework structure, by metal framework structure by chip packet
It encloses；During load, the load of every chip piece all carries out load positioning with the metal framework unit center where the chip；
(4) wafer scale injection molding reconstruct obtains wafer architecture by metal framework structure together with chip injection molding；
(5) substrate and interim bonding film are removed；
(6) wafer scale is routed again；
(7) ball is planted；
(8) scribing obtains wafer-level packaging.
9. wafer scale as claimed in claim 8 is fanned out to packaging technology, it is characterized in that: in the step (2), metal framework structure
(6) it is directly obtained by way of machining, or is obtained by lithographic method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811469838.XA CN109686716A (en) | 2018-11-28 | 2018-11-28 | Wafer scale is fanned out to the wafer architecture of encapsulation and is fanned out to packaging technology using the wafer scale of the wafer architecture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811469838.XA CN109686716A (en) | 2018-11-28 | 2018-11-28 | Wafer scale is fanned out to the wafer architecture of encapsulation and is fanned out to packaging technology using the wafer scale of the wafer architecture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109686716A true CN109686716A (en) | 2019-04-26 |
Family
ID=66186043
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811469838.XA Pending CN109686716A (en) | 2018-11-28 | 2018-11-28 | Wafer scale is fanned out to the wafer architecture of encapsulation and is fanned out to packaging technology using the wafer scale of the wafer architecture |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109686716A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103904044A (en) * | 2014-04-02 | 2014-07-02 | 华进半导体封装先导技术研发中心有限公司 | Fan-out wafer-level packaging structure and manufacturing technology |
| CN105489516A (en) * | 2016-01-22 | 2016-04-13 | 中芯长电半导体（江阴）有限公司 | Packaging method of fan-out type chip, and packaging structure |
| CN107481977A (en) * | 2017-08-21 | 2017-12-15 | 华进半导体封装先导技术研发中心有限公司 | A kind of wafer scale fan-out package structure and method for packing |
-
2018
- 2018-11-28 CN CN201811469838.XA patent/CN109686716A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103904044A (en) * | 2014-04-02 | 2014-07-02 | 华进半导体封装先导技术研发中心有限公司 | Fan-out wafer-level packaging structure and manufacturing technology |
| CN105489516A (en) * | 2016-01-22 | 2016-04-13 | 中芯长电半导体（江阴）有限公司 | Packaging method of fan-out type chip, and packaging structure |
| CN107481977A (en) * | 2017-08-21 | 2017-12-15 | 华进半导体封装先导技术研发中心有限公司 | A kind of wafer scale fan-out package structure and method for packing |
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Application publication date: 20190426 |