WO2017024794A1

WO2017024794A1 - Wafer level chip encapsulation method

Info

Publication number: WO2017024794A1
Application number: PCT/CN2016/076235
Authority: WO
Inventors: 林正忠; 仇月东
Original assignee: 中芯长电半导体（江阴）有限公司
Priority date: 2015-08-12
Filing date: 2016-03-14
Publication date: 2017-02-16
Also published as: CN105161431A

Abstract

Provided is a wafer level chip encapsulation method, comprising:1) providing a first carrier (11) and a first adhesive layer (12), and adhering a semiconductor chip (13) to the first adhesive layer (12); 2) adopting injection molding process to encapsulate each semiconductor chip (13), so as to form an encapsulation layer (14); 3) removing the first carrier (11) and the first adhesive layer (12); 4) providing a second carrier (15) and a second adhesive layer (16), and adhering the encapsulation layer (14) to the second adhesive layer (16); 5) forming a dielectric layer (17) on the front side of each semiconductor chip (13), and manufacturing a redistribution layer (18) for each semiconductor chip (13) based on the dielectric layer (17); 6) performing a ball placement and reflow process on the redistribution layer (18) to form a microbump (19); and 7) removing the second carrier (15) and the second adhesive layer (16). By way of fixing a plastic encapsulated semiconductor chip onto a carrier again, the stability of a plastic encapsulation material can be increased, thereby avoiding the problem of the occurrence of deformation of the plastic encapsulation material during the subsequent redistribution process and ball placement process.

Description

Wafer level chip packaging method

Technical field

The invention belongs to the field of semiconductor manufacturing, and in particular to a wafer level chip packaging method.

Background technique

With the rapid development of the integrated circuit manufacturing industry, the requirements for packaging technology of integrated circuits are also increasing. The existing packaging technologies include ball grid array package (BGA), chip size package (CSP), and wafer level package (WLP). ), three-dimensional packaging (3D) and system packaging (SiP). Among them, the wafer-level package (WLP) is gradually adopted by most semiconductor manufacturers due to its excellent advantages. All or most of the process steps are completed on the silicon wafer that has completed the pre-process, and finally the wafer is finished. Cut directly into separate, independent devices. Wafer-level package (WLP) has its unique advantages: 1 package processing efficiency, can be processed simultaneously with multiple wafers; 2 with the advantages of flip chip packaging, namely light, thin, short, small; 3 and the previous process Than, just added two steps of pin rewiring (RDL) and bump fabrication, the rest are all traditional processes; 4 reduces the number of tests in traditional packages. Therefore, the world's major IC packaging companies have invested in the research, development and production of such WLP. The shortcomings of WLP are that the current pin count is low and there is no standardization and high cost. The key technologies involved in WLP include re-wiring (RDL) technology and bump fabrication techniques in addition to the metal deposition techniques, lithography, and etching techniques necessary for the previous process. Usually the lead pads on the chip are square aluminum layers that are routed around the die. In order to adapt the WLP to the wider pad pitch of the SMT secondary package, these pads need to be redistributed so that these pads are The peripheral arrangement of the chip is changed to the array arrangement on the active side of the chip, which requires rewiring (RDL) technology.

The rewiring layer (RDL) is the interface between the chip and the package in the flip chip assembly. The rewiring layer is an additional metal layer consisting of core metal top traces that are used to bond the die's I/O pads outward to other locations such as bump pads. The bumps are usually arranged in a grid pattern, and each bump is cast with two pads (one at the top and one at the bottom) which are connected to the rewiring layer and the package substrate, respectively.

The existing fan-out chip packaging technology often faces a prominent problem: assembly deformation. In the prior art, the semiconductor chip is generally attached to the film of the carrier face down, and then plastic-sealed, and the carrier and the film are removed after plastic sealing. In the subsequent rewiring layer process and the ball reflow process, the molding material tends to be deformed and bent, which greatly affects the performance of the packaged product.

In order to overcome the above drawbacks, a conventional solution is to assemble the semiconductor chip face up in the molding material. Since the molding material is supported by the rigid carrier, this method can greatly reduce the subsequent rewiring layer process. And the deformation probability of the molding material caused by the ball placement process. However, this method requires some process steps such as grinding and thinning, which leads to an increase in product cost.

In view of the above reasons, it is necessary to provide a wafer level chip packaging method which avoids the problem that the molding material is easily deformed during the rewiring and ball placement process without increasing the product cost.

Summary of the invention

In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a wafer level chip packaging method for solving the problem that the molding material is easily deformed during the rewiring and ball placement process in the prior art.

To achieve the above and other related objects, the present invention provides a wafer level chip packaging method, the wafer level chip packaging method comprising the steps of: 1) providing a first carrier, the first carrier surface having a first bond a layer, the semiconductor chip is adhered face down on the surface of the first adhesive layer; 2) each semiconductor chip is packaged by an injection molding process to form an encapsulation layer; 3) separating the first adhesive layer and each semiconductor chip And removing the first carrier and the first adhesive layer; 4) providing a second carrier, the second carrier surface having a second adhesive layer, bonding the encapsulation layer to the second adhesive layer And making each semiconductor chip face up; 5) forming a dielectric layer on the front side of each semiconductor chip, and forming a rewiring layer on each semiconductor chip based on the dielectric layer; 6) performing a ball reflow process on the rewiring layer Forming microbumps; 7) separating the second adhesive layer and the encapsulation layer to remove the second carrier and the second adhesive layer.

As a preferred embodiment of the wafer level chip packaging method of the present invention, the semiconductor chip is a fan-out type semiconductor chip.

As a preferred embodiment of the wafer level chip packaging method of the present invention, the first carrier comprises one of glass, semiconductor, metal, and a rigid polymer.

As a preferred embodiment of the wafer level chip packaging method of the present invention, the first adhesive layer is a double-sided adhesive tape or an adhesive made by a spin coating process, the first adhesive layer The separation method from each semiconductor chip includes a chemical solvent method, a UV light exposure method, or a heat insulation method.

As a preferred embodiment of the wafer level chip packaging method of the present invention, the second carrier comprises one of glass, semiconductor, metal, and a rigid polymer.

As a preferred embodiment of the wafer level chip packaging method of the present invention, the second adhesive layer is a double-sided adhesive tape or an adhesive made by a spin coating process, the second adhesive layer The separation method from the encapsulation layer includes a chemical solvent method, a UV light exposure method, or a heat insulation method.

As a preferred embodiment of the wafer level chip packaging method of the present invention, the packaging material used in the injection molding process of step 2) is a polymer composite material. The polymer composite material may be a material such as a filled epoxy resin and a filled epoxy acrylate resin.

As a preferred solution of the wafer level chip packaging method of the present invention, step 5) comprises the following steps: 5-1) adopting a deposition process forms a dielectric layer on the front surface of each semiconductor chip; 5-2) forming a via hole corresponding to the electrical extraction of the semiconductor chip in the dielectric layer by a photolithography process and an etching process; 5-3) The hole is filled with a metal conductor to form a connection via; 5-4) is formed on the surface of the dielectric layer to form a rewiring layer correspondingly connected to the connection via.

Further, the step 5-4) comprises the steps of: 5-4 a) forming a photoresist pattern on the surface of the dielectric layer; 5-4 b) depositing or sputtering a seed on the surface of the dielectric layer based on the photoresist pattern a layer; 5-4c) forming a metal wiring by plating a metal conductor based on the seed layer; 5-4d) removing the photoresist pattern to form a rewiring layer.

As described above, the wafer level chip packaging method of the present invention has the following advantageous effects: the present invention re-fixes the plasticized semiconductor chip to the carrier to enhance the stability of the molding material and prevent the subsequent rewiring of the molding material. Deformation problems occur during the process and the ball placement process. By adopting the packaging method of the invention, the deformation condition of the plastic sealing material can be well controlled, the product yield is greatly improved, and the cost of the product can be saved. The invention has simple steps and can greatly improve the yield of the product, and has wide application prospects in the field of semiconductor manufacturing.

DRAWINGS

FIG. 1 is a flow chart showing the steps of a wafer level chip packaging method of the present invention.

2 to FIG. 11 are schematic diagrams showing the steps of the steps of the wafer level chip packaging method of the present invention.

Component label description

11 first carrier

12 first adhesive layer

13 semiconductor chip

14 encapsulation layer

15 second carrier

16 second adhesive layer

17 dielectric layer

18 rewiring layer

19 micro bumps

S11～S17 Step 1)～Step 7)

detailed description

The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. The invention may also be added by other different embodiments The details of the present invention can be variously modified or changed without departing from the spirit and scope of the invention.

Please refer to Figure 1 to Figure 11. It should be noted that the illustrations provided in the embodiments merely illustrate the basic concept of the present invention in a schematic manner, and only the components related to the present invention are shown in the drawings, rather than the number and shape of components in actual implementation. Dimensional drawing, the actual type of implementation of each component's type, number and proportion can be a random change, and its component layout can be more complicated.

As shown in FIG. 1 to FIG. 11 , the embodiment provides a wafer level chip packaging method, and the wafer level chip packaging method includes the following steps:

As shown in FIG. 1 to FIG. 3, firstly, steps 1) to S11 are performed to provide a first carrier 11 having a first adhesive layer 12 on the surface thereof, and the semiconductor chip 13 is adhered face down on the first surface. An adhesive layer 12 surface.

The first carrier 11 may provide a rigid structure or substrate for the first adhesive layer 12 and the subsequent encapsulation layer 14. For example, the first carrier 11 may be selected from a suitable shape of glass, semiconductor (such as silicon). One of the metal, and a rigid polymer. In this embodiment, the first carrier 11 is selected as glass.

The first adhesive layer 12 is preferably made of an adhesive material having a smooth surface, which must have a certain bonding force with the semiconductor chip 13 to ensure that the semiconductor chip 13 does not move during subsequent processes, and It may have a strong bonding force with the first carrier 11. Generally, its bonding force with the first carrier 11 needs to be greater than the bonding force with the semiconductor chip 13, and the first bonding layer 12 is in a subsequent process. Used in the separation layer between the semiconductor chip 13 and the first carrier 11. The first adhesive layer is an adhesive tape which is adhesive on both sides, or an adhesive which is produced by a spin coating process. As an example, the first adhesive layer 12 is a UV adhesive that is formed on the surface of the first carrier 11 by a spin coating process.

In the present embodiment, the front surface of the semiconductor chip 13 is a side on which the semiconductor chip 13 is formed with a device and an electrode.

In the embodiment, the semiconductor chip 13 is a fan-out type semiconductor chip. Of course, in other embodiments, the packaging method of the present invention can also be used to install devices such as memory devices, display devices, input components, discrete components, power supplies, voltage regulators, etc., and is not limited to the ones listed herein. An example.

As shown in FIGS. 1 and 4, steps 2) S12 are then performed, and each semiconductor chip 13 is packaged by an injection molding process to form an encapsulation layer 14.

As an example, the encapsulating material used in the injection molding process is a polymer composite material, specifically an opaque polymer composite material. Further, the polymer composite material comprises a material such as a filled epoxy resin and a filled epoxy acrylate resin. In this embodiment, the encapsulating material is a filled epoxy resin. The encapsulation layer 14 is used to fix the semiconductor chip 13 in a subsequent process.

As shown in FIGS. 1 and 5, steps 3) S13 are subsequently performed to separate the first adhesive layer 12 and each of the semiconductor chips 13 to remove the first carrier 11 and the first adhesive layer 12.

Generally, the method of separating the first adhesive layer from each of the semiconductor chips includes a chemical solvent method, a UV light exposure method, or a heat insulation method. In this embodiment, the first adhesive layer 12 (UV adhesive) is reduced in viscosity by an exposure method to achieve separation from the semiconductor chips to finally remove the first carrier 11 and the first Adhesive layer 12.

As shown in FIG. 1 and FIG. 6, step 4) S14 is then performed to provide a second carrier 15 having a second adhesive layer 16 on the surface thereof, and bonding the encapsulation layer 14 to the second layer The adhesive layer 16 is bonded with the semiconductor chips 13 facing upward.

The second carrier 15 may provide a rigid structure or substrate for the second adhesive layer 16 and the subsequent encapsulation layer 14. For example, the second carrier 15 may be selected from a suitable shape of glass, semiconductor (such as silicon). One of the metal, and a rigid polymer. In this embodiment, the second carrier 15 is selected as glass.

The second adhesive layer 16 is preferably made of an adhesive material having a smooth surface, which must have a certain bonding force with the encapsulation layer 14, and further, it can have a strong bonding force with the second carrier 15. In general, its bonding force with the second carrier 15 needs to be greater than the bonding force with the encapsulation layer 14, and the second adhesive layer 16 is used in the subsequent process for the encapsulation layer 14 and the second carrier. Separation layer between 15 The second adhesive layer is an adhesive tape which is adhesive on both sides, or an adhesive which is produced by a spin coating process. As an example, the second adhesive layer 16 is a UV adhesive formed on the surface of the second carrier 15 by a spin coating process.

As shown in FIGS. 1 and 7 to 8, step 5) S15 is performed, a dielectric layer 17 is formed on the front surface of each semiconductor chip 13, and a rewiring layer 18 is formed on each semiconductor chip 13 based on the dielectric layer 17.

As an example, the following steps are specifically included:

Step 5-1), a dielectric layer 17 is formed on the front surface of each of the semiconductor chips 13 by a deposition process. The dielectric layer 17 includes one of silicon dioxide and silicon nitride. In the present embodiment, the dielectric layer 17 is silicon dioxide, which can be formed on the semiconductor chip 13 by, for example, a vapor deposition method. Of course, other dielectric layers 17 are equally applicable and are not limited to the examples listed herein.

Step 5-2), a through hole corresponding to the electrical extraction of the semiconductor chip 13 is formed in the dielectric layer 17 by a photolithography process and an etching process.

Step 5-3), filling each of the through holes with a metal conductor to form a connection through hole.

As an example, the metal conductor includes a metal material such as Cu, Al, or the like, and may be filled in the through hole by, for example, a deposition, electroplating-process to form a connection via. In this embodiment, the metal conductor is Cu.

Step 5-4) is formed on the surface of the dielectric layer 17 on the rewiring layer 18 corresponding to the connection via.

In this embodiment, step 5-4) specifically includes the following steps:

Step 5-4a), forming a photoresist pattern on the surface of the dielectric layer 17.

Step 5-4b) depositing or sputtering a seed layer on the surface of the dielectric layer 17 based on the photoresist pattern. In this embodiment, the seed layer is a Ti/Cu layer.

Step 5-4c), forming a metal wire by plating a metal conductor based on the seed layer.

Step 5-4d), the photoresist pattern is removed to form the rewiring layer 18.

As shown in FIG. 1 and FIG. 9, then step 6) S16, performing a ball reflow process on the rewiring layer 18 to form microbumps 19;

As shown in FIGS. 1 and 10 to 11, finally, steps 7) to S17 are performed to separate the second adhesive layer 16 and the encapsulation layer 14 to remove the second carrier 15 and the second adhesive layer 16.

Generally, the method for separating the second adhesive layer from the encapsulation layer includes a chemical solvent method, a UV light exposure method, or a heat insulation method. In this embodiment, the second adhesive layer 16 (UV adhesive) is reduced in viscosity by an exposure method to achieve separation from the encapsulation layer 14 to finally remove the second carrier 15 and The second adhesive layer 16 is.

As described above, the present invention provides a wafer level chip packaging method including the steps of: 1) providing a first carrier 11 having a first adhesive layer 12 on its surface, The semiconductor chip 13 is adhered face down on the surface of the first adhesive layer 12; 2) each semiconductor chip 13 is packaged by an injection molding process to form an encapsulation layer 14; 3) separating the first adhesive layer 12 and Each of the semiconductor chips 13 to remove the first carrier 11 and the first adhesive layer 12; 4) to provide a second carrier 15 having a second adhesive layer 16 on the surface thereof, the encapsulation layer 14 Bonding to the second adhesive layer 16 and facing each semiconductor chip 13 upward; 5) forming a dielectric layer 17 on the front surface of each semiconductor chip 13, and rewiring each semiconductor chip 13 based on the dielectric layer 17 a layer 18; 6) performing a ball reflow process on the rewiring layer 18 to form microbumps 19; 7) separating the second adhesive layer 16 and the encapsulation layer 14 to remove the second carrier 15 and The second adhesive layer 16 is. The invention re-fixes the plasticized semiconductor chip 13 on the carrier to strengthen the stability of the molding material, and avoids the problem that the molding material may be deformed in the subsequent rewiring process and the ball-planting process. By adopting the packaging method of the invention, the deformation condition of the plastic sealing material can be well controlled, the product yield is greatly improved, and the cost of the product can be saved. The invention has simple steps and can greatly improve the yield of the product, and has wide application prospects in the field of semiconductor manufacturing. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications or variations of the above-described embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, all that is accomplished by those of ordinary skill in the art without departing from the spirit and scope of the invention disclosed herein Modifications or modifications are still covered by the claims of the present invention.

Claims

A wafer level chip packaging method, characterized in that the wafer level chip packaging method comprises the steps of:

1) providing a first carrier, the first carrier surface having a first adhesive layer, the semiconductor chip is adhered face down on the surface of the first adhesive layer;

2) packaging each semiconductor chip by an injection molding process to form an encapsulation layer;

3) separating the first adhesive layer and each semiconductor chip to remove the first carrier and the first adhesive layer;

4) providing a second carrier, the second carrier surface having a second adhesive layer, bonding the encapsulation layer to the second adhesive layer, and facing each semiconductor chip face up;

5) forming a dielectric layer on a front surface of each semiconductor chip, and fabricating a rewiring layer for each semiconductor chip based on the dielectric layer;

6) performing a ball reflow process on the rewiring layer to form micro bumps;

7) separating the second adhesive layer and the encapsulation layer to remove the second carrier and the second adhesive layer.
The wafer level chip packaging method according to claim 1, wherein the semiconductor chip is a fan-out type semiconductor chip.
The wafer level chip packaging method according to claim 1, wherein the first carrier comprises one of a glass, a semiconductor, a metal, and a rigid polymer.
The wafer level chip packaging method according to claim 1, wherein the first adhesive layer is a double-sided adhesive tape or an adhesive made by a spin coating process, the first adhesive The method of separating the layer and each semiconductor chip includes a chemical solvent method, a UV light exposure method, or a heat insulation method.
The wafer level chip packaging method according to claim 1, wherein the second carrier comprises one of a glass, a semiconductor, a metal, and a rigid polymer.
The wafer level chip packaging method according to claim 1, wherein the second adhesive layer is a double-sided adhesive tape or an adhesive made by a spin coating process, the second adhesive The separation method of the layer and the encapsulation layer includes a chemical solvent method, a UV light exposure method, or a heat insulation method.
The wafer level chip packaging method according to claim 1, wherein the step of the injection molding process of step 2) is The material is a polymer composite material, including one of a filled epoxy resin and a filled epoxy acrylate resin.
The wafer level chip packaging method according to claim 1, wherein the step 5) comprises the following steps:

5-1) forming a dielectric layer on the front side of each semiconductor chip by a deposition process;

5-2) forming a via hole corresponding to the electrical extraction of the semiconductor chip in the dielectric layer by using a photolithography process and an etching process;

5-3) filling a metal conductor in each of the through holes to form a connecting through hole;

5-4) forming a rewiring layer corresponding to the connection via hole on the surface of the dielectric layer.
The wafer level chip packaging method according to claim 8, wherein the step 5-4) comprises the following steps:

5-4a) forming a photoresist pattern on the surface of the dielectric layer;

5-4b) depositing or sputtering a seed layer on the surface of the dielectric layer based on the photoresist pattern;

5-4c) forming a metal wire by plating a metal conductor based on the seed layer;

5-4d) removing the photoresist pattern to form a rewiring layer.