WO2017024794A1 - Procédé d'encapsulation de puce au niveau tranche de semi-conducteur - Google Patents

Procédé d'encapsulation de puce au niveau tranche de semi-conducteur Download PDF

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Publication number
WO2017024794A1
WO2017024794A1 PCT/CN2016/076235 CN2016076235W WO2017024794A1 WO 2017024794 A1 WO2017024794 A1 WO 2017024794A1 CN 2016076235 W CN2016076235 W CN 2016076235W WO 2017024794 A1 WO2017024794 A1 WO 2017024794A1
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Prior art keywords
layer
semiconductor chip
carrier
adhesive layer
wafer level
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PCT/CN2016/076235
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English (en)
Chinese (zh)
Inventor
林正忠
仇月东
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中芯长电半导体（江阴）有限公司
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Publication of WO2017024794A1 publication Critical patent/WO2017024794A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages

Definitions

  • the invention belongs to the field of semiconductor manufacturing, and in particular to a wafer level chip packaging method.
  • the existing packaging technologies include ball grid array package (BGA), chip size package (CSP), and wafer level package (WLP). ), three-dimensional packaging (3D) and system packaging (SiP).
  • BGA ball grid array package
  • CSP chip size package
  • WLP wafer level package
  • 3D three-dimensional packaging
  • SiP system packaging
  • the wafer-level package (WLP) is gradually adopted by most semiconductor manufacturers due to its excellent advantages. All or most of the process steps are completed on the silicon wafer that has completed the pre-process, and finally the wafer is finished. Cut directly into separate, independent devices.
  • Wafer-level package has its unique advantages: 1 package processing efficiency, can be processed simultaneously with multiple wafers; 2 with the advantages of flip chip packaging, namely light, thin, short, small; 3 and the previous process Than, just added two steps of pin rewiring (RDL) and bump fabrication, the rest are all traditional processes; 4 reduces the number of tests in traditional packages. Therefore, the world's major IC packaging companies have invested in the research, development and production of such WLP.
  • the shortcomings of WLP are that the current pin count is low and there is no standardization and high cost.
  • the key technologies involved in WLP include re-wiring (RDL) technology and bump fabrication techniques in addition to the metal deposition techniques, lithography, and etching techniques necessary for the previous process.
  • the lead pads on the chip are square aluminum layers that are routed around the die. In order to adapt the WLP to the wider pad pitch of the SMT secondary package, these pads need to be redistributed so that these pads are The peripheral arrangement of the chip is changed to the array arrangement on the active side of the chip, which requires rewiring (RDL) technology.
  • RDL rewiring
  • the rewiring layer is the interface between the chip and the package in the flip chip assembly.
  • the rewiring layer is an additional metal layer consisting of core metal top traces that are used to bond the die's I/O pads outward to other locations such as bump pads.
  • the bumps are usually arranged in a grid pattern, and each bump is cast with two pads (one at the top and one at the bottom) which are connected to the rewiring layer and the package substrate, respectively.
  • the existing fan-out chip packaging technology often faces a prominent problem: assembly deformation.
  • the semiconductor chip is generally attached to the film of the carrier face down, and then plastic-sealed, and the carrier and the film are removed after plastic sealing.
  • the molding material tends to be deformed and bent, which greatly affects the performance of the packaged product.
  • a conventional solution is to assemble the semiconductor chip face up in the molding material. Since the molding material is supported by the rigid carrier, this method can greatly reduce the subsequent rewiring layer process. And the deformation probability of the molding material caused by the ball placement process. However, this method requires some process steps such as grinding and thinning, which leads to an increase in product cost.
  • the object of the present invention is to provide a wafer level chip packaging method for solving the problem that the molding material is easily deformed during the rewiring and ball placement process in the prior art.
  • the present invention provides a wafer level chip packaging method, the wafer level chip packaging method comprising the steps of: 1) providing a first carrier, the first carrier surface having a first bond a layer, the semiconductor chip is adhered face down on the surface of the first adhesive layer; 2) each semiconductor chip is packaged by an injection molding process to form an encapsulation layer; 3) separating the first adhesive layer and each semiconductor chip And removing the first carrier and the first adhesive layer; 4) providing a second carrier, the second carrier surface having a second adhesive layer, bonding the encapsulation layer to the second adhesive layer And making each semiconductor chip face up; 5) forming a dielectric layer on the front side of each semiconductor chip, and forming a rewiring layer on each semiconductor chip based on the dielectric layer; 6) performing a ball reflow process on the rewiring layer Forming microbumps; 7) separating the second adhesive layer and the encapsulation layer to remove the second carrier and the second adhesive layer.
  • the semiconductor chip is a fan-out type semiconductor chip.
  • the first carrier comprises one of glass, semiconductor, metal, and a rigid polymer.
  • the first adhesive layer is a double-sided adhesive tape or an adhesive made by a spin coating process, the first adhesive layer
  • the separation method from each semiconductor chip includes a chemical solvent method, a UV light exposure method, or a heat insulation method.
  • the second carrier comprises one of glass, semiconductor, metal, and a rigid polymer.
  • the second adhesive layer is a double-sided adhesive tape or an adhesive made by a spin coating process
  • the second adhesive layer The separation method from the encapsulation layer includes a chemical solvent method, a UV light exposure method, or a heat insulation method.
  • the packaging material used in the injection molding process of step 2) is a polymer composite material.
  • the polymer composite material may be a material such as a filled epoxy resin and a filled epoxy acrylate resin.
  • step 5) comprises the following steps: 5-1) adopting a deposition process forms a dielectric layer on the front surface of each semiconductor chip; 5-2) forming a via hole corresponding to the electrical extraction of the semiconductor chip in the dielectric layer by a photolithography process and an etching process; 5-3) The hole is filled with a metal conductor to form a connection via; 5-4) is formed on the surface of the dielectric layer to form a rewiring layer correspondingly connected to the connection via.
  • the step 5-4) comprises the steps of: 5-4 a) forming a photoresist pattern on the surface of the dielectric layer; 5-4 b) depositing or sputtering a seed on the surface of the dielectric layer based on the photoresist pattern a layer; 5-4c) forming a metal wiring by plating a metal conductor based on the seed layer; 5-4d) removing the photoresist pattern to form a rewiring layer.
  • the wafer level chip packaging method of the present invention has the following advantageous effects: the present invention re-fixes the plasticized semiconductor chip to the carrier to enhance the stability of the molding material and prevent the subsequent rewiring of the molding material. Deformation problems occur during the process and the ball placement process.
  • the packaging method of the invention By adopting the packaging method of the invention, the deformation condition of the plastic sealing material can be well controlled, the product yield is greatly improved, and the cost of the product can be saved.
  • the invention has simple steps and can greatly improve the yield of the product, and has wide application prospects in the field of semiconductor manufacturing.
  • FIG. 1 is a flow chart showing the steps of a wafer level chip packaging method of the present invention.
  • FIG. 2 to FIG. 11 are schematic diagrams showing the steps of the steps of the wafer level chip packaging method of the present invention.
  • the embodiment provides a wafer level chip packaging method, and the wafer level chip packaging method includes the following steps:
  • steps 1) to S11 are performed to provide a first carrier 11 having a first adhesive layer 12 on the surface thereof, and the semiconductor chip 13 is adhered face down on the first surface.
  • the first carrier 11 may provide a rigid structure or substrate for the first adhesive layer 12 and the subsequent encapsulation layer 14.
  • the first carrier 11 may be selected from a suitable shape of glass, semiconductor (such as silicon). One of the metal, and a rigid polymer. In this embodiment, the first carrier 11 is selected as glass.
  • the first adhesive layer 12 is preferably made of an adhesive material having a smooth surface, which must have a certain bonding force with the semiconductor chip 13 to ensure that the semiconductor chip 13 does not move during subsequent processes, and It may have a strong bonding force with the first carrier 11. Generally, its bonding force with the first carrier 11 needs to be greater than the bonding force with the semiconductor chip 13, and the first bonding layer 12 is in a subsequent process. Used in the separation layer between the semiconductor chip 13 and the first carrier 11.
  • the first adhesive layer is an adhesive tape which is adhesive on both sides, or an adhesive which is produced by a spin coating process.
  • the first adhesive layer 12 is a UV adhesive that is formed on the surface of the first carrier 11 by a spin coating process.
  • the front surface of the semiconductor chip 13 is a side on which the semiconductor chip 13 is formed with a device and an electrode.
  • the semiconductor chip 13 is a fan-out type semiconductor chip.
  • the packaging method of the present invention can also be used to install devices such as memory devices, display devices, input components, discrete components, power supplies, voltage regulators, etc., and is not limited to the ones listed herein. An example.
  • steps 2) S12 are then performed, and each semiconductor chip 13 is packaged by an injection molding process to form an encapsulation layer 14.
  • the encapsulating material used in the injection molding process is a polymer composite material, specifically an opaque polymer composite material.
  • the polymer composite material comprises a material such as a filled epoxy resin and a filled epoxy acrylate resin.
  • the encapsulating material is a filled epoxy resin.
  • the encapsulation layer 14 is used to fix the semiconductor chip 13 in a subsequent process.
  • steps 3) S13 are subsequently performed to separate the first adhesive layer 12 and each of the semiconductor chips 13 to remove the first carrier 11 and the first adhesive layer 12.
  • the method of separating the first adhesive layer from each of the semiconductor chips includes a chemical solvent method, a UV light exposure method, or a heat insulation method.
  • the first adhesive layer 12 (UV adhesive) is reduced in viscosity by an exposure method to achieve separation from the semiconductor chips to finally remove the first carrier 11 and the first Adhesive layer 12.
  • step 4) S14 is then performed to provide a second carrier 15 having a second adhesive layer 16 on the surface thereof, and bonding the encapsulation layer 14 to the second layer
  • the adhesive layer 16 is bonded with the semiconductor chips 13 facing upward.
  • the second carrier 15 may provide a rigid structure or substrate for the second adhesive layer 16 and the subsequent encapsulation layer 14.
  • the second carrier 15 may be selected from a suitable shape of glass, semiconductor (such as silicon). One of the metal, and a rigid polymer. In this embodiment, the second carrier 15 is selected as glass.
  • the second adhesive layer 16 is preferably made of an adhesive material having a smooth surface, which must have a certain bonding force with the encapsulation layer 14, and further, it can have a strong bonding force with the second carrier 15. In general, its bonding force with the second carrier 15 needs to be greater than the bonding force with the encapsulation layer 14, and the second adhesive layer 16 is used in the subsequent process for the encapsulation layer 14 and the second carrier. Separation layer between 15
  • the second adhesive layer is an adhesive tape which is adhesive on both sides, or an adhesive which is produced by a spin coating process.
  • the second adhesive layer 16 is a UV adhesive formed on the surface of the second carrier 15 by a spin coating process.
  • step 5 S15 is performed, a dielectric layer 17 is formed on the front surface of each semiconductor chip 13, and a rewiring layer 18 is formed on each semiconductor chip 13 based on the dielectric layer 17.
  • a dielectric layer 17 is formed on the front surface of each of the semiconductor chips 13 by a deposition process.
  • the dielectric layer 17 includes one of silicon dioxide and silicon nitride.
  • the dielectric layer 17 is silicon dioxide, which can be formed on the semiconductor chip 13 by, for example, a vapor deposition method.
  • other dielectric layers 17 are equally applicable and are not limited to the examples listed herein.
  • Step 5-2 a through hole corresponding to the electrical extraction of the semiconductor chip 13 is formed in the dielectric layer 17 by a photolithography process and an etching process.
  • Step 5-3) filling each of the through holes with a metal conductor to form a connection through hole.
  • the metal conductor includes a metal material such as Cu, Al, or the like, and may be filled in the through hole by, for example, a deposition, electroplating-process to form a connection via.
  • the metal conductor is Cu.
  • Step 5-4) is formed on the surface of the dielectric layer 17 on the rewiring layer 18 corresponding to the connection via.
  • step 5-4) specifically includes the following steps:
  • Step 5-4a forming a photoresist pattern on the surface of the dielectric layer 17.
  • the seed layer is a Ti/Cu layer.
  • Step 5-4c) forming a metal wire by plating a metal conductor based on the seed layer.
  • Step 5-4d the photoresist pattern is removed to form the rewiring layer 18.
  • step 6 S16, performing a ball reflow process on the rewiring layer 18 to form microbumps 19;
  • steps 7) to S17 are performed to separate the second adhesive layer 16 and the encapsulation layer 14 to remove the second carrier 15 and the second adhesive layer 16.
  • the method for separating the second adhesive layer from the encapsulation layer includes a chemical solvent method, a UV light exposure method, or a heat insulation method.
  • the second adhesive layer 16 (UV adhesive) is reduced in viscosity by an exposure method to achieve separation from the encapsulation layer 14 to finally remove the second carrier 15 and The second adhesive layer 16 is.
  • the present invention provides a wafer level chip packaging method including the steps of: 1) providing a first carrier 11 having a first adhesive layer 12 on its surface, The semiconductor chip 13 is adhered face down on the surface of the first adhesive layer 12; 2) each semiconductor chip 13 is packaged by an injection molding process to form an encapsulation layer 14; 3) separating the first adhesive layer 12 and Each of the semiconductor chips 13 to remove the first carrier 11 and the first adhesive layer 12; 4) to provide a second carrier 15 having a second adhesive layer 16 on the surface thereof, the encapsulation layer 14 Bonding to the second adhesive layer 16 and facing each semiconductor chip 13 upward; 5) forming a dielectric layer 17 on the front surface of each semiconductor chip 13, and rewiring each semiconductor chip 13 based on the dielectric layer 17 a layer 18; 6) performing a ball reflow process on the rewiring layer 18 to form microbumps 19; 7) separating the second adhesive layer 16 and the encapsulation layer 14 to remove the second carrier 15 and The second adhesive layer 16 is.
  • the invention re-fixes the plasticized semiconductor chip 13 on the carrier to strengthen the stability of the molding material, and avoids the problem that the molding material may be deformed in the subsequent rewiring process and the ball-planting process.
  • the packaging method of the invention By adopting the packaging method of the invention, the deformation condition of the plastic sealing material can be well controlled, the product yield is greatly improved, and the cost of the product can be saved.
  • the invention has simple steps and can greatly improve the yield of the product, and has wide application prospects in the field of semiconductor manufacturing. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

L'invention concerne un procédé d'encapsulation de puce au niveau tranche de semi-conducteur, comprenant les étapes consistant : à 1) fournir un premier support (11) et une première couche d'adhésif (12), et fixer une puce à semi-conducteurs (13) à la première couche d'adhésif (12) ; 2) à adopter un processus de moulage par injection pour encapsuler chaque puce à semi-conducteurs (13), de manière à former une couche d'encapsulation (14) ; 3) à retirer le premier support (11) et la première couche d'adhésif (12) ; 4) à fournir un second support (15) et une seconde couche d'adhésif (16), et à fixer la couche d'encapsulation (14) à la seconde couche d'adhésif (16) ; 5) à former une couche diélectrique (17) sur le côté avant de chaque puce à semi-conducteurs (13), et à fabriquer une couche de redistribution (18) pour chaque puce à semi-conducteurs (13) sur la base de la couche diélectrique (17) ; 6) à effectuer un processus de placement et de refusion de balle sur la couche de redistribution (18) pour former une microbosse (19) ; et 7) à retirer le second support (15) et la seconde couche d'adhésif (16). Au moyen de la fixation d'une puce à semi-conducteurs encapsulée de matière plastique sur un support une nouvelle fois, la stabilité d'un matériau d'encapsulation en matière plastique peut être augmentée, ce qui permet d'éviter le problème de l'apparition d'une déformation du matériau d'encapsulation en matière plastique pendant le processus de redistribution ultérieur et le processus de placement de balle.
PCT/CN2016/076235 2015-08-12 2016-03-14 Procédé d'encapsulation de puce au niveau tranche de semi-conducteur WO2017024794A1 (fr)

Applications Claiming Priority (2)

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CN201510494161.5A CN105161431A (zh) 2015-08-12 2015-08-12 晶圆级芯片封装方法
CN201510494161.5 2015-08-12

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CN116053202A (zh) * 2023-02-11 2023-05-02 浙江嘉辰半导体有限公司 一种空腔结构晶圆级封装工艺方法

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TWI645523B (zh) * 2017-07-14 2018-12-21 矽品精密工業股份有限公司 封裝結構及其製法
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CN110148567A (zh) * 2019-06-06 2019-08-20 中芯长电半导体（江阴）有限公司 一种指纹识别芯片的封装结构及封装方法
CN110289219B (zh) * 2019-06-28 2021-07-06 广东工业大学 扇出型模块高压封装工艺、结构以及设备
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CN110571197A (zh) * 2019-08-07 2019-12-13 广东芯华微电子技术有限公司 一种多芯片嵌入式abf封装结构及其制造方法
CN112582287A (zh) * 2019-09-30 2021-03-30 中芯长电半导体（江阴）有限公司 晶圆级芯片封装结构及封装方法
CN113192850B (zh) * 2021-04-29 2023-09-01 长沙新雷半导体科技有限公司 一种扇出型芯片的封装方法
CN117198897A (zh) * 2022-06-01 2023-12-08 矽磐微电子(重庆)有限公司 半导体结构的板级封装方法

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