US20120129297A1 - Method of manufacturing wafer level package - Google Patents
Method of manufacturing wafer level package Download PDFInfo
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- US20120129297A1 US20120129297A1 US13/363,513 US201213363513A US2012129297A1 US 20120129297 A1 US20120129297 A1 US 20120129297A1 US 201213363513 A US201213363513 A US 201213363513A US 2012129297 A1 US2012129297 A1 US 2012129297A1
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present invention relates to a wafer level package and a method of manufacturing the same and a method of reusing a chip, and more particularly, to a wafer level package and a method of manufacturing the same and a method of reusing a chip capable of manufacturing the package by selecting only a good chip coated with an epoxy-based photoresist such as KMPR® by MicroChem Corp. (MCC) and reusing the good chip by removing the KMPR coated on the good chip if necessary after dicing a wafer into the individual packages.
- MCC MicroChem Corp.
- KMPR® brand photoresist is high contrast, i-line sensitive and can be developed in convention aqueous alkaline-based developers and also can be readily removed from the substrate.
- a conventional package has been manufactured in such a way of cutting a wafer including a plurality of chips along dicing lines to separate the wafer into the individual chips and then performing a packaging process for each chip.
- the packaging process includes a plurality of unit processes, for example, chip attaching, wire bonding, molding, trimming/forming and the like. Therefore, a conventional package manufacturing method in which the packaging process must be performed for each chip has a problem that it takes too long time to package all the chips in consideration of the number of the chips obtained from one wafer.
- a method of manufacturing a package by firstly performing a packaging process in a wafer level state and then dicing a wafer into individual packages.
- the package manufactured by this method is referred to as a wafer level package.
- the present invention has been proposed in order to solve the above-described problems, and it is, therefore, an object of the present invention to provide a wafer level package and a method of manufacturing the same and a method of reusing a chip capable of improving production yield of the wafer level package and reducing manufacturing cost thereof by selecting only a good chip to manufacture the package and reusing the good chip by removing KMPR® brand photoresist coated on the good chip if necessary.
- a wafer level package including a chip; a removable resin layer formed to surround side surfaces and a lower surface of the chip; a molding material formed on the lower surface of the removable resin layer; a dielectric layer formed over the removable resin layer including the chip and having via holes to expose portions of the chip; redistribution lines formed on the dielectric layer including insides of the via holes to be connected to the chip; and a solder resist layer formed on the dielectric layer to expose portions of the redistribution lines.
- the removable resin layer may be made of KMPR® brand photoresist.
- the wafer level package may further include a seed layer formed between the dielectric layer and the redistribution lines.
- the wafer level package may further include UBMs (Under Bump Metal) and solder balls sequentially formed on the redistribution lines exposed by the solder resist layer.
- UBMs Under Bump Metal
- the chip may be a good chip selected through a chip failure test.
- a method of manufacturing a wafer level package including the steps of: separating chips by dicing a wafer; forming a removable resin layer in a space between the separated chips and at upper parts thereof; separating the chips by dicing the removable resin layer; mounting the chips separated in a state of being surrounded by the removable resin layer, on a carrier plate; forming a molding material on the carrier plate to cover the removable resin layer; separating the carrier plate from the chips; forming a dielectric layer having redistribution lines connected to the chips, on the chips exposed by separating the carrier plate; and forming a solder resist layer on the dielectric layer to expose portions of the redistribution lines.
- the method may further include the step of rearranging the chips to be separated from one another by selecting only the chips determined as good through a chip failure test among the separated chips.
- only the chips determined as good through the chip failure test, among the chips separated in a state of being surrounded by the removable resin layer, can be selected to be mounted on the carrier plate on which an adhesion layer is formed.
- the removable resin layer may be made of KMPR® brand photoresist.
- the step of forming the dielectric layer including the redistribution lines connected to the chips, on the chips exposed by separating the carrier plate may include the steps of: forming the dielectric layer on the chips exposed by separating the carrier plate; forming via holes to expose portions of the chips by removing portions of the dielectric layer; forming a seed layer on the dielectric layer including insides of the via holes; forming a photoresist pattern on the seed layer to expose portions corresponding to the via holes; forming the redistribution lines by plating metal on the seed layer exposed by the photoresist pattern; removing the photoresist pattern; and removing portions of the seed layer exposed by removing the photoresist pattern.
- the method may further include the steps of: forming UBMs on the redistribution lines exposed by the solder resist layer; and forming solder balls on the UBMs.
- the method may further include the step of separating the chips into individual packages by cutting along dicing lines between the chips.
- a method of reusing a chip including the steps of: manufacturing an individual package by using a method of manufacturing a wafer level package; separating a molding material from a chip by removing a removable resin layer surrounding the chip; and removing a solder resist layer and a dielectric layer including redistribution lines on the chip.
- the removable resin layer may be made of KMPR® brand photoresist.
- the removable resin layer can be removed by using NMP (N-Methyl Pyrrolidone).
- FIG. 1 is a cross-sectional view illustrating a structure of a wafer level package in accordance with an embodiment of the present invention
- FIGS. 2 to 20 are plan views and cross-sectional views sequentially illustrating a method of manufacturing a wafer level package in accordance with another embodiment of the present invention.
- FIGS. 21 to 22 are cross-sectional views illustrating a method of reusing a chip in accordance with still another embodiment of the present invention.
- FIG. 1 is a cross-sectional view illustrating a structure of the wafer level package in accordance with the embodiment of the present invention.
- the wafer level package in accordance with the embodiment of the present invention includes a chip 10 , a removable resin layer 20 formed to surround side surfaces and a lower surface of the chip 10 , a molding material 32 formed on the lower surface of the removable resin layer 20 , a dielectric layer 33 formed over the removable resin layer 20 including the chip 10 and having via holes 34 to expose portions of the chip 10 , redistribution lines 37 formed on the dielectric layer 33 including insides of the via holes 34 to be connected to the chip 10 , and a solder resist layer 38 formed on the dielectric layer 33 to expose portions of the redistribution lines 37 .
- the chip 10 is a good chip selected through a chip failure test.
- the wafer level package in accordance with the embodiment of the present invention is packaged by using only the chip determined as good without using the chip determined as bad through the chip failure test of the chips separated through dicing of a wafer.
- the removable resin layer 20 surrounding the chip 10 may be made of resin such as KMPR® brand photoresist and the like, which is removable without damage to an adhered surface.
- the KMPR® brand photoresist can be cleanly removed without damage to the adhered surface by NMP (N-Methyl Pyrrolidone) and the like.
- the molding material 32 formed on the lower surface of the removable resin layer 20 may be made of EMC (Epoxy Molding Compound) and the like.
- a seed layer 35 is formed between the dielectric layer 33 and the redistribution lines 37 .
- the seed layer 35 may be formed by Cu electroless plating and the like.
- the redistribution lines 37 may be formed on the seed layer 35 by Cu electro plating and the like.
- UBMs (Under Bump Metal) 39 are formed on the redistribution lines 37 exposed by the solder resist layer 38 , and solder balls 40 are formed on the UBMs 39 .
- FIG. 1 a method of manufacturing a wafer level package shown in FIG. 1 in accordance with another embodiment of the present invention will be described in detail with reference to FIGS. 2 to 20 .
- FIGS. 2 to 20 are plan views and cross-sectional views sequentially illustrating the method of manufacturing the wafer level package in accordance with the embodiment of the present invention.
- chips 10 are separated by dicing a wafer 100 .
- a removable resin layer 20 is formed in a space between the separated chips 10 and at upper parts thereof and then cured.
- the removable resin layer 20 may be made of KMPR® brand photoresist and the like, and the KMPR® brand photoresist is formed by a method such as spin coating and the like. As described above, the KMPR® brand photoresist has an advantage of being removed without damage to an adhered surface.
- the chips 10 are separated by dicing the removable resin layer 20 .
- the carrier plate 30 may be made of porous ceramic and the like.
- an adhesion layer 31 is formed on the carrier plate 30 .
- the chips 10 which are separated in a state of being surrounded by the removable resin layer 20 , are mounted on the carrier plate 30 on which the adhesion layer 31 is formed.
- the chips 10 when mounting the chips 10 , it is preferable to select and mount only the chips determined as good through a chip failure test, among the chips 30 separated in a state of being surrounded by the removable resin layer 20 .
- the chips 10 are separated by dicing the wafer 100 as shown in FIG. 1 , and then the removable resin layer 20 may be formed in the space between the rearranged good chips 10 and at the upper parts thereof after selecting only the chips determined as good through the chip failure test among the separated chips 10 and rearranging the selected chips to be separated from one another. In this case, as shown in FIG.
- a molding material 32 is formed on the adhesion layer 31 to cover the removable resin layer 20 .
- the molding material 32 may be made of EMC and the like.
- the carrier plate 30 is separated from the chips 10 by dipping the porous ceramic carrier plate 30 in an organic solvent such as acetone and the like so that the organic solvent is absorbed through the porous ceramic carrier plate 30 to melt the adhesion layer 31 on the carrier plate 30 .
- an organic solvent such as acetone and the like
- a dielectric layer 33 is formed on the molding material 32 and the removable resin layer 20 including the chips 10 exposed by separating the carrier plate 30 .
- via holes 34 are formed to expose portions of the chips 10 by removing portions of the dielectric layer 33 .
- a seed layer 35 is formed on the dielectric layer 33 including insides of the via holes 34 by Cu electroless plating and the like.
- a photoresist pattern 36 is formed on the seed layer 35 to expose portions corresponding to the via holes 34 .
- the photoresist pattern 36 plays a role of a plating mask when plating redistribution lines 37 described later.
- the redistribution lines 37 are formed by plating metal on the seed layer 35 exposed by the photoresist pattern 36 .
- the redistribution lines 37 may be formed by Cu electro plating and the like.
- the photoresist pattern 36 is removed.
- portions of the seed layer 35 which are exposed by removing the photoresist pattern 36 , are removed by etching.
- portions of the redistribution lines 37 are exposed by removing portions of a solder resist layer 38 after forming the solder resist layer 38 on the dielectric layer 33 .
- solder balls 40 are formed on UBMs 39 after forming the UBMs 39 on the redistribution lines 37 exposed by the solder resist layer 38 .
- the chips 10 are separated into individual packages by cutting along dicing lines therebetween.
- the method of manufacturing the wafer level package in accordance with the embodiment of the present invention has effects of improving production yield of the wafer level package and reducing manufacturing cost thereof by selecting only the good chips 10 to manufacture the wafer level package.
- the method of manufacturing the wafer level package in accordance with the embodiment of the present invention can be applied to fan-out type wafer level packaging as well as chip size wafer level packaging.
- FIGS. 21 and 22 are cross-sectional views illustrating the method of reusing the chip in accordance with the embodiment of the present invention.
- individual packages are manufactured by a method of manufacturing a wafer level package in accordance with another embodiment of the present invention.
- All of the individual packages of the wafer level package in accordance with the embodiment of the present invention include good chips 10 .
- the chip 10 itself is a good chip, in case of separating and reusing only the chip 10 , there is an advantage of saving process cost and the like for manufacturing the good chip 10 .
- a molding material 32 is separated from the chip 10 by removing a removable resin layer 20 surrounding the chip 10 after manufacturing the individual package.
- the removable resin layer 20 surrounding the chip 10 is made of resin such as KMPR® brand photoresist and the like, which is removable without damage to an adhered surface, the molding material 32 can be removed without damage to a surface of the chip 10 through removal of the resin layer 20 .
- the removable resin layer 20 can be removed by NMP and the like.
- a solder resist layer 38 and a dielectric layer 33 including the redistribution lines 37 on the chip 10 are all removed.
- the dielectric layer 33 and the solder resist layer 38 can be removed by plasma etching and the like, and the redistribution lines 37 can be removed by a Cu etchant and the like.
- the wafer level package and the method of manufacturing the same and the method of reusing the chip in accordance with the present invention have effects of improving production yield of the wafer level package and reducing manufacturing cost thereof by selecting only the good chip to manufacture the wafer level package.
- the present invention has an advantage of reusing the good chip if necessary by separating the molding material from the good chip through removal of the removable resin layer surrounding the good chip.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A method of manufacturing a wafer level package including: separating chips by dicing a wafer; forming a removable resin layer in a space between the separated chips and at upper parts thereof; separating the chips by dicing the removable resin layer; mounting the chips separated in a state of being surrounded by the removable resin layer, on a carrier plate; forming a molding material on the carrier plate to cover the removable resin layer; separating the carrier plate from the chips; forming a dielectric layer having redistribution lines connected to the chips, on the chips exposed by separating the carrier plate; and forming a solder resist layer on the dielectric layer to expose portions of the redistribution lines.
Description
- This application is a U.S. divisional application filed under 37 CFR 1.53(b) claiming priority benefit of U.S. Ser. No. 12/318,752 filed in the United States on Jan. 7, 2009, which claims earlier priority benefit to Korean Patent Application No. 10-2008-0121660 filed with the Korean Intellectual Property Office on Dec. 3, 2008 the disclosures of which are incorporated herein by reference.
- 1. Field
- The present invention relates to a wafer level package and a method of manufacturing the same and a method of reusing a chip, and more particularly, to a wafer level package and a method of manufacturing the same and a method of reusing a chip capable of manufacturing the package by selecting only a good chip coated with an epoxy-based photoresist such as KMPR® by MicroChem Corp. (MCC) and reusing the good chip by removing the KMPR coated on the good chip if necessary after dicing a wafer into the individual packages. KMPR® brand photoresist is high contrast, i-line sensitive and can be developed in convention aqueous alkaline-based developers and also can be readily removed from the substrate.
- 2. Description of the Related Art
- A conventional package has been manufactured in such a way of cutting a wafer including a plurality of chips along dicing lines to separate the wafer into the individual chips and then performing a packaging process for each chip.
- However, the packaging process includes a plurality of unit processes, for example, chip attaching, wire bonding, molding, trimming/forming and the like. Therefore, a conventional package manufacturing method in which the packaging process must be performed for each chip has a problem that it takes too long time to package all the chips in consideration of the number of the chips obtained from one wafer.
- Accordingly, recently, there has been proposed a method of manufacturing a package by firstly performing a packaging process in a wafer level state and then dicing a wafer into individual packages. The package manufactured by this method is referred to as a wafer level package.
- However, in the conventional wafer level package, since all of good and bad chips are packaged in a wafer level and then diced into the individual packages without selecting and packaging only the good chip, it costs the same as the good chip to package the bad chip in a FAB process. Therefore, there have been problems such as a waste of packaging cost and reduction of production yield.
- The present invention has been proposed in order to solve the above-described problems, and it is, therefore, an object of the present invention to provide a wafer level package and a method of manufacturing the same and a method of reusing a chip capable of improving production yield of the wafer level package and reducing manufacturing cost thereof by selecting only a good chip to manufacture the package and reusing the good chip by removing KMPR® brand photoresist coated on the good chip if necessary.
- In accordance with an aspect of the present invention to achieve the object, there is provided a wafer level package including a chip; a removable resin layer formed to surround side surfaces and a lower surface of the chip; a molding material formed on the lower surface of the removable resin layer; a dielectric layer formed over the removable resin layer including the chip and having via holes to expose portions of the chip; redistribution lines formed on the dielectric layer including insides of the via holes to be connected to the chip; and a solder resist layer formed on the dielectric layer to expose portions of the redistribution lines.
- Here, the removable resin layer may be made of KMPR® brand photoresist.
- Also, the wafer level package may further include a seed layer formed between the dielectric layer and the redistribution lines.
- Also, the wafer level package may further include UBMs (Under Bump Metal) and solder balls sequentially formed on the redistribution lines exposed by the solder resist layer.
- Also, the chip may be a good chip selected through a chip failure test.
- And, in accordance with another aspect of the present invention to achieve the object, there is provided a method of manufacturing a wafer level package including the steps of: separating chips by dicing a wafer; forming a removable resin layer in a space between the separated chips and at upper parts thereof; separating the chips by dicing the removable resin layer; mounting the chips separated in a state of being surrounded by the removable resin layer, on a carrier plate; forming a molding material on the carrier plate to cover the removable resin layer; separating the carrier plate from the chips; forming a dielectric layer having redistribution lines connected to the chips, on the chips exposed by separating the carrier plate; and forming a solder resist layer on the dielectric layer to expose portions of the redistribution lines.
- Here, between the step of separating the chips by dicing the wafer and the step of forming the removable resin layer in the space between the separated chips and at the upper parts thereof, the method may further include the step of rearranging the chips to be separated from one another by selecting only the chips determined as good through a chip failure test among the separated chips.
- Also, in the step of mounting the chips separated in a state of being surrounded by the removable resin layer, only the chips determined as good through the chip failure test, among the chips separated in a state of being surrounded by the removable resin layer, can be selected to be mounted on the carrier plate on which an adhesion layer is formed.
- Also, the removable resin layer may be made of KMPR® brand photoresist.
- Also, the step of forming the dielectric layer including the redistribution lines connected to the chips, on the chips exposed by separating the carrier plate may include the steps of: forming the dielectric layer on the chips exposed by separating the carrier plate; forming via holes to expose portions of the chips by removing portions of the dielectric layer; forming a seed layer on the dielectric layer including insides of the via holes; forming a photoresist pattern on the seed layer to expose portions corresponding to the via holes; forming the redistribution lines by plating metal on the seed layer exposed by the photoresist pattern; removing the photoresist pattern; and removing portions of the seed layer exposed by removing the photoresist pattern.
- Also, after the step of forming the solder resist layer on the dielectric layer to expose the portions of the redistribution lines, the method may further include the steps of: forming UBMs on the redistribution lines exposed by the solder resist layer; and forming solder balls on the UBMs.
- Also, after the step of forming the solder balls, the method may further include the step of separating the chips into individual packages by cutting along dicing lines between the chips.
- And, in accordance with still another aspect of the present invention to achieve the object, there is provided a method of reusing a chip including the steps of: manufacturing an individual package by using a method of manufacturing a wafer level package; separating a molding material from a chip by removing a removable resin layer surrounding the chip; and removing a solder resist layer and a dielectric layer including redistribution lines on the chip.
- Here, the removable resin layer may be made of KMPR® brand photoresist.
- Also, in the step of separating the molding material from the chip by removing the removable resin layer surrounding the chip, the removable resin layer can be removed by using NMP (N-Methyl Pyrrolidone).
- These and/or other aspects and advantages of the present general inventive concept will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
-
FIG. 1 is a cross-sectional view illustrating a structure of a wafer level package in accordance with an embodiment of the present invention; -
FIGS. 2 to 20 are plan views and cross-sectional views sequentially illustrating a method of manufacturing a wafer level package in accordance with another embodiment of the present invention; and -
FIGS. 21 to 22 are cross-sectional views illustrating a method of reusing a chip in accordance with still another embodiment of the present invention. - Reference will now be made in detail to the embodiments of the present general inventive concept, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The embodiments are described below in order to explain the present general inventive concept by referring to the figures.
- First, a wafer level package in accordance with an embodiment of the present invention will be described in detail with reference to
FIG. 1 . -
FIG. 1 is a cross-sectional view illustrating a structure of the wafer level package in accordance with the embodiment of the present invention. - As shown in
FIG. 1 , the wafer level package in accordance with the embodiment of the present invention includes achip 10, aremovable resin layer 20 formed to surround side surfaces and a lower surface of thechip 10, amolding material 32 formed on the lower surface of theremovable resin layer 20, adielectric layer 33 formed over theremovable resin layer 20 including thechip 10 and having viaholes 34 to expose portions of thechip 10,redistribution lines 37 formed on thedielectric layer 33 including insides of thevia holes 34 to be connected to thechip 10, and a solder resistlayer 38 formed on thedielectric layer 33 to expose portions of theredistribution lines 37. - Here, the
chip 10 is a good chip selected through a chip failure test. - That is, the wafer level package in accordance with the embodiment of the present invention is packaged by using only the chip determined as good without using the chip determined as bad through the chip failure test of the chips separated through dicing of a wafer.
- The
removable resin layer 20 surrounding thechip 10 may be made of resin such as KMPR® brand photoresist and the like, which is removable without damage to an adhered surface. The KMPR® brand photoresist can be cleanly removed without damage to the adhered surface by NMP (N-Methyl Pyrrolidone) and the like. - The
molding material 32 formed on the lower surface of theremovable resin layer 20 may be made of EMC (Epoxy Molding Compound) and the like. - A
seed layer 35 is formed between thedielectric layer 33 and theredistribution lines 37. Theseed layer 35 may be formed by Cu electroless plating and the like. - Also, the
redistribution lines 37 may be formed on theseed layer 35 by Cu electro plating and the like. - UBMs (Under Bump Metal) 39 are formed on the
redistribution lines 37 exposed by thesolder resist layer 38, andsolder balls 40 are formed on the UBMs 39. - Hereinafter, a method of manufacturing a wafer level package shown in
FIG. 1 in accordance with another embodiment of the present invention will be described in detail with reference toFIGS. 2 to 20 . -
FIGS. 2 to 20 are plan views and cross-sectional views sequentially illustrating the method of manufacturing the wafer level package in accordance with the embodiment of the present invention. - First, as shown in
FIGS. 2 and 3 ,chips 10 are separated by dicing awafer 100. - Then, as shown in
FIG. 4 , aremovable resin layer 20 is formed in a space between theseparated chips 10 and at upper parts thereof and then cured. - Here, the
removable resin layer 20 may be made of KMPR® brand photoresist and the like, and the KMPR® brand photoresist is formed by a method such as spin coating and the like. As described above, the KMPR® brand photoresist has an advantage of being removed without damage to an adhered surface. - Next, as shown in
FIG. 5 , thechips 10 are separated by dicing theremovable resin layer 20. - After that, as shown in
FIG. 6 , acarrier plate 30 is prepared. Thecarrier plate 30 may be made of porous ceramic and the like. - Then, as shown in
FIG. 7 , anadhesion layer 31 is formed on thecarrier plate 30. - Next, as shown in
FIG. 8 , thechips 10, which are separated in a state of being surrounded by theremovable resin layer 20, are mounted on thecarrier plate 30 on which theadhesion layer 31 is formed. - Here, when mounting the
chips 10, it is preferable to select and mount only the chips determined as good through a chip failure test, among thechips 30 separated in a state of being surrounded by theremovable resin layer 20. - Also, in the embodiment of the present invention, in order to mount only the good chips on the
carrier plate 30, instead of selecting and mounting only the good chips when mounting thechips 10 on thecarrier plate 30 as described above, thechips 10 are separated by dicing thewafer 100 as shown inFIG. 1 , and then theremovable resin layer 20 may be formed in the space between the rearrangedgood chips 10 and at the upper parts thereof after selecting only the chips determined as good through the chip failure test among the separatedchips 10 and rearranging the selected chips to be separated from one another. In this case, as shown inFIG. 5 , since all of thechips 10, which are diced in a state of being surrounded by theremovable resin layer 20, may be the good chips, all of thechips 10 surrounded by theremovable resin layer 20 can be mounted on thecarrier plate 30. Therefore, there is an advantage of reducing material cost of theremovable resin layer 20. - After that, as shown in
FIG. 9 , amolding material 32 is formed on theadhesion layer 31 to cover theremovable resin layer 20. Themolding material 32 may be made of EMC and the like. - Next, as shown in
FIG. 10 , thecarrier plate 30 is separated from thechips 10 by dipping the porousceramic carrier plate 30 in an organic solvent such as acetone and the like so that the organic solvent is absorbed through the porousceramic carrier plate 30 to melt theadhesion layer 31 on thecarrier plate 30. - Then, as shown in
FIG. 11 , adielectric layer 33 is formed on themolding material 32 and theremovable resin layer 20 including thechips 10 exposed by separating thecarrier plate 30. - Next, as shown in
FIG. 12 , viaholes 34 are formed to expose portions of thechips 10 by removing portions of thedielectric layer 33. - Next, as shown in
FIG. 13 , aseed layer 35 is formed on thedielectric layer 33 including insides of the via holes 34 by Cu electroless plating and the like. - After that, as shown in
FIG. 14 , aphotoresist pattern 36 is formed on theseed layer 35 to expose portions corresponding to the via holes 34. Thephotoresist pattern 36 plays a role of a plating mask when platingredistribution lines 37 described later. - Then, as shown in
FIG. 15 , theredistribution lines 37 are formed by plating metal on theseed layer 35 exposed by thephotoresist pattern 36. The redistribution lines 37 may be formed by Cu electro plating and the like. - Next, as shown in
FIG. 16 , thephotoresist pattern 36 is removed. - Next, as shown in
FIG. 17 , portions of theseed layer 35, which are exposed by removing thephotoresist pattern 36, are removed by etching. - Then, as shown in
FIG. 18 , portions of theredistribution lines 37 are exposed by removing portions of a solder resistlayer 38 after forming the solder resistlayer 38 on thedielectric layer 33. - After that, as shown in
FIG. 19 ,solder balls 40 are formed onUBMs 39 after forming theUBMs 39 on theredistribution lines 37 exposed by the solder resistlayer 38. - Then, as shown in
FIG. 20 , thechips 10 are separated into individual packages by cutting along dicing lines therebetween. - As described above, the method of manufacturing the wafer level package in accordance with the embodiment of the present invention has effects of improving production yield of the wafer level package and reducing manufacturing cost thereof by selecting only the
good chips 10 to manufacture the wafer level package. - The method of manufacturing the wafer level package in accordance with the embodiment of the present invention can be applied to fan-out type wafer level packaging as well as chip size wafer level packaging.
- Hereinafter, a method of reusing a chip in accordance with still another embodiment of the present invention will be described in detail with reference to
FIGS. 21 and 22 . -
FIGS. 21 and 22 are cross-sectional views illustrating the method of reusing the chip in accordance with the embodiment of the present invention. - First, as shown in
FIGS. 2 to 20 , individual packages are manufactured by a method of manufacturing a wafer level package in accordance with another embodiment of the present invention. - All of the individual packages of the wafer level package in accordance with the embodiment of the present invention include
good chips 10. - However, even in case of the package manufactured by the
good chip 10, a package failure can be generated since the failure is generated in a build-up process of formingredistribution lines 37 and the like on thechip 10. - In this case, since the
chip 10 itself is a good chip, in case of separating and reusing only thechip 10, there is an advantage of saving process cost and the like for manufacturing thegood chip 10. - For this, in the embodiment of the present invention, as shown in
FIG. 21 , amolding material 32 is separated from thechip 10 by removing aremovable resin layer 20 surrounding thechip 10 after manufacturing the individual package. - At this time, as described above, since the
removable resin layer 20 surrounding thechip 10 is made of resin such as KMPR® brand photoresist and the like, which is removable without damage to an adhered surface, themolding material 32 can be removed without damage to a surface of thechip 10 through removal of theresin layer 20. - The
removable resin layer 20 can be removed by NMP and the like. - Then, as shown in
FIG. 22 , a solder resistlayer 38 and adielectric layer 33 including the redistribution lines 37 on thechip 10 are all removed. Thedielectric layer 33 and the solder resistlayer 38 can be removed by plasma etching and the like, and theredistribution lines 37 can be removed by a Cu etchant and the like. - As described above, the wafer level package and the method of manufacturing the same and the method of reusing the chip in accordance with the present invention have effects of improving production yield of the wafer level package and reducing manufacturing cost thereof by selecting only the good chip to manufacture the wafer level package.
- Also, the present invention has an advantage of reusing the good chip if necessary by separating the molding material from the good chip through removal of the removable resin layer surrounding the good chip.
- Although a few embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the appended claims and their equivalents.
Claims (16)
1. A method of manufacturing a wafer level package comprising:
separating chips by dicing a wafer;
forming a removable resin layer in a space between the separated chips and at upper parts thereof;
separating the chips by dicing the removable resin layer;
mounting the chips separated in a state of being surrounded by the removable resin layer, on a carrier plate;
forming a molding material on the carrier plate to cover the removable resin layer;
separating the carrier plate from the chips;
forming a dielectric layer having redistribution lines connected to the chips, on the chips exposed by separating the carrier plate; and
forming a solder resist layer on the dielectric layer to expose portions of the redistribution lines.
2. The method according to claim 1 , between the separating the chips by dicing the wafer and the forming the removable resin layer in the space between the separated chips and at the upper parts thereof, further comprising rearranging the chips to be separated from one another by selecting only the chips determined as good through the chip failure test among the separated chips.
3. The method according to claim 1 , wherein in the mounting the chips separated in a state of being surrounded by the removable resin layer, only the chips determined as good through the chip failure test, among the chips separated in a state of being surrounded by the removable resin layer, are selected to be mounted on the carrier plate on which an adhesion layer is formed.
4. The method according to claim 1 , wherein the removable resin layer is made of KMPR.
5. The method according to claim 1 , wherein the forming the dielectric layer having the redistribution lines connected to the chips, on the chips exposed by separating the carrier plate includes:
forming the dielectric layer on the chips exposed by separating the carrier plate;
forming via holes to expose portions of the chips by removing portions of the dielectric layer;
forming a seed layer on the dielectric layer including insides of the via holes;
forming a photoresist pattern on the seed layer to expose portions corresponding to the via holes;
forming the redistribution lines by plating metal on the seed layer exposed by the photoresist pattern;
removing the photoresist pattern; and
removing portions of the seed layer exposed by removing the photoresist pattern.
6. The method according to claim 1 , after the forming the solder resist layer on the dielectric layer to expose the portions of the redistribution lines, further comprising:
forming UBMs on the redistribution lines exposed by the solder resist layer; and
forming solder balls on the UBMs.
7. The method according to claim 6 , after the forming the solder balls, further comprising separating the chips into individual packages by cutting along dicing lines between the chips.
8. A method of reusing a chip comprising:
manufacturing an individual package according to claim 1 ;
separating a molding material from a chip by removing a removable resin layer surrounding the chip; and
removing a solder resist layer and a dielectric layer including redistribution lines on the chip.
9. The method according to claim 8 , wherein the removable resin layer is made of KMPR.
10. The method according to claim 8 , wherein in the separating the molding material from the chip by removing the removable resin layer surrounding the chip, the resin layer is removed by using N-Methyl Pyrrolidone (NMP).
11. A method of reusing a chip comprising:
manufacturing an individual package according to claim 2 ;
separating a molding material from a chip by removing a removable resin layer surrounding the chip; and
removing a solder resist layer and a dielectric layer including redistribution lines on the chip.
12. A method of reusing a chip comprising:
manufacturing an individual package according to claim 3 ;
separating a molding material from a chip by removing a removable resin layer surrounding the chip; and
removing a solder resist layer and a dielectric layer including redistribution lines on the chip.
13. A method of reusing a chip comprising:
manufacturing an individual package according to claim 4 ;
separating a molding material from a chip by removing a removable resin layer surrounding the chip; and
removing a solder resist layer and a dielectric layer including redistribution lines on the chip.
14. A method of reusing a chip comprising:
manufacturing an individual package according to claim 5 ;
separating a molding material from a chip by removing a removable resin layer surrounding the chip; and
removing a solder resist layer and a dielectric layer including redistribution lines on the chip.
15. A method of reusing a chip comprising:
manufacturing an individual package according to claim 6 ;
separating a molding material from a chip by removing a removable resin layer surrounding the chip; and
removing a solder resist layer and a dielectric layer including redistribution lines on the chip.
16. A method of reusing a chip comprising:
manufacturing an individual package according to claim 7 ;
separating a molding material from a chip by removing a removable resin layer surrounding the chip; and
removing a solder resist layer and a dielectric layer including redistribution lines on the chip.
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KR1020080121660A KR101003678B1 (en) | 2008-12-03 | 2008-12-03 | wafer level package and method of manufacturing the same and method for reusing chip |
US12/318,752 US8110914B2 (en) | 2008-12-03 | 2009-01-07 | Wafer level package with removable chip protecting layer |
US13/363,513 US20120129297A1 (en) | 2008-12-03 | 2012-02-01 | Method of manufacturing wafer level package |
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-
2009
- 2009-01-07 US US12/318,752 patent/US8110914B2/en not_active Expired - Fee Related
-
2012
- 2012-02-01 US US13/363,513 patent/US20120129297A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US20080043067A1 (en) * | 2006-08-15 | 2008-02-21 | Fuji Xerox Co., Ltd. | Method of manufacturing substrate and substrate, method of manufacturing liquid drop ejecting head and liquid drop ejecting head, and liquid drop ejecting device |
US20080248614A1 (en) * | 2006-12-13 | 2008-10-09 | Advanced Chip Engineering Technology Inc. | Wafer level package with good cte performance |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8912087B2 (en) * | 2012-08-01 | 2014-12-16 | Infineon Technologies Ag | Method of fabricating a chip package |
TWI559468B (en) * | 2015-05-29 | 2016-11-21 | 矽品精密工業股份有限公司 | Electronic package structure and its carrier member |
WO2017024794A1 (en) * | 2015-08-12 | 2017-02-16 | 中芯长电半导体(江阴)有限公司 | Wafer level chip encapsulation method |
WO2020081691A1 (en) * | 2018-10-16 | 2020-04-23 | Averatek Corporation | Method of manufacture for embedded ic chip directly connected to pcb |
Also Published As
Publication number | Publication date |
---|---|
US8110914B2 (en) | 2012-02-07 |
KR101003678B1 (en) | 2010-12-23 |
KR20100063232A (en) | 2010-06-11 |
US20100133680A1 (en) | 2010-06-03 |
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