KR101030381B1 - Wafer level package and method of manufacturing the same - Google Patents

Wafer level package and method of manufacturing the same Download PDF

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KR101030381B1
KR101030381B1 KR20080112538A KR20080112538A KR101030381B1 KR 101030381 B1 KR101030381 B1 KR 101030381B1 KR 20080112538 A KR20080112538 A KR 20080112538A KR 20080112538 A KR20080112538 A KR 20080112538A KR 101030381 B1 KR101030381 B1 KR 101030381B1
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substrate
chip
molding material
molding
level package
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KR20100053765A (en
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박승욱
권영도
김진구
홍주표
이희곤
강준석
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삼성전기주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

본 발명은 웨이퍼 레벨 패키지 및 그 제조방법에 관한 것으로서, 재분배선을 포함하는 절연층; 상기 절연층 상에 상기 재분배선과 접속되도록 형성된 칩; 상기 칩을 몰딩시키도록 상기 절연층 상에 형성된 제1몰딩재; 및 상기 제1몰딩재 상에 형성된 제2몰딩재;를 포함하는 웨이퍼 레벨 패키지를 제공하고, 또한 본 발명은 상기 웨이퍼 레벨 패키지의 제조방법을 제공한다.The present invention relates to a wafer level package and a method of manufacturing the same, comprising: an insulating layer including redistribution wiring; A chip formed on the insulating layer so as to be connected to the redistribution line; A first molding material formed on the insulating layer to mold the chip; And a second molding material formed on the first molding material, and the present invention also provides a method of manufacturing the wafer level package.

웨이퍼 레벨 패키지, CTE, 몰딩재 Wafer Level Package, CTE, Molding Materials

Description

웨이퍼 레벨 패키지 및 그 제조방법{Wafer level package and method of manufacturing the same}Wafer level package and method of manufacturing the same

본 발명은 웨이퍼 레벨 패키지 및 그 제조방법에 관한 것으로서, 보다 상세하게는, 복수의 칩을 미리 몰딩시킨 다음, 이를 기판 상에 실장하고 나서 다시 최종 몰딩공정을 진행하는 웨이퍼 레벨 패키지 및 그 제조방법에 관한 것이다.The present invention relates to a wafer level package and a method for manufacturing the same. More particularly, the present invention relates to a wafer level package and a method for manufacturing the same, in which a plurality of chips are molded in advance, and then mounted on a substrate. It is about.

기존의 패키지는 수 개의 칩(chip)들을 포함하는 웨이퍼를 다이싱 라인(dicing line)을 따라 절단하여 개개의 칩으로 분리하고 나서, 개개의 칩 별로 패키징 공정을 실시하는 것을 통해 제조되었다.Existing packages are manufactured by cutting a wafer including several chips along a dicing line, separating the wafer into individual chips, and then performing a packaging process for each chip.

그러나, 상기 패키징 공정은 자체적으로 많은 단위 공정들, 예를 들어, 칩 부착, 와이어 본딩, 몰딩, 트림/포밍 등의 공정들을 포함하고 있는 바, 칩 별로 각각의 패키징 공정이 수행되어야 하는 기존의 패키지 제조방법은, 하나의 웨이퍼에서 얻어지는 칩의 수를 고려할 때, 모든 칩에 대한 패키징에 소요되는 시간이 너무 길다는 문제점을 안고 있다.However, the packaging process itself includes many unit processes, for example, chip attaching, wire bonding, molding, trim / forming, etc., and thus, an existing package in which each packaging process must be performed for each chip. The manufacturing method has a problem in that the time required for packaging for all chips is too long in view of the number of chips obtained from one wafer.

따라서, 최근에는 웨이퍼 상태에서 패키징 공정을 우선적으로 실시하고, 그런다음, 웨이퍼의 다이싱 라인을 따라 절단하여 개개의 패키지를 제조하는 방법이 제시되었다. 이와 같은 방법으로 제조된 패키지를 웨이퍼 레벨 패키지(Wafer Level Package)라 칭한다.Therefore, in recent years, a method of manufacturing an individual package by first performing a packaging process in a wafer state and then cutting along a dicing line of a wafer has been proposed. A package manufactured in this manner is called a wafer level package.

그러나, 종래의 웨이퍼 레벨 패키지는, 웨이퍼나 기판 상에 칩을 실장한 후 몰딩재를 형성하는 몰딩공정을 진행하는 동안, 기판, 칩, 몰딩재 등 다양한 재료가 사용되므로 각 재료 간의 CTE(Coefficient of Thermal Expansion) 차이로 인한 수축, 팽창에 의하여 칩 로케이션이 쉬프트(shift)되어 버리고, 이는 제조수율과 성능에 문제점을 야기시킨다.However, in the conventional wafer level package, various materials such as a substrate, a chip, and a molding material are used during the molding process of forming a molding material after mounting a chip on a wafer or a substrate. Shrinkage and expansion due to thermal expansion differences cause the chip location to shift, which causes problems in manufacturing yield and performance.

그리고 이러한 문제점은 현재의 트렌드(trend)인 대구경 웨이퍼에서 더욱 심하게 나타나고 있다.And this problem is more severe in the current trend (large diameter wafer).

따라서, 본 발명은 상기 문제점을 해결하기 위하여 이루어진 것으로서, 본 발명의 목적은, 복수의 칩을 미리 몰딩시킨 다음, 상기 프리-몰딩(pre-molding)된 복수의 칩을 기판 상에 실장하고 나서 최종 몰딩공정을 진행함으로써, 기판 상에 실장되는 칩의 위치가 쉬프트되는 것을 방지하여 제조 공정 수율을 향상시키고, 제조 원가를 절감시킬 수 있는 웨이퍼 레벨 패키지 및 그 제조방법을 제공하는데 있다.Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to mold a plurality of chips in advance, and then mount the plurality of pre-molded chips on a substrate, and then finally The present invention provides a wafer level package and a method of manufacturing the same, which prevents the position of the chip mounted on the substrate from being shifted, thereby improving the manufacturing process yield and reducing the manufacturing cost.

상기 목적을 달성하기 위한 본 발명의 실시예에 의한 웨이퍼 레벨 패키지는, 재분배선을 포함하는 절연층; 상기 절연층 상에 상기 재분배선과 접속되도록 형성된 칩; 상기 칩을 몰딩시키도록 상기 절연층 상에 형성된 제1몰딩재; 및 상기 제1몰딩재 상에 형성된 제2몰딩재;를 포함할 수 있다.Wafer-level package according to an embodiment of the present invention for achieving the above object, the insulating layer including a redistribution wire; A chip formed on the insulating layer so as to be connected to the redistribution line; A first molding material formed on the insulating layer to mold the chip; And a second molding material formed on the first molding material.

여기서, 상기 재분배선과 접속되는 외부연결수단을 더 포함할 수 있다.Here, the connection may further include an external connection means connected to the redistribution line.

또한, 상기 외부연결수단은 솔더볼일 수 있다.In addition, the external connection means may be a solder ball.

그리고, 상기 목적을 달성하기 위한 본 발명의 실시예에 의한 웨이퍼 레벨 패키지의 제조방법은, 복수의 칩이 실장된 제1기판 상에 상기 칩을 제1몰딩재로 몰딩시키는 단계; 상기 제1기판을 제거하는 단계; 상기 칩을 포함한 상기 제1몰딩재를 제2기판 상에 복수개 실장하는 단계; 상기 제2기판 상에 상기 칩을 포함한 상기 제1몰딩재를 몰딩시키는 제2몰딩재를 형성하는 단계; 상기 제2기판을 제거하는 단계; 및 상기 칩의 하부에 상기 칩과 접속되는 재분배선을 포함하는 절연층을 형성하는 단계;를 포함할 수 있다.In addition, a method of manufacturing a wafer level package according to an embodiment of the present invention for achieving the above object comprises the steps of: molding the chip with a first molding material on a first substrate on which a plurality of chips are mounted; Removing the first substrate; Mounting a plurality of first molding materials including the chip on a second substrate; Forming a second molding material for molding the first molding material including the chip on the second substrate; Removing the second substrate; And forming an insulating layer under the chip, the insulating layer including a redistribution line connected to the chip.

여기서, 상기 제1기판은 상기 제2기판보다 작은 크기를 가질 수 있다.The first substrate may have a smaller size than the second substrate.

또한, 상기 칩과 접속되는 재분배선을 포함하는 절연층을 형성하는 단계 이후에, 상기 재분배선과 접속되는 외부연결수단을 형성하는 단계;를 더 포함할 수 있다.The method may further include forming an external connection unit connected to the redistribution line after forming the insulating layer including the redistribution line connected to the chip.

또한, 상기 외부연결수단을 형성하는 단계 이후에, 상기 칩 사이의 다이싱 라인을 따라 절단하여 칩단위로 분리하는 단계;를 더 포함할 수 있다.In addition, after the forming of the external connection means, the step of cutting along the dicing line between the chips to separate the chip unit; may further include.

이상에서 설명한 바와 같이, 본 발명에 따른 웨이퍼 레벨 패키지 및 그 제조방법에 의하면, 복수의 칩을 프리-몰딩(pre-molding)시킨 제1몰딩재를 기판 상에 복수개 실장하고 나서, 상기 기판 상에 실장된 상기 칩을 포함한 제1몰딩재를 재몰딩시킴으로써, 상기 기판 상에서의 몰딩공정시 각 재료간의 CTE 차이로 인한 수축, 팽창 정도를 감소시켜, 칩의 위치가 쉬프트(shift)되는 것을 방지할 수 있다.As described above, according to the wafer level package according to the present invention and a method of manufacturing the same, after mounting a plurality of first molding materials on which a plurality of chips are pre-molded on a substrate, By remolding the first molding material including the mounted chip, the degree of shrinkage and expansion due to the difference in CTE between materials during the molding process on the substrate can be reduced, thereby preventing the chip position from shifting. have.

따라서, 본 발명은 웨이퍼 레벨 패키지의 제조 공정 수율 향상 및 제조 원가 절감에 기여할 수 있는 효과가 있다.Therefore, the present invention has an effect that can contribute to the improvement of the manufacturing process yield and manufacturing cost of the wafer level package.

본 발명에 따른 웨이퍼 레벨 패키지 및 그 제조방법의 상기 목적에 대한 기술적 구성을 비롯한 작용효과에 관한 사항은 본 발명의 바람직한 실시예가 도시된 도면을 참조한 아래의 상세한 설명에 의해서 명확하게 이해될 것이다.Matters relating to the operational effects including the technical configuration for the above object of the wafer-level package and the manufacturing method thereof according to the present invention will be clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

먼저, 도 1을 참조하여 본 발명의 실시예에 따른 웨이퍼 레벨 패키지에 대하여 상세하게 설명한다.First, a wafer level package according to an embodiment of the present invention will be described in detail with reference to FIG. 1.

도 1은 본 발명의 실시예에 따른 웨이퍼 레벨 패키지의 구조를 나타내는 단면도이다.1 is a cross-sectional view showing the structure of a wafer level package according to an embodiment of the present invention.

도 1에 도시된 바와 같이, 본 발명의 실시예에 의한 웨이퍼 레벨 패키지(100)는, 재분배선(redistribution layer; 70)을 포함하는 절연층(60)과, 상기 절연층(60) 상에 상기 재분배선(70)과 접속되도록 형성된 칩(20)과, 상기 칩(20)을 몰딩시키도록 상기 절연층(60) 상에 형성된 제1몰딩재(30) 및 상기 제1몰딩재(30) 상에 형성된 제2몰딩재(50)를 포함한다.As shown in FIG. 1, a wafer level package 100 according to an embodiment of the present invention includes an insulating layer 60 including a redistribution layer 70 and the insulating layer 60 on the insulating layer 60. The chip 20 formed to be connected to the redistribution line 70, and the first molding material 30 and the first molding material 30 formed on the insulating layer 60 to mold the chip 20. The second molding material 50 formed in the.

상기 제1몰딩재(30) 및 제2몰딩재(50)는 EMC(epoxy molding compound), 또는 레진(resin) 등으로 이루어질 수 있다.The first molding material 30 and the second molding material 50 may be made of an epoxy molding compound (EMC), a resin, or the like.

또한, 상기 제1몰딩재(30) 및 제2몰딩재(50)는, 컴프레션 몰딩(compression molding), 라미네이션(lamination), 또는 스크린 프린팅(screen printing) 등의 공정에 의해 형성된 것일 수 있다.In addition, the first molding material 30 and the second molding material 50 may be formed by a process such as compression molding, lamination, screen printing, or the like.

상기 절연층(60)은 폴리이미드(PI) 레진, 또는 포토레지스트(PR) 등과 같은 절연재로 이루어질 수 있다.The insulating layer 60 may be made of an insulating material such as polyimide (PI) resin or photoresist (PR).

그리고, 상기 절연층(60) 내에 상기 칩(20)과 접속되도록 형성된 재분배선(70)은 금속, 예컨대 Cu 등과 같은 전도성 물질로 이루어질 수 있다.In addition, the redistribution line 70 formed to be connected to the chip 20 in the insulating layer 60 may be made of a conductive material such as metal, for example, Cu.

상기 재분배선(70)을 포함하는 상기 절연층(60) 상에는, 상기 재분배선(70)과 전기적으로 접속되는 외부연결수단(80)이 형성되어 있다.On the insulating layer 60 including the redistribution line 70, an external connection means 80 is electrically connected to the redistribution line 70.

여기서, 상기 외부연결수단(80)은 솔더볼(solder ball) 등으로 이루어질 수 있다.Here, the external connection means 80 may be made of a solder ball (solder ball) or the like.

이하, 도 2a 내지 도 2i를 참조하여 앞서의 도 1에 도시된 웨이퍼 레벨 패키지의 제조방법에 대하여 상세히 설명한다.Hereinafter, a method of manufacturing the wafer level package shown in FIG. 1 will be described in detail with reference to FIGS. 2A to 2I.

도 2a 내지 도 2i는 본 발명의 실시예에 따른 웨이퍼 레벨 패키지의 제조방법을 설명하기 위해 순차적으로 나타낸 공정 단면도이다.2A to 2I are cross-sectional views sequentially illustrating a method of manufacturing a wafer level package according to an embodiment of the present invention.

도 2a에 도시된 바와 같이, 제1기판(10) 상에 복수의 칩(20)을 실장한다. 여기서, 상기 칩(20)을 실장하기 전에, 상기 제1기판(10) 상에 접착층(adhesion layer; 도시안됨)을 형성할 수 있다. 여기서, 상기 제1기판(10)은, 후술하는 제2기판(40)보다 작은 크기를 갖는 것이 바람직하다.As shown in FIG. 2A, a plurality of chips 20 are mounted on the first substrate 10. Here, an adhesive layer (not shown) may be formed on the first substrate 10 before the chip 20 is mounted. Here, the first substrate 10 preferably has a smaller size than the second substrate 40 to be described later.

다음으로, 도 2b에 도시된 바와 같이, 상기 칩(20)이 실장된 상기 제1기판(10) 상에, 상기 칩(20)을 제1몰딩재(30)로 몰딩시킨다. 상기 제1몰딩재(30)는 EMC(epoxy molding compound), 또는 레진(resin) 등으로 이루어질 수 있다.Next, as shown in FIG. 2B, the chip 20 is molded with the first molding material 30 on the first substrate 10 on which the chip 20 is mounted. The first molding material 30 may be made of an epoxy molding compound (EMC), a resin, or the like.

또한, 상기 제1몰딩재(30)는 컴프레션 몰딩(compression molding), 라미네이션(lamination), 또는 스크린 프린팅(screen printing) 등의 공정으로 형성하는 것 이 바람직하다.In addition, the first molding material 30 is preferably formed by a process such as compression molding, lamination, screen printing, or the like.

그런 다음, 도 2c에 도시된 바와 같이, 상기 제1기판(10)을 제거한다. 상기 제1기판(10)의 제거는, 상기 제1기판(10) 상에 형성된 접착층을 제거하는 방법 등에 의해 이루어질 수 있다.Then, as shown in Figure 2c, the first substrate 10 is removed. Removal of the first substrate 10 may be performed by a method of removing the adhesive layer formed on the first substrate 10.

그 다음에, 도 2d에 도시된 바와 같이, 상기 제1기판(10)이 제거된 상기 칩(20)을 포함한 상기 제1몰딩재(30)를 별도의 제2기판(40) 상에 복수개 실장한다.Next, as illustrated in FIG. 2D, a plurality of first molding materials 30 including the chip 20 from which the first substrate 10 has been removed are mounted on a separate second substrate 40. do.

여기서, 상기 칩(20)을 포함한 상기 제1몰딩재(30)를 실장하기 전에, 상기 제2기판(40) 상에도 접착층(adhesion layer; 도시안됨)을 형성할 수 있다.Here, before mounting the first molding material 30 including the chip 20, an adhesion layer (not shown) may also be formed on the second substrate 40.

다음으로, 도 2e에 도시된 바와 같이, 상기 제2기판(40) 상에 상기 칩(20)을 포함한 상기 제1몰딩재(30)를 몰딩시키는 제2몰딩재(50)를 형성한다.Next, as shown in FIG. 2E, a second molding material 50 is formed on the second substrate 40 to mold the first molding material 30 including the chip 20.

이와 같이 본 발명의 실시예에 따른 웨이퍼 레벨 패키지의 제조방법에서는, 칩(20)을 제2기판(40) 상에서 한번에 몰딩시키지 않고, 상술한 바와 같이 복수의 칩(20)을 상기 제2기판(40)보다 작은 크기의 제1기판(10) 상에서 제1몰딩재(30)로 프리-몰딩(pre-molding)시킨 다음, 상기 칩(20)을 포함한 제1몰딩재(30)를 상기 제2기판(40) 상에 복수개 실장하고 나서, 상기 제2기판(40) 상에 실장된 상기 칩(20)을 포함한 상기 제1몰딩재(30)를 제2몰딩재(50)로 재몰딩시킨다.As described above, in the method of manufacturing a wafer-level package according to the embodiment of the present invention, the plurality of chips 20 are formed on the second substrate as described above without molding the chips 20 on the second substrate 40 at one time. After pre-molding with the first molding material 30 on the first substrate 10 having a size smaller than 40, the first molding material 30 including the chip 20 is transferred to the second molding material. After mounting a plurality of substrates on the substrate 40, the first molding material 30 including the chip 20 mounted on the second substrate 40 is remolded with the second molding material 50.

즉, 본 발명의 실시예에서는 제2기판(40) 상에 실장될 전체 칩(20)들을 미리 복수의 군으로 나누어 각각의 군을 상기 제2기판(40)보다 작은 크기의 제1기판(10) 상에서 제1몰딩재(30)로 프리-몰딩시켜 고정시킨 후, 상기 제1몰딩재(30)에 고정된 칩(20)을 상기 제2기판(40) 상에 실장하고 제2몰딩재(50)로 몰딩시키는 것이다.That is, in the embodiment of the present invention, the entire chip 20 to be mounted on the second substrate 40 is divided into a plurality of groups in advance, and each group is smaller than the second substrate 40. After pre-molding and fixing the first molding material 30 on the first molding material 30, the chip 20 fixed to the first molding material 30 is mounted on the second substrate 40, and the second molding material ( 50).

따라서, 본 발명의 실시예에 따른 웨이퍼 레벨 패키지는, 전체 칩(20)들을 모두 기판 상에 실장한 후 한번에 몰딩시키는 종래의 웨이퍼 레벨 패키지에 비해,상기 제2기판(40) 상에서의 몰딩시 각 재료간의 CTE 차이로 인한 수축, 팽창 정도를 감소시켜, 칩(20)의 위치가 쉬프트(shift)되는 것을 방지할 수 있는 장점이 있다.Accordingly, in the wafer level package according to the embodiment of the present invention, the molding time on the second substrate 40 is compared with the conventional wafer level package in which all the chips 20 are all mounted on the substrate and then molded at a time. By reducing the degree of shrinkage and expansion due to the difference in the CTE between the materials, there is an advantage that the position of the chip 20 can be prevented from being shifted.

결국, 본 발명의 실시예에 따르면 웨이퍼 레벨 패키지를 제조하기 위한 기판의 크기가 점점 커지는 현재의 트렌드에 대응하여, 웨이퍼 레벨 패키지의 제조 공정 수율을 향상시킬 수 있으며, 제조 원가를 절감시킬 수 있는 효과가 있다.As a result, according to an embodiment of the present invention, in response to the current trend of increasing the size of a substrate for manufacturing a wafer level package, the manufacturing process yield of the wafer level package can be improved and the manufacturing cost can be reduced. There is.

그런 후에, 도 2f에 도시된 바와 같이, 상기 제2기판(40)을 제거한다. 여기서, 상기 제2기판(40)의 제거는, 상술한 바와 같이 상기 제2기판(40) 상에 형성된 접착층을 제거하는 방법 등에 의해 이루어질 수 있다.Thereafter, as shown in FIG. 2F, the second substrate 40 is removed. In this case, the second substrate 40 may be removed by a method of removing the adhesive layer formed on the second substrate 40 as described above.

그런 다음, 도 2g에 도시된 바와 같이, 상기 제2기판(40)이 제거된 상기 칩(20)의 하부에 절연층(60)을 형성한다. 상기 절연층(60)은 폴리이미드(PI) 레진, 또는 포토레지스트(PR) 등과 같은 절연재로 이루어질 수 있다.Next, as shown in FIG. 2G, the insulating layer 60 is formed under the chip 20 from which the second substrate 40 is removed. The insulating layer 60 may be made of an insulating material such as polyimide (PI) resin or photoresist (PR).

그 다음에, 도 2h에 도시된 바와 같이, 상기 절연층(60) 내에 상기 칩(20)과 접속되는 재분배선(70)을 형성하고 나서, 상기 재분배선(70)과 접속되는 외부연결수단(80)을 형성한다. 상기 외부연결수단(80)은 솔더볼 등으로 이루어질 수 있다.Next, as shown in FIG. 2H, a redistribution line 70 is formed in the insulating layer 60 to be connected to the chip 20, and then external connection means connected to the redistribution line 70 ( 80). The external connection means 80 may be made of a solder ball or the like.

그런 후에, 도 2i에 도시된 바와 같이, 상기 칩(20) 사이의 다이싱 라인(도시안됨)을 따라 절단하여 각각의 패키지(100)로 분리한다.Thereafter, as shown in FIG. 2I, the chips are cut along the dicing line (not shown) between the chips 20 and separated into respective packages 100.

이상에서 설명한 본 발명의 바람직한 실시예들은 예시의 목적을 위해 개시된 것이며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 있어 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러가지 치환, 변형 및 변경이 가능할 것이나, 이러한 치환, 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.Preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and various substitutions, modifications, and changes within the scope without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains. It will be possible, but such substitutions, changes and the like should be regarded as belonging to the following claims.

도 1은 본 발명의 실시예에 따른 웨이퍼 레벨 패키지의 구조를 나타내는 단면도.1 is a cross-sectional view showing the structure of a wafer level package according to an embodiment of the present invention.

도 2a 내지 도 2i는 본 발명의 실시예에 따른 웨이퍼 레벨 패키지의 제조방법을 설명하기 위해 순차적으로 나타낸 공정 단면도.2A to 2I are cross-sectional views sequentially showing a method of manufacturing a wafer level package according to an embodiment of the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

10: 제1기판 20: 칩10: first substrate 20: chip

30: 제1몰딩재 40: 제2기판30: first molding material 40: second substrate

50: 제2몰딩재 60: 절연층50: second molding material 60: insulating layer

70: 재분배선 80: 외부연결수단70: redistribution wiring 80: external connection means

100: 웨이퍼 레벨 패키지100: wafer level package

Claims (7)

삭제delete 삭제delete 삭제delete 복수개의 칩이 실장된 제1기판 상에 상기 복수개의 칩을 제1몰딩재로 몰딩시키는 단계;Molding the plurality of chips with a first molding material on a first substrate on which the plurality of chips are mounted; 상기 제1기판을 제거하는 단계;Removing the first substrate; 상기 복수개의 칩을 포함한 상기 제1몰딩재를, 제1몰딩재 면적의 2배 보다 큰 면적으로 이루어지는 제2기판 상에 복수개 실장하는 단계;Mounting a plurality of the first molding materials including the plurality of chips on a second substrate having an area larger than twice the area of the first molding materials; 상기 제2기판 상에 상기 복수개의 칩을 포함한 상기 제1몰딩재를 몰딩시키는 제2몰딩재를 형성하는 단계;Forming a second molding material for molding the first molding material including the plurality of chips on the second substrate; 상기 제2기판을 제거하는 단계;Removing the second substrate; 상기 칩의 하부에 상기 칩과 접속되는 재분배선을 포함하는 절연층을 형성하는 단계; 및Forming an insulating layer under the chip, the insulating layer including a redistribution line connected to the chip; And 상기 제1몰딩재 및 제2몰딩재와 결합된 상태의 복수개의 칩이 분리될 수 있도록 절단하는 단계;Cutting a plurality of chips in a state in which the first molding material and the second molding material are combined to be separated; 를 포함하는 웨이퍼 레벨 패키지의 제조방법.Method of manufacturing a wafer level package comprising a. 삭제delete 제4항에 있어서,The method of claim 4, wherein 상기 칩과 접속되는 재분배선을 포함하는 절연층을 형성하는 단계와 절단하는 단계 사이에,Between the step of forming and cutting the insulating layer including a redistribution wire connected to the chip, 상기 재분배선과 접속되는 외부연결수단을 형성하는 단계;를 더 포함하는 웨이퍼 레벨 패키지의 제조방법.And forming an external connection means connected to the redistribution line. 삭제delete
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