US8988093B2 - Bumped semiconductor wafer or die level electrical interconnect - Google Patents

Bumped semiconductor wafer or die level electrical interconnect Download PDF

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US8988093B2
US8988093B2 US13413032 US201213413032A US8988093B2 US 8988093 B2 US8988093 B2 US 8988093B2 US 13413032 US13413032 US 13413032 US 201213413032 A US201213413032 A US 201213413032A US 8988093 B2 US8988093 B2 US 8988093B2
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probe assembly
stud bumps
substrate
ic device
electrically coupled
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US20120182035A1 (en )
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James Rathburn
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HSIO Tech LLC
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HSIO Tech LLC
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2886Features relating to contacting the IC under test, e.g. probe heads; chucks
    • G01R31/2889Interfaces, e.g. between probe and tester

Abstract

A probe assembly that acts as a temporary interconnect between terminals on an IC device and a test station. The probe assembly includes a plurality of stud bumps arranged on a first surface of a substrate in a configuration corresponding to the terminal on the IC device. The stud bumps include a shape adapted to temporarily couple with the terminals on the IC device. A plurality of conductive traces on the substrate electrically couple the stud bumps with the test station.

Description

RELATED APPLICATIONS

The present application claims the benefit of U.S. Provisional Application No. 61/449,871, entitled Bumped Semiconductor Wafer or Die Level Electrical Interconnect, filed Mar. 7, 2011.

This application is continuation-in-part of U.S. patent application Ser. No. 13/266,522, titled COMPLIANT WAFER LEVEL PROBE ASSEMBLY, filed Oct. 27, 2011 now U.S. Pat. No. 8,803,539, which is a national stage application under 35 U.S.C. §371 of International Application No. PCT/US2010/036047, titled COMPLIANT WAFER LEVEL PROBE ASSEMBLY, filed May 25, 2010, which claims priority to U.S. Provisional Application No. 61/183,856, filed Jun. 3, 2009, both of which are hereby incorporated by reference in their entireties.

This application is a continuation-in-part of U.S. patent application Ser. No. 13/266,573, titled COMPLIANT PRINTED CIRCUIT AREA ARRAY SEMICONDUCTOR DEVICE PACKAGE, filed Oct. 27, 2011 now U.S. Pat. No. 8,803,539, which is a national stage application under 35 U.S.C. §371 of International Application No. PCT/US2010/036363, titled COMPLIANT PRINTED CIRCUIT AREA ARRAY SEMICONDUCTOR DEVICE PACKAGE, filed May 27, 2010, which claims priority to U.S. Provisional Application No. 61/183,411, filed Jun. 2, 2009, all of which are hereby incorporated by reference in their entireties.

This application is a continuation-in-part of U.S. patent application Ser. No. 13/318,203, entitled COMPLIANT PRINTED CIRCUIT SEMICONDUCTOR TESTER INTERFACE, filed Oct. 7, 2011 now U.S. Pat. No. 8,680,718, which is a national stage application under 35 U.S.C. §371 of International Application No. PCT/US2010/040188, titled COMPLIANT PRINTED CIRCUIT SEMICONDUCTOR TESTER INTERFACE, filed Jun. 28, 2010, which claims priority to U.S. Provisional Application No. 61/221,356, filed Jun. 29, 2009, all of which are hereby incorporated by reference in their entireties.

This application is a continuation-in-part of U.S. patent application Ser. No. 13/319,228, entitled SINGULATED SEMICONDUCTOR DEVICE SEPARABLE ELECTRICAL INTERCONNECT, filed Nov. 7, 2011, which is a national stage application under 35 U.S.C. §371 of International Application No. PCT/US2010/040197, titled SINGULATED SEMICONDUCTOR DEVICE SEPARABLE ELECTRICAL INTERCONNECT, filed Jun. 28, 2010, which claims priority to U.S. Provisional Application No. 61/221,380, filed Jun. 29, 2009, all of which are hereby incorporated by reference in their entireties.

The present application is a continuation-in-part of International Application No. PCT/US2011/062313, titled HIGH PERFORMANCE SURFACE MOUNT ELECTRICAL INTERCONNECT, filed Nov. 29, 2011, which claims the benefit of U.S. Provisional Application No. 61/418,625, filed Dec. 1, 2010, which are hereby incorporated by reference in their entireties.

TECHNICAL FIELD

The present disclosure relates to a probe assembly for testing electrical devices, and in particular, to a probe assembly that forms a temporary electrical interconnect between a wafer-level electrical device and a test station.

BACKGROUND OF THE INVENTION

During the semiconductor production process, manufacturers typically test integrated circuit (IC) devices while they are still grouped together as built on a silicon wafer. These tests verify various manufacturing parameters as well as chip function when possible. The connection points or terminals that will eventually be connected to the semiconductor package are typically very small and tightly spaced to conserve space on the wafer and allow for more ICs in the given area. Since the terminals are so small and tightly spaced, specialized tool sets are used to connect the IC to test electronics of a test station.

In basic terms, a precision piece of equipment called a probe station includes a customized precision connection device called a probe card mounted in a manner that allows contact tips of the probe card to be located directly over the terminal pads of the IC device on the silicon wafer. This probe card typically includes contact tips that correspond to the terminals to be contacted and the circuitry on the probe card routes the connection to a test station, which can be a general or special purpose computer.

When the device is powered, the test station looks for specific results and software determines if the IC passes or fails the test. Some applications allow for multiple devices to be contacted and tested at one time, increasing throughput of the testing process. Traditional probe cards consist of a variety of methods to transition the very small and tightly spaced terminal connections on the wafer to more widely spaced connections of the interface to a test station.

One probe style is called a cantilever needle, which is essentially a long precise wire that is shaped and positioned such that the contact tip is located where the terminal on the wafer will be during use to test an electrical device. Groups of needles are assembled into the probe card assembly and each needle is adjusted such that the field of tips all contact the desired terminal positions. Needle probes are typically the least expensive, are well established in the industry, and are widely available.

For mechanical reasons, the needles are relatively long (inches) to provide the required spring properties. Long contact members, however, tend to reduce the electrical performance of the connection by creating a parasitic effect that impacts the signal as it travels through the contact. Resistance in the contacts impacts the self heating effects as current passes through power delivery contacts. Also, the small space between contacts can cause distortion known as cross talk as a nearby contact may influence its neighbor. In most cases, the tests that are run using needle probes are typically basic on-off tests due to the limited signal integrity.

Another probe style is called a buckling beam or vertical probe. Basically, a series of very fine wires can be precisely located within an assembly that locates and guides each wire such that it can be located directly above the IC terminal to be connected. Buckling beam probes have been used for many years and can be based upon IBM technology that is over 20 years old. These probes are usually more expensive, and are typically used for area array connections. Again, the length of the contact wire to allow the beam to buckle is relatively large, so the signal performance can be impacted.

Another probe style is based upon a small precisely formed wire called a micro spring that is created on a sophisticated substrate in such a way that the tip of the wire is in position to contact the desired terminal on the wafer. There are also probe types that are made with semiconductor style processes, creating very small mechanisms commonly referred to as micro-electro-mechanical systems (“MEMS”) devices. Micro spring and MEMS-based probes are typically very expensive, and although better electrically than the longer probe styles, they may have electrical limitations.

Membrane probes are made using a photolithography process to create a very intricate flexible printed circuit member. The precisely shaped probe tips can be routed to the tester electronics through the circuit traces on the flexible printed circuit member. The probe tips are created with a proprietary process where the desired shape can be coined at the desired location into a sacrificial substrate. A series of plating, lithography, sputtering and etching steps are used to create the final circuit.

Membrane probes typically have the best signal performance, but can be expensive to build. For applications requiring higher frequency testing, membrane probes are currently the only choice available. The manufacturing process is very complicated, with many thin film, plating and lithography steps. The complexity of the process results in yield loss and the capital requirements are fairly large. The manufacturing process limits the physical height of the probe tips, such that they do not extend very far off the membrane. There is a potential for the membrane probe to collect debris and crush it into the wafer, thereby damaging ICS. Also, the contact tips must be extremely planar relative to the wafer since the probe tips typically have little or no compliance to compensate for non-planarity.

All of these probe types are rather expensive, costing thousands or even hundreds of thousands of dollars, depending on the type and number of contact points required. Wafer manufactures typically test each device at least once, so durability of the probe tips can be critical.

As processors and electrical systems evolve, increased terminal count, reductions in the terminal pitch (i.e., the distance between the terminals), and signal integrity have been drivers that impact probe tip requirements. As terminal count increases, a certain degree of compliance is required between the contacts on the IC and the probe tips to accommodate the topographic differences and maintain reliable electrical connections. Next generation systems will operate above 5 GHz and beyond and existing probe cards will not achieve acceptable price/performance levels without significant revision.

BRIEF SUMMARY OF THE INVENTION

The present disclosure relates to a high performance probe assembly for testing wafer-level integrated circuits. A present probe assembly, according to one embodiment, can form a temporary electrical interconnect between an electrical device and a test station.

The present probe assembly can provide a low cost alternative to other probe products, by utilizing an additive printing process and unique probe member fabrication process. The nature of the process can allow for very high frequency performance, as well as the addition of on-board electrical devices and circuitry planes that are not available with other probe products. The present probe assembly can be superior to membrane probe products in terms of mechanical performance, manufacturing complexity, electrical performance, and cost.

The production cost for a probe assembly in accordance with the present disclosure can be a fraction of the cost of producing exiting probe cards. The use of additive processes, such as for example, printed electrical features, reduces the capital cost and lead time for building the present probe assemblies. The additive processes can also increase yields over probe systems that rely on conventional lithography tools and masks.

Internal compliance of the entire assembly and of individual probe members can greatly increase performance of the present probe assemblies. The ability to build multi-layer structures over a relatively large area can permit terminal pitch on the IC devices to be reduced. The addition of circuitry planes and electrical devices in the present probe assembly can provide performance enhancements not available with current probe systems. The ability to add electrical devices, such as transistors and memory, to the present probe assembly can provide the opportunity to incorporate test intelligence, extending the use of legacy test equipment and improving test performance. The present probe assemblies can provide the opportunity to develop adaptive testing and to alter the circuit members during testing.

The present disclosure is directed to a probe assembly that acts as a temporary interconnect between terminals on an IC device and a test station. The probe assembly includes a plurality of stud bumps arranged on a first surface of a substrate in a configuration corresponding to the terminal on the IC device. The stud bumps include a shape adapted to temporarily couple with the terminals on the IC device. A plurality of conductive traces on the substrate electrically couple the stud bumps with the test station.

The substrate optionally includes a compliant layer located under the stud bumps. In one embodiment, the substrate is a multi-layered structure. A protective layer is optionally deposited on the conductive traces. In one embodiment, the conductive traces include a substantially rectangular cross-sectional shape.

The substrate is optionally a multi-layered structure. The substrate optionally includes at least one additional circuitry plane selected from a ground plane, a power plane, an electrical connection to other circuit members, a dielectric layer, and a flexible circuit. A flexible circuit member can electrically couple the conductive traces to the test station.

In one embodiment, at least one electrical device is printed on the substrate and electrically coupled to one or more of the conductive traces. The electrical devices are selected from the group consisting of a power plane, ground plane, capacitor, resistor, filters, signal or power altering and enhancing device, capacitive coupling feature, memory device, embedded integrated circuit, and RF antennae.

The present disclosure is also directed to an IC device test station including a housing with an opening adapted to retain the IC device. An IC device is located in the openings and electrically coupled to the stud bumps. The test station is electrically coupled to the conductive traces and evaluates the IC device.

The present disclosure is also directed to a method of forming a probe assembly to act as a temporary interconnect between terminals on an IC device and a test station. The method includes depositing a plurality of stud bumps on a first surface of a substrate in a configuration corresponding to the terminal on the IC device. The stud bumps include a shape adapted to temporarily couple with the terminals on the IC device. Conductive traces are formed on the substrate that electrically couple the stud bumps with the test station.

The use of additive printing processes can permit the material set in a given layer of a probe assembly to vary. Traditional PCB and circuit fabrication methods take sheets of material and stack them up, laminate, and/or drill. Additive printing technologies permit a wide variety of materials to be applied on a layer with a registration relative to the features of the previous layer. Selective addition of conductive, non-conductive, or semi-conductive materials at precise locations to create a desired effect has the major advantages in tuning impedance or adding electrical function on a given layer. Tuning performance on a layer by layer basis relative to the previous layer greatly enhances electrical performance.

The present disclosure is also directed to a method of adaptive testing of circuit members using the probe assembly of the present invention. Electrical devices on the probe assembly can monitor performance of the circuit member being tested and signal the test station to modify the test protocol accordingly. The test station can also be signaled to modify the circuit member.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a cross-sectional view of a method of making a high performance probe assembly in accordance with an embodiment of the present disclosure.

FIG. 2 illustrates the probe assembly of FIG. 1 after a coining operation in accordance with an embodiment of the present disclosure.

FIG. 3 illustrates an alternate probe assembly in accordance with an embodiment of the present disclosure.

FIG. 4 illustrates a method of forming circuitry on a probe assembly in accordance with an embodiment of the present disclosure.

FIG. 5 illustrates conductive traces applied to the probe assembly of FIG. 4.

FIG. 6 illustrates a compliant layer added to the probe assembly of FIG. 5.

FIG. 7 illustrates a protective layer added to the probe assembly of FIG. 6.

FIG. 8 is a cross-sectional view of a probe assembly in accordance with an embodiment of the present disclosure.

FIG. 9 is a cross-sectional view of an alternate probe assembly in accordance with an embodiment of the present disclosure.

FIG. 10 is a cross-sectional view of a probe assembly with circuitry layers in accordance with an embodiment of the present disclosure.

FIG. 11 is a cross-sectional view of a probe assembly with electrical devices in accordance with an embodiment of the present disclosure.

FIG. 12 is a cross-sectional view of a multi-layered probe assembly in accordance with an embodiment of the present disclosure.

FIG. 13 is a cross-sectional view of a probe assembly with coupling features in accordance with an embodiment of the present disclosure.

FIG. 14 is a cross-sectional view of the probe assembly of FIG. 13 with capacitive coupling features instead of probe members in accordance with an embodiment of the present disclosure.

FIG. 15 illustrates a method of reworking a probe assembly in accordance with an embodiment of the present disclosure.

FIG. 16 illustrates an alternate method of making a probe assembly in accordance with an embodiment of the present disclosure.

FIG. 17 illustrates the probe assembly of FIG. 16 with bumps applied in accordance with an embodiment of the present disclosure.

FIG. 18 illustrates an alternate method of making a probe assembly in accordance with an embodiment of the present disclosure.

FIG. 19 illustrates application of a second circuitry layer to the probe assembly of FIG. 18.

FIG. 20 illustrates a probe assembly with bulk metal deposited in recesses to form the vias in accordance with an embodiment of the present disclosure.

FIG. 21 illustrates a probe assembly with recesses filed with conductive particles as the vias in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE INVENTION

The present disclosure relates to a high performance probe assembly for testing wafer-level integrated circuits. The present probe assembly can be used with electrical devices having contact-to-contact spacing (pitch) on the order of less than about 1.0 millimeter (1×10−3 meters), and more preferably a pitch of less than about 0.7 millimeter, and most preferably a pitch of less than about 0.4 millimeter. Such fine pitch probe assemblies are especially useful for probing wafer-level integrated circuits.

FIG. 1 illustrates a probe assembly 50 that leverages the principle of stud bumping in accordance with an embodiment of the present disclosure. Stud bumping is a derivation of wire bonding, both of which have been used for many years in the semiconductor packaging industry. In recent years, the cost of gold has driven a migration to the use of copper bonding wire in an effort to reduce cost.

Substrate 56 is positioned appropriately within the bond area and stud bumps 54 are bonded to bonding pads 52 on the substrate 56. In operation, the wire on the stub bumping machine is broken off at a pre-determined point after the leading end of the wire is bonded to bonding pad 52. The bumps 54 are arranged in a pattern that corresponds to the target device to be connected, such as an integrated circuit (“IC”) device. The stub bumps 54 add metal above the surface of the substrate 56 to facilitate a probe tip or contact point. In some cases, a tamping tool is used to coin bump 54 into a more planar height and consistent shape relative to adjacent bumps.

The stub bumps 54 are connected to a circuit routing in the substrate 56. The substrate 56 optionally includes circuitry 58 electrically coupled to the bumps 54. The substrate 56 and/or the circuitry 58 are then connected to a test system.

The present method permits the use of copper, which enhances the durability of the present probe assembly 50 because copper is much harder than gold. As will be discussed herein, the various probe assemblies of the present disclosure can be further processed to increase the mechanical robustness as well as provide a low cost interconnect method compared to gold.

As illustrated in FIG. 2, the bumps 54 are coined or tamped to create a more uniform and planar peak height 55 with a shape more conductive to probing small targets.

FIG. 3 illustrates an alternate embodiment in which the bumps 54 are coined planar to create a target for another bump to be bonded to increase the overall extension beyond the substrate. A thick resist 60 can also be applied and the bond sites be extended by copper plating 62 to resemble copper pillars.

FIGS. 4 through 7 illustrate a method for building circuitry 100 in a substrate 102 of a probe assembly 104 that connects the bumps 106 to test equipment in accordance with an embodiment of the present disclosure. In the illustrated embodiment, the bumps 106 are located in protective structure 108. The protective structure 108 provide a platform for processing the interconnecting circuitry on backside 110 where the substrate 102. In this embodiment, the added circuitry and routing can be provided with a dielectric patterning method that provides an optional means to add function and interconnectivity.

As illustrated in FIG. 5, dielectrics 114 are printed or imaged to define the circuitry 100. Conductive traces 112 for the circuitry 100 are formed on the substrate 102 that connect to the bumps 106. The conductive traces 112 are manufactured to provide the corresponding routing and terminal fan-out to enable connection to the test electronics.

The conductive traces 112 may be deposited or printed on backside 110 of the substrate 102. In one embodiment, the conductive traces 112 are a metallic powder deposited in recesses created by the dielectric 114 and sintered. In another embodiment, the conductive traces 112 are a flowable, curable conductive material. The conductive traces 112 can also be created by foil transfer plated to the previous targets or applying a platable target catalyst which is post print plated. Various methods for maskless deposition of electronic materials, such as inkjet printing technology as will be described below, may also be used to deposit the conductive traces 112 on the substrate 102.

The plating is optionally applied using printing technology, such as for example inkjet printing technology, aerosol printing technology, or other maskless deposition process. The printing process is additive in nature. Digital images of the dielectric layers 114 and conductive traces 112 are printed directly on the surface 110, eliminating or reducing many of the lithography, plating, and etching steps used to manufacture conventional probes. The resulting probe assembly 104 (see FIG. 8) provides high frequency capability, and can reduce manufacturing production time and cost by orders of magnitude. The dielectric layer 114 can optionally be filled or doped with a near endless list of enhancement materials to lower dielectric constant, provide thermal management properties, create rigid, flexible, or compliant regions, and the like.

The dielectric layers of the present disclosure may be constructed of any of a number of dielectric materials that are currently used to make sockets, semiconductor packaging, and printed circuit boards. Examples may include UV stabilized tetrafunctional epoxy resin systems referred to as Flame Retardant 4 (FR-4); bismaleimide-triazine thermoset epoxy resins referred to as BT-Epoxy or BT Resin; and liquid crystal polymers (LCPs), which are polyester polymers that are extremely unreactive, inert and resistant to fire. Other suitable plastics include phenolics, polyesters, and Ryton® available from Phillips Petroleum Company.

In one embodiment, one or more of the dielectric materials are designed to provide electrostatic dissipation or to reduce cross-talk between the traces of the circuit geometry. An efficient way to prevent electrostatic discharge (“ESD”) is to construct one of the layers from materials that are not too conductive but that will slowly conduct static charges away. These materials preferably have resistivity values in the range of 105 to 1011 Ohm-meters.

The use of additive printing processes can permit a wide variety of materials to be applied on a layer with a registration relative to the features of the previous layer. Selective addition of conductive, non-conductive, or semi-conductive materials at precise locations to create a desired effect can offer advantages in tuning impedance or adding electrical function on a given layer. Tuning performance on a layer by layer basis relative to the previous layer can greatly enhance electrical performance.

The resulting conductive traces 112 preferably have substantially rectangular cross-sectional shapes. The use of additive printing processes permits conductive material, non-conductive material, and semi-conductive material to be simultaneously located on a single layer.

In one embodiment, recesses 116 (or trenches) formed on the substrate 102 that permit control of the location, cross section, material content, and aspect ratio of the conductive traces 112. Maintaining the conductive traces 112 with a cross-section of 1:1 or greater can provide greater signal integrity than traditional subtractive trace forming technologies. For example, traditional methods take a sheet of a given thickness and etch the material between the traces away to have a resultant trace that is usually wider than it is thick. The etching process also removes more material at the top surface of the trace than at the bottom, leaving a trace with a trapezoidal cross-sectional shape, degrading signal integrity in some applications. Using recesses to control the aspect ratio of the conductive traces 64 can result in a more rectangular or square cross-section of the conductive traces, with a corresponding improvement in signal integrity.

In another embodiment, pre-patterned or pre-etched thin conductive foil circuit traces can be transferred to the recesses 116. For example, a pressure sensitive adhesive can be used to retain the copper foil circuit traces in the recesses 116. The trapezoidal cross-sections of the pre-formed conductive foil traces are then post-plated. The plating material fills the open spaces in the recesses 116, resulting in a substantially rectangular or square cross-sectional shape corresponding to the shape of the recesses 116.

In another embodiment, a thin conductive foil is pressed into the recesses 116, and the edges of the recesses 116 act to cut or shear the conductive foil. The process positions a portion of the conductive foil in the recesses 116, but leaves the negative pattern of the conductive foil not wanted outside and above the recesses 116 for easy removal. Again, the foil in the recesses 116 is preferably post plated to add material to increase the thickness of the conductive traces 112 and to fill any voids left between the conductive foil and the recesses 116.

FIG. 6 illustrates a compliant layer 118 deposited on a surface 120 of the dielectric layers 114 and the conductive traces 112. The compliant layer 118 is preferably printed onto the surface 120. The compliant layer 118 can be printed using inkjet printing technology, aerosol printing technology, or other maskless deposition techniques as previously described. The compliant layer 118 provides normal force and actuation compliance. In another embodiment, the compliant layer 118 can be bonded to the surface 120. As used herein, “bond” or “bonding” refers to, for example, adhesive bonding, solvent bonding, ultrasonic welding, thermal bonding, or any other techniques suitable for attaching adjacent layers to a substrate.

FIG. 7 illustrates a protective layer 122 added to a top surface 124 of the compliant layer 118. The protective layer 122 can be applied using printing technology or can be a patterned film bonded to the top surface 124.

In one embodiment, the bumped substrate 102 can then be processed with post bump operations to harden or strengthen the bumps 106 since they are copper and remain relatively ductile although much harder than gold. Various metals such as nickel, nickel boron, palladium cobalt, rhodium, etc. can be plated onto the bumps to increase the wear resistance and reduce contamination during use.

FIG. 8 illustrates the probe assembly 104 of FIG. 7 removed from the fixture 108. Exposed portions 130 of the bumps 106 are optionally plated. In another embodiment, the bumps 106 are further processed, such as for example by coining or etching, to facilitate engagement with terminals 132 on a circuit member 134. Although the present probe assembly 104 can be particularly well suited for probing wafer-level integrated circuits, it can be used on a variety of other circuit members, such as for example, packaged integrated circuits, unpackaged integrated circuits, printed circuit boards, flexible circuits, bare-die devices, organic or inorganic substrates, or any other device capable of carrying electrical current.

In operation, a normal force 136 can be applied to a top surface 138 of the probe assembly 104 (on the protective layer 122) so the distal ends 140 of the bumps 106 electrically couple with the terminals 132 on the circuit member 134. The compliant layer 118 can compensate for non-planarity at the interface 142.

FIG. 9 is a cross-sectional view of an alternate probe assembly 150 with gaps 152, 154 in dielectric layers 156, 158 in accordance with an embodiment of the present disclosure. In the illustrated embodiment, the gaps 152, 154 are located substantially adjacent to probe members 160 to provide a degree of compliance. The gaps 152, 154 decouple compliance of probe members 160 from the dielectric layers 156, 158. A height 162 of the probe members 160 can be increased to reduce the chance of a bottom surface 164 of the dielectric layer 156 contacting a wafer 166.

FIG. 10 is a cross-sectional view of an alternate probe assembly 170 with additional functional layers 172A, 172B, 172C (collectively “172”), in accordance with an embodiment of the present disclosure. The functional layers can be, for example, specialty dielectrics, ground planes, power planes, shielding layers, stiffening layers, capacitive coupling features, circuitry layers, and the like. The layers 172 can be printed or preformed and selectively bonded or non-bonded to provide contiguous material or releasable layers.

In the illustrated embodiment, layers 172A and 1726 are ground planes. Layer 172C is a compliant layer that operates in either alone or in conjunction with gaps 174 adjacent to the probe members 176 to compensate for non-planarity at the interface 178 with the wafer 180.

FIG. 11 is a cross-sectional view of a probe assembly 200 with additional electrical devices 202 in accordance with embodiments of the present disclosure. The electrical devices 202 can be capacitors, transistors, resistors, filters, signal or power altering and enhancing devices, memory devices, an embedded IC, an RF antennae, and the like. The electrical devices 202 can be located on surface 204 or embedded in one of the layers. The probe assembly 200 can include an extension 208, such as for example a flexible circuit member, electrically coupling conductive traces 210 to test station 206.

The electrical devices 202 can be added as discrete components or printed onto one of the layers. The electrical devices 202 can be printed using inkjet printing technology, aerosol printing technology, or other maskless deposition techniques, as previously described. Electrical devices that are typically located on the test station 206 can be incorporated into the probe assembly 200, improving electrical performance.

In one embodiment, the electrical devices 202 monitor the testing of the circuit member 212 and communicate feedback to the test station 206. In one embodiment, a feedback signal from the electronic devices 202 can cause the test station 206 to alter the testing protocol depending on the performance of the circuit member 212, referred to as adaptive testing. In one embodiment, the feedback signal from the electronic devices 202 can cause the test station 206 to alter the circuit member 212, such as for example, by altering software resident on the circuit member 212. The electrical devices 202 can include passive or active functional elements. Passive structure refers to a structure having a desired electrical, magnetic, or other property, including but not limited to a conductor, resistor, capacitor, inductor, insulator, dielectric, suppressor, filter, varistor, ferromagnet, and the like. In the illustrated embodiment, electrical devices 202 include printed LED indicator and display electronics. Geometries can also be printed to provide capacitive coupling. Compliant material can be added between circuit geometry, such as discussed above, so the present electrical interconnect can be plugged into a receptacle or socket, supplementing or replacing the need for compliance within the connector.

The electrical devices 202 are preferably printed during construction of the interconnect assembly 200. The electrical devices 202 can be ground planes, power planes, electrical connections to other circuit members, dielectric layers, conductive traces, transistors, capacitors, resistors, RF antennae, shielding, filters, signal or power altering and enhancing devices, memory devices, embedded IC, and the like. For example, the electrical devices 202 can be formed using printing technology, adding intelligence to the high performance electrical interconnect 200. Features that are typically located on other circuit members can be incorporated into the interconnect 200 in accordance with an embodiment of the present disclosure.

The availability of printable silicon inks provides the ability to print electrical devices 202, such as disclosed in U.S. Pat. No. 7,485,345 (Renn et al.); U.S. Pat. No. 7,382,363 (Albert et al.); U.S. Pat. No. 7,148,128 (Jacobson); U.S. Pat. No. 6,967,640 (Albert et al.); U.S. Pat. No. 6,825,829 (Albert et al.); U.S. Pat. No. 6,750,473 (Amundson et al.); U.S. Pat. No. 6,652,075 (Jacobson); U.S. Pat. No. 6,639,578 (Comiskey et al.); U.S. Pat. No. 6,545,291 (Amundson et al.); U.S. Pat. No. 6,521,489 (Duthaler et al.); U.S. Pat. No. 6,459,418 (Comiskey et al.); U.S. Pat. No. 6,422,687 (Jacobson); U.S. Pat. No. 6,413,790 (Duthaler et al.); U.S. Pat. No. 6,312,971 (Amundson et al.); U.S. Pat. No. 6,252,564 (Albert et al.); U.S. Pat. No. 6,177,921 (Comiskey et al.); U.S. Pat. No. 6,120,588 (Jacobson); U.S. Pat. No. 6,118,426 (Albert et al.); and U.S. Pat. Publication No. 2008/0008822 (Kowalski et al.), which are hereby incorporated by reference. In particular, U.S. Pat. No. 6,506,438 (Duthaler et al.) and U.S. Pat. No. 6,750,473 (Amundson et al.), which are incorporated by reference, teach using ink-jet printing to make various electrical devices, such as, resistors, capacitors, diodes, inductors (or elements which may be used in radio applications or magnetic or electric field transmission of power or data), semiconductor logic elements, electro-optical elements, transistor (including, light emitting, light sensing or solar cell elements, field effect transistor, top gate structures), and the like.

The electrical devices 202 can also be created by aerosol printing, such as disclosed in U.S. Pat. No. 7,674,671 (Renn et al.); U.S. Pat. No. 7,658,163 (Renn et al.); U.S. Pat. No. 7,485,345 (Renn et al.); U.S. Pat. No. 7,045,015 (Renn et al.); and U.S. Pat. No. 6,823,124 (Renn et al.), which are hereby incorporated by reference.

Printing processes are preferably used to fabricate various functional structures, such as conductive paths and electrical devices, without the use of masks or resists. Features down to about 10 microns can be directly written in a wide variety of functional inks, including metals, ceramics, polymers and adhesives, on virtually any substrate—silicon, glass, polymers, metals and ceramics. The substrates can be planar and non-planar surfaces. The printing process is typically followed by a thermal treatment, such as in a furnace or with a laser, to achieve dense functionalized structures.

Ink jet printing of electronically active inks can be done on a large class of substrates, without the requirements of standard vacuum processing or etching. The inks may incorporate mechanical, electrical or other properties, such as, conducting, insulating, resistive, magnetic, semi conductive, light modulating, piezoelectric, spin, optoelectronic, thermoelectric or radio frequency.

A plurality of ink drops are dispensed from the print head directly to a substrate or on an intermediate transfer member. The transfer member can be a planar or non-planar structure, such as a drum. The surface of the transfer member can be coated with a non-sticking layer, such as silicone, silicone rubber, or Teflon.

The ink (also referred to as function inks) can include conductive materials, semi-conductive materials (e.g., p-type and n-type semiconducting materials), metallic material, insulating materials, and/or release materials. The ink pattern can be deposited in precise locations on a substrate to create fine lines having a width smaller than 10 microns, with precisely controlled spaces between the lines. For example, the ink drops form an ink pattern corresponding to portions of a transistor, such as a source electrode, a drain electrode, a dielectric layer, a semiconductor layer, or a gate electrode.

The substrate can be an insulating polymer, such as polyethylene terephthalate (PET), polyester, polyethersulphone (PES), polyimide film (e.g. Kapton, available from DuPont located in Wilmington, Del.; Upilex available from Ube Corporation located in Japan), or polycarbonate. Alternatively, the substrate can be made of an insulator such as undoped silicon, glass, or a plastic material. The substrate can also be patterned to serve as an electrode. The substrate can further be a metal foil insulated from the gate electrode by a non-conducting material. The substrate can also be a woven material or paper, planarized or otherwise modified on at least one surface by a polymeric or other coating to accept the other structures.

Electrodes can be printed with metals, such as aluminum or gold, or conductive polymers, such as polythiophene or polyaniline. The electrodes may also include a printed conductor, such as a polymer film comprising metal particles, such as silver or nickel, a printed conductor comprising a polymer film containing graphite or some other conductive carbon material, or a conductive oxide such as tin oxide or indium tin oxide.

Dielectric layers can be printed with a silicon dioxide layer, an insulating polymer, such as polyimide and its derivatives, poly-vinyl phenol, polymethylmethacrylate, polyvinyldenedifluoride, an inorganic oxide, such as metal oxide, an inorganic nitride such as silicon nitride, or an inorganic/organic composite material such as an organic-substituted silicon oxide, or a sol-gel organosilicon glass. Dielectric layers can also include a bicylcobutene derivative (BCB) available from Dow Chemical (Midland, Mich.), spin-on glass, or dispersions of dielectric colloid materials in a binder or solvent.

Semiconductor layers can be printed with polymeric semiconductors, such as, polythiophene, poly(3-alkyl)thiophenes, alkyl-substituted oligothiophene, polythienylenevinylene, poly(para-phenylenevinylene) and doped versions of these polymers. An example of suitable oligomeric semiconductor is alpha-hexathienylene. Horowitz, Organic Field-Effect Transistors, Adv. Mater., 10, No. 5, p. 365 (1998) describes the use of unsubstituted and alkyl-substituted oligothiophenes in transistors. A field effect transistor made with regioregular poly(3-hexylthiophene) as the semiconductor layer is described in Bao et al., Soluble and Processable Regioregular Poly(3-hexylthiophene) for Thin Film Field-Effect Transistor Applications with High Mobility, Appl. Phys. Lett. 69 (26), p. 4108 (December 1996). A field effect transistor made with a-hexathienylene is described in U.S. Pat. No. 5,659,181, which is incorporated herein by reference.

A protective layer can optionally be printed onto the electrical devices. The protective layer can be an aluminum film, a metal oxide coating, a polymeric film, or a combination thereof.

Organic semiconductors can be printed using suitable carbon-based compounds, such as, pentacene, phthalocyanine, benzodithiophene, buckminsterfullerene or other fullerene derivatives, tetracyanonaphthoquinone, and tetrakisimethylanimoethylene. The materials provided above for forming the substrate, the dielectric layer, the electrodes, or the semiconductor layer are exemplary only. Other suitable materials known to those skilled in the art having properties similar to those described above can be used in accordance with the present disclosure.

The ink-jet print head preferably includes a plurality of orifices for dispensing one or more fluids onto a desired media, such as for example, a conducting fluid solution, a semiconducting fluid solution, an insulating fluid solution, and a precursor material to facilitate subsequent deposition. The precursor material can be surface active agents, such as octadecyltrichlorosilane (OTS).

Alternatively, a separate print head is used for each fluid solution. The print head nozzles can be held at different potentials to aid in atomization and imparting a charge to the droplets, such as disclosed in U.S. Pat. No. 7,148,128 (Jacobson), which is hereby incorporated by reference. Alternate print heads are disclosed in U.S. Pat. No. 6,626,526 (Ueki et al.), and U.S. Pat. Publication Nos. 2006/0044357 (Andersen et al.) and 2009/0061089 (King et al.), which are hereby incorporated by reference.

The print head preferably uses a pulse-on-demand method, and can employ one of the following methods to dispense the ink drops: piezoelectric, magnetostrictive, electromechanical, electro pneumatic, electrostatic, rapid ink heating, magneto hydrodynamic, or any other technique well known to those skilled in the art. The deposited ink patterns typically undergo a curing step or another processing step before subsequent layers are applied.

While ink jet printing is preferred, the term “printing” is intended to include all forms of printing and coating, including: pre-metered coating such as patch die coating, slot or extrusion coating, slide or cascade coating, and curtain coating; roll coating such as knife over roll coating, forward and reverse roll coating; gravure coating; dip coating; spray coating; meniscus coating; spin coating; brush coating; air knife coating; screen printing processes; electrostatic printing processes; thermal printing processes; and other similar techniques.

FIG. 12 is a cross-sectional view of a probe assembly 220 with multiple layers 222 in accordance with an embodiment of the present disclosure. The probe assembly 220 can permit IC manufactures to reduce the pitch 224 of the terminals 226 on the IC devices 228 since the required signal routing to a test station 230 is performed by the probe assembly 220.

FIG. 13 is a cross-sectional view of a probe assembly 230 with coupling features 232 in accordance with an embodiment of the present disclosure. In one embodiment, the coupling features 232 can be capacitive couplings located between dielectric layers 234, 236. In another embodiment, the coupling features 232 can be optical fibers supported by the dielectric layers 234, 236. Optical quality materials can optionally be printed directly onto the dielectric layers 234, 236. The printing process can also allow for deposition of coatings in-situ that will enhance the optical transmission or reduce loss. The precision of the printing process can resolve misalignment issues when the optical fibers 232 are placed into a connector. In another embodiment, the coupling features 232 can be embedded coaxial or printed micro strip RF circuits with dielectric layers 234, 236. The dielectric layers 234, 236 can be formed of metal. Any of the structures noted above, as well as the probe members 240, can be created by printing dielectrics and metallization geometry.

FIG. 14 illustrates the probe assembly 250 of FIG. 13 with probe members 240 (shown in FIG. 13) removed. Optional different dielectric materials 252 can be located where the probe members 250 were located. The coupling features 252 can capacitively couple with terminals 254 on the wafer 256 due to the very precise planar nature of the printing process.

FIG. 15 illustrates a probe assembly 270 on which damaged probe members are removed and new probe members 272 are re-printed. Although the illustrated embodiment discloses triangular shaped probe members 272, a variety of other non-triangular shapes can be created using printing technology.

FIG. 16 is a side cross-sectional view of a method of making a probe assembly 300 using additive processes in accordance with an embodiment of the present disclosure. The process starts similar to a traditional PCB with a first circuitry layer 302 laminated to a stiffening layer or core 304, such as glass-reinforced epoxy laminate sheets (e.g., FR4). The first circuitry layer 302 can be preformed or can be formed using a fine line imaging step is conducted to etch the copper foil as done with many PCB processes. One or more dielectric layers 306, 308 are printed or placed to the surface 310 such that the first circuitry layer 302 is at least partially encased and isolated. In some embodiments, it may be desirable to use a preformed dielectric film to leave air dielectric gaps between traces. Recesses 312 in the dielectric layer 308 to expose circuitry 302 can be formed by printing, embossing, imprinting, chemical etching with a printed mask, or a variety of other techniques.

As illustrated in FIG. 17, the exposed circuitry 302 can be stud bumped or ball bonded 314 with a traditional bonding machine used in semiconductor packaging applications. In the embodiment below, copper foil layer 316 is applied surface 318 so that the bumps 314 engage with the foil 316 and deforms to create the interconnecting via during the lamination operation. The size and shape of the bumps 314 can be tailored to the ideal condition for deformation without piercing the foil 316. The foil 316 can be pre-etched with the next circuit pattern or can be laminated as a sheet and etched post lamination. In addition, the dielectric material 308 can be left in a tack cure or partial cure state such that a final bond is achieved at final cure. If desired, the bond bumps 314 can be coined planar prior to adding the subsequent foil layer 316.

FIGS. 18 and 19 illustrate an variation of the probe assembly 300 in which the foil layer 316 includes preformed holes or breaks 320 in accordance with an embodiment of the present disclosure. The bumps 314 extend into the openings 320 or reside near the openings 320 so plating solution 322 can enter the mating region to plate the via structure 324 together. The plating 322 is preferably a corrosion resistant metallic material such as nickel, gold, silver, palladium, or multiple layers thereof. One benefit of the present structure is the material set can be varied layer by layer or altered on a given layer to create some desired performance enhancement not possible with conventional construction.

FIG. 20 illustrates an alternate probe assembly 350 with solid bulk metal 352, such as copper or solder spheres, or plated copper, located in recesses 354 in dielectric layer 356 in accordance with an embodiment of the present disclosure. The bulk metal 352 electrically couples with the lower circuitry layer 358 and the upper circuitry layer 360 with slight deformation or material displacement. In one embodiment, the bulk metal 352 is plated, such as by flowing a plating solution through openings 362 in the upper circuitry 360. It may be possible to provide sufficient engagement to interconnect reliably without the need for plating since the bulk metal 352 is encased within dielectric 356 and environmentally sealed. In the event the bulk metal 352 is solder, the circuit layers 358, 360 can be interconnected when the solder 352 is reflowed with the dielectric 356 acting as a natural solder wicking barrier.

FIG. 21 illustrates an alternate probe assembly 370 with reservoirs 372 between circuitry layers 374, 376 that can be filled with loose conductive particles 378 in accordance with an embodiment of the present disclosure. The conductive particles 378 can optionally be sintered, coined, tightly compacted, plated, mixed with an adhesive binder, etc. to create via 380. The method of FIG. 21 can also be used to create the circuitry itself or supplement the etched foil structures. Use of reservoirs containing conductive particles is disclosed in commonly assigned PCT/US2010/36313 entitled Resilient Conductive Electrical Interconnect, filed May 27, 2010, which is hereby incorporated by reference.

The probe assembly 370 can also be mated with a variety of connection techniques, with the routing to the tester terminated in a Land Pad to simulate a LGA device or Board to Board format as well as terminated in BGA style terminals either of solder or plated copper to facilitate an easily removed and replaced probe assembly or structure where the probe assembly is easily removed from the probe card.

Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limit of that range and any other stated or intervening value in that stated range is encompassed within the embodiments of the present invention. The upper and lower limits of these smaller ranges which may independently be included in the smaller ranges is also encompassed within the embodiments of the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either both of those included limits are also included in the embodiments of the invention.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of the invention belong. Although any methods and materials similar or equivalent to those described herein can also be used in the practice or testing of the embodiments of the present invention, the preferred methods and materials are now describe. All patents and publications mentioned herein, including those cited in the Background of the application, are hereby incorporated by reference to disclose and described the methods and/or materials in connection with which the publications are cited.

The publications discussed herein are provided solely for their disclosure prior to the filing date of the present application. Nothing herein is to be construed as an admission that the embodiments of the present invention are not entitled to antedate such publication by virtue of prior invention. Further, the dates of publication provided may be different from the actual publication dates which may need to be independently confirmed.

Other embodiments of the invention are possible. Although the description above contains much specificity, these should not be construed as limiting the scope of the invention, but as merely providing illustrations of some of the presently preferred embodiments of this invention. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be made and still fall within the scope of the invention. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying modes of the disclosed embodiments of the present invention. Thus, it is intended that the scope of at least some of the present invention herein disclosed should not be limited by the particular disclosed embodiments described above.

Thus, the scope of this invention should be determined by the appended claims and their legal equivalents. Therefore, it will be appreciated that the scope of the present invention fully encompasses other embodiments which may become obvious to those skilled in the art, and that the scope of the present invention is accordingly to be limited by nothing other than the appended claims, in which reference to an element in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather “one or more.” All structural, chemical, and functional equivalents to the elements of the above-described preferred embodiment that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Moreover, it is not necessary for a device or method to address each and every problem sought to be solved by the present invention, for it to be encompassed by the present claims. Furthermore, no element, component, or method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the claims.

Claims (19)

What is claimed is:
1. A probe assembly to act as a temporary interconnect between terminals on an IC device and a test station, the probe assembly comprising:
a substrate comprising a dielectric material;
a plurality of conductive stud bumps arranged on a first surface of the substrate in a configuration corresponding to the terminal on the IC device, the stud bumps comprising a shape adapted to temporarily couple with the terminals on the IC device;
a plurality of conductive traces located on the substrate electrically coupled with the test station and proximal ends of one or more of the stud bumps; and
a compliant layer supporting the proximal ends of the stud bumps, the compliant layer adapted to elastically bias the stud bumps toward the terminals on the circuit member and to compensate for non-planarity of the terminal.
2. The probe assembly of claim 1 comprising a protective layer deposited on the compliant layer.
3. The probe assembly of claim 1 wherein the substrate comprises a multi-layered structure.
4. The probe assembly of claim 3 wherein the substrate comprises a conductive material and a non-conductive material located on a single layer of the probe assembly.
5. The probe assembly of claim 3 wherein the multi-layered structure comprises at least one additional circuitry plane comprising one of a ground plane, a power plane, an electrical connection to other circuit members, a dielectric layer, and a flexible circuit.
6. The probe assembly of claim 1 further comprising a flexible circuit member electrically coupled to the conductive traces and extending beyond a perimeter edge of the probe assembly.
7. The probe assembly of claim 1 further comprising a plurality of electrical devices located on the probe assembly and electrically coupled to one or more of the conductive traces.
8. The probe assembly of claim 7 wherein the electrical devices are selected from the group consisting of a power plane, ground plane, capacitor, resistor, filters, signal or power altering and enhancing device, capacitive coupling feature, memory device, embedded integrated circuit, and RF antennae.
9. The probe assembly of claim 1 further comprising a plurality of electrical devices printed on one or more of the layers and electrically coupled to at least one of the stud bumps.
10. A test system comprising:
a housing comprising an opening adapted to retain the IC device;
an IC device located in the openings in the housing and electrically coupled to the stud bumps on the probe assembly of claim 1; and
a test station electrically coupled to the conductive traces that is adapted to evaluate the IC device.
11. A testing system comprising:
a probe assembly comprising;
a substrate comprising a dielectric material;
a plurality of conductive stud bumps arranged on a first surface of the substrate in a configuration corresponding to the terminal on the IC device, the stud bumps comprising a shape adapted to temporarily couple with the terminals on the IC device;
a plurality of conductive traces located on the substrate electrically coupled with proximal ends of one or more of the stud bumps; and
a compliant layer supporting the proximal ends of the stud bumps, the compliant layer adapted to bias the stud bumps toward the terminals on the circuit member and to compensate for non-planarity of the terminal;
an IC device comprising terminals compressively engaged with distal ends of the stud bumps, the compliant layer biasing the stud bumps toward terminals on the IC device and to compensate for non-planarity of the terminals; and
a test station electrically coupled to the conductive traces of the probe assembly configured to test the IC device.
12. The test system of claim 11 comprising a protective layer deposited on the compliant layer.
13. The test system of claim 11 wherein the substrate comprises a multi-layered structure.
14. The test system of claim 13 wherein the substrate comprises a conductive material and a non-conductive material located on a single layer of the probe assembly.
15. The test system of claim 13 wherein the multi-layered structure comprises at least one additional circuitry plane comprising one of a ground plane, a power plane, an electrical connection to other circuit members, a dielectric layer, and a flexible circuit.
16. The test system of claim 11 further comprising a flexible circuit member electrically coupled to the conductive traces and extending beyond a perimeter edge of the probe assembly.
17. The test system of claim 11 further comprising a plurality of electrical devices located on the probe assembly and electrically coupled to one or more of the conductive traces.
18. The test system of claim 17 wherein the electrical devices are selected from the group consisting of a power plane, ground plane, capacitor, resistor, filters, signal or power altering and enhancing device, capacitive coupling feature, memory device, embedded integrated circuit, and RF antennae.
19. The test system of claim 11 further comprising a plurality of electrical devices printed on one or more of the layers and electrically coupled to at least one of the stud bumps.
US13413032 2009-06-02 2012-03-06 Bumped semiconductor wafer or die level electrical interconnect Active 2031-11-14 US8988093B2 (en)

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US18341109 true 2009-06-02 2009-06-02
US18385609 true 2009-06-03 2009-06-03
US22138009 true 2009-06-29 2009-06-29
PCT/US2010/036047 WO2010141264A1 (en) 2009-06-03 2010-05-25 Compliant wafer level probe assembly
PCT/US2010/036363 WO2010141311A1 (en) 2009-06-02 2010-05-27 Compliant printed circuit area array semiconductor device package
PCT/US2010/040197 WO2011002712A1 (en) 2009-06-29 2010-06-28 Singulated semiconductor device separable electrical interconnect
US41862510 true 2010-12-01 2010-12-01
US201161449871 true 2011-03-07 2011-03-07
US201113266573 true 2011-10-27 2011-10-27
US201113266522 true 2011-10-27 2011-10-27
US201113319228 true 2011-11-07 2011-11-07
PCT/US2011/062313 WO2012074963A1 (en) 2010-12-01 2011-11-29 High performance surface mount electrical interconnect
US201213318203 true 2012-02-14 2012-02-14
US13413032 US8988093B2 (en) 2009-06-02 2012-03-06 Bumped semiconductor wafer or die level electrical interconnect

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US13413032 US8988093B2 (en) 2009-06-02 2012-03-06 Bumped semiconductor wafer or die level electrical interconnect

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PCT/US2010/036047 Continuation-In-Part WO2010141264A1 (en) 2009-06-03 2010-05-25 Compliant wafer level probe assembly
US13266522 Continuation-In-Part US8803539B2 (en) 2009-06-03 2010-05-25 Compliant wafer level probe assembly
US13266573 Continuation-In-Part US9054097B2 (en) 2009-06-02 2010-05-27 Compliant printed circuit area array semiconductor device package
PCT/US2010/036363 Continuation-In-Part WO2010141311A1 (en) 2009-06-02 2010-05-27 Compliant printed circuit area array semiconductor device package
US13319228 Continuation-In-Part US8984748B2 (en) 2009-06-29 2010-06-28 Singulated semiconductor device separable electrical interconnect
PCT/US2010/040197 Continuation-In-Part WO2011002712A1 (en) 2009-06-29 2010-06-28 Singulated semiconductor device separable electrical interconnect
US13319203 Continuation-In-Part US8981809B2 (en) 2009-06-29 2010-06-28 Compliant printed circuit semiconductor tester interface
PCT/US2010/040188 Continuation-In-Part WO2011002709A1 (en) 2009-06-29 2010-06-28 Compliant printed circuit semiconductor tester interface
US201113266522 Continuation-In-Part 2011-10-27 2011-10-27
PCT/US2011/062313 Continuation-In-Part WO2012074963A1 (en) 2010-12-01 2011-11-29 High performance surface mount electrical interconnect
US13413032 Continuation-In-Part US8988093B2 (en) 2009-06-02 2012-03-06 Bumped semiconductor wafer or die level electrical interconnect

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