TWI497679B - 半導體封裝件及其製造方法 - Google Patents

半導體封裝件及其製造方法 Download PDF

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Publication number
TWI497679B
TWI497679B TW098140649A TW98140649A TWI497679B TW I497679 B TWI497679 B TW I497679B TW 098140649 A TW098140649 A TW 098140649A TW 98140649 A TW98140649 A TW 98140649A TW I497679 B TWI497679 B TW I497679B
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Taiwan
Prior art keywords
dielectric layer
metal
layer
manufacturing
semiconductor package
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TW098140649A
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English (en)
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TW201119002A (en
Inventor
Chao Fu Weng
John Richard Hunt
Li Chuan Tsai
Yi Ting Wu
Chieh Chen Fu
Ying Te Ou
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Advanced Semiconductor Eng
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Priority to TW098140649A priority Critical patent/TWI497679B/zh
Priority to US12/955,782 priority patent/US20110127654A1/en
Publication of TW201119002A publication Critical patent/TW201119002A/zh
Application granted granted Critical
Publication of TWI497679B publication Critical patent/TWI497679B/zh

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Description

半導體封裝件及其製造方法
本發明是有關於一種半導體封裝件及其製造方法，且特別是有關於一種晶片被金屬環繞的半導體封裝件及其製造方法。
請參照第1圖(習知技藝)，其繪示習知半導體封裝件的示意圖。半導體封裝件10包括一金屬防護層12、一封膠14、一晶片16、數條銲線18及一基板20。
晶片16設於基板20，銲線18電性連接晶片16與基板20，封膠14包覆晶片16及銲線18。金屬防護層12包覆封膠14，以防止電磁干擾(Electromagnetic Interference,EMI)。
金屬防護層12一般都是另外製作的金屬罩，以緊配方式組裝至封膠14。或者，金屬防護層12亦可使用塗佈的方式形成封膠14上。以塗佈方式形成的金屬防護層12，於封膠14轉角處的厚度係不均。
此外，由於金屬防護層12全部暴露於大氣環境中，故其材質須具備優良的抗氧化特性。一般來說，金屬防護層12由鎳或銀組成，其價格較昂貴。
本發明係有關於一種半導體封裝件及其製造方法，金屬層之大部份或甚至全部被包覆，使金屬層之大部份或甚至全部與環境隔離，降低金屬層受到大氣環境侵害的程度。
根據本發明之第一方面，提出一種半導體封裝件。半導體封裝件包括一金屬環繞部、一晶片、一封膠、一第一介電層及一圖案化導電層。金屬環繞部環繞出一凹部。晶片設於凹部，晶片包括數個接墊。封膠形成於凹部並包覆晶片之側面並露出接墊。第一介電層形成於晶片，第一介電層並具有數個第一開孔，第一開孔露出接墊。圖案化導電層形成於第一介電層並電性連接接墊。
根據本發明之第二方面，提出一種半導體封裝件的製造方法。製造方法包括以下步驟。提供一第一載板；設置數個金屬環繞部於第一載板每個金屬環繞部環繞出一凹部；對應地設置數個晶片於該些凹部，晶片連接於第一載板，每個晶片包括數個接墊，接墊面向第一載板。以一封膠包覆晶片及金屬環繞部，以使封膠、晶片及金屬環繞部形成一封膠體；設置封膠體於一第二載板，接墊背向第二載板；移除第一載板，以露出接墊；形成一第一介電層於晶片，第一介電層具有數個第一開孔，第一開孔露出接墊；形成一圖案化導電層於第一介電層，圖案化導電層電性連接接墊；移除第二載板；以及，切割封膠體，以形成數個半導體封裝件。
根據本發明之第三方面，提出一種半導體封裝件的製造方法。製造方法包括以下步驟。提供一載板；設置數個金屬環繞部於載板，每個金屬環繞部環繞出一凹槽；對應地設置數個晶片於該些凹槽，晶片具有相對應之一主動表面與一底面並包括數個接墊，接墊設於主動表面，底面面向對應之凹槽之一槽底面；以一封膠包覆晶片之側面並露出接墊；形成一第一介電層於晶片，第一介電層具有數個第一開孔，第一開孔露出接墊；形成一圖案化導電層於第一介電層，圖案化導電層電性連接接墊；移除載板；以及，切割封膠體，以形成數個半導體封裝件。
為讓本發明之上述內容能更明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：
以下係提出較佳實施例作為本發明之說明，然而實施例所提出的內容，僅為舉例說明之用，而繪製之圖式係為配合說明，並非作為限縮本發明保護範圍之用。再者，實施例之圖示亦省略不必要之元件，以利清楚顯示本發明之技術特點。
第一實施例
請參照第2圖，其繪示依照本發明第一實施例之半導體封裝件之示意圖。半導體封裝件100，例如是通訊型的半導體封裝件或其它種類的半導體封裝件，其包括一金屬環繞部102、一封膠104、一晶片106、一第一介電層110、一圖案化導電層112、一第二介電層114、數個錫球118及一金屬防護層116。
請同時參照第2圖及第3圖，第3圖繪示第2圖之金屬環繞部的上視圖。金屬環繞部可102為一封閉環狀體，該封閉環狀體環繞出一凹部124。晶片106設於凹部124內。金屬環繞部102具有相對應之一第一金屬表面120與一第二金屬表面122。由於金屬環繞部102被包覆住而與環境隔離，故金屬環繞部102的材質可以是廉價的金屬，例如是銅或鋁，或者可以是不具抗腐蝕性的金屬。
金屬防護層116連接於第二金屬表面122並遮蓋凹部124之開口140。金屬環繞部102與金屬防護層116圍繞晶片106，有效防止電磁干擾。
晶片106包括數個接墊126及一保護層136並具有一主動表面138，接墊126設於主動表面138上。
封膠104形成於凹部124內並包覆晶片106之側面128及底面130並露出晶片106之數個接墊126。其中，封膠104更包覆金屬環繞部102之外側壁142，亦即，本實施例的半導體封裝件100係露出封膠104。
此外，封膠104之外側壁144、第一介電層110之外側壁146及第二介電層114之外側壁148係切齊。
第一介電層110，例如是高分子聚合物，形成於晶片106及金屬環繞部102之第一金屬表面120。第一介電層110具有數個第一開孔132(繪示於第5I圖)，該些第一開孔132對應地露出該些接墊126。
圖案化導電層112例如是重新佈線層(Redistribution layer,RDL)，其形成於第一介電層110並電性連接接墊126。
第二介電層114，例如是高分子聚合物，形成於圖案化導電層112以保護圖案化導電層112並具有數個第二開孔134。該些第二開孔134露出圖案化導電層112。錫球118形成於第二開孔134，以電性連接圖案化導電層112。
此外，第二開孔134內可形成錫球接墊(未繪示)，例如是凸塊下層金屬(Under Bump Metallization,UBM)，以提升錫球118的結合性。
於本實施例中，可應用重佈晶片之封膠體級封裝(Chip-redistribution Encapsulant Level Package)技術來形成半導體封裝件100。即，晶圓上的晶片106被切割分離後，重新佈置於載板上，然後再形成例如是第一介電層110、圖案化導電層112及第二介電層114等結構。亦即，本實施例的半導體封裝件100可說是晶圓級封裝件(Wafer Level Package,WLP)。
以下係詳細介紹本發明第一實施例之半導體封裝件100的製造方法。請同時參照第4圖及第5A至5M圖，第4圖繪示依照本發明第一實施例之半導體封裝件的製造方法流程圖，第5A至5M圖繪示第3圖之半導體封裝件的製造示意圖。
於步驟S102中，如第5A圖所示，提供一包括黏貼層152之第一載板150。
然後，於步驟S104中，如第5B圖所示，設置數個金屬環熱部102於第一載板150的黏貼層152上。
金屬環繞部102的第一金屬表面120連接於第一載板150的黏貼層152。每個金屬環繞部102環繞出凹部124。該些金屬環繞部102彼此分離地設置於第一載板150的黏貼層152上。
可應用沖壓工法或雷射加工的方式於金屬環繞部102上製作出凹部124，亦即，凹部124係為貫孔。
然後，於步驟S106中，如第5C圖所示，對應地設置數個晶片106於該些凹部124。晶片106連接於第一載板150的黏貼層152上，晶片106之接墊126面向第一載板150。
此外，該些晶片106可從一晶圓上切割下來後，於本步驟S106中重新配置於第一載板150。
然後，於步驟S108中，如第5D圖所示，以封膠104包覆晶片106的側面128及底面130以及金屬環繞部102，使封膠104、晶片106及金屬環繞部102形成一封膠體154。其中，封膠104覆蓋第二金屬表面122及凹部124，且封膠104更形成於該些環狀體中相鄰二者之間的空間S。
然後，於步驟S110中，如第5E圖所示，去除第二金屬表面122及凹部124上方的封膠，以露出第二金屬表面122。去除封膠的方式例如是化學機械研磨(Chemical Mechanical Polishing,CMP)。
然後，於步驟S112中，如第5F圖所示，形成金屬防護層116於第二金屬表面122及封膠104。金屬防護層116覆蓋凹部124之開口140。
然後，於步驟S114中，如第5G圖所示，設置包含有金屬防護層116的封膠體154於一第二載板156之黏貼層160上，其中金屬防護層116連接於第二載板156之黏貼層160，即晶片106的底面130朝向第二載板156。
然後，於步驟S116中，如第5H圖所示，移除第一載板150，以露出接墊126。
然後，於步驟S116之後，倒置(reverse)封膠體154如第5I圖所示，使接墊126朝上。為清楚表示，第5I圖僅繪示出局部的第5H圖。
然後，於步驟S118中，如第5I圖所示，形成第一介電層110於晶片106、封膠104及金屬環繞部102。第一介電層110具有數個第一開孔132，該些第一開孔132對應地露出該些接墊126。
然後，於步驟S120中，如第5J圖所示，形成圖案化導電層112於第一介電層110。圖案化導電層112電性連接接墊126。
然後，於步驟S122中，如第5K圖所示，形成第二介電層114於圖案化導電層112。第二介電層114具有數個第二開孔134，該些第二開孔134露出圖案化導電層112之一部份。
然後，於步驟S124中，如第5L圖所示，對應地形成數個錫球118於該些第二開孔134，以電性連接圖案化導電層112。
然後，於步驟S126中，移除第二載板156。
然後，於步驟S128中，如第5M圖所示，沿著一切割路徑P1切割出數個如第2圖所示之半導體封裝件100。其中，第一介電層110、第二介電層114及封膠104係重疊，切割路徑P1通過重疊之第一介電層110、第二介電層114及封膠104，使切割後之封膠104之外側壁144、第一介電層110之外側壁146及第二介電層114之外側壁148係切齊，如第2圖所示。
第二實施例
請參照第6圖，其繪示依照本發明第二實施例之半導體封裝件之金屬環繞部的示意圖。第二實施例中與第一實施例相同之處沿用相同標號，在此不再贅述。第二實施例與第一實施例不同之處在於，第二實施例的半導體封裝件的金屬環繞部202包括數個金屬件260。
本實施例中，四個金屬件260彼此分離地設置並環繞出凹部224。較佳但非限定地，四個金屬件260的排列外型呈矩形。然此非用以限制本發明，在其它實施態樣中，數個金屬件260的排列外形可以是相異於矩形的其它外形，例如是三角形及多邊形等。
當然，本技術領域的通常知識者應當明暸，金屬件260的數量不限於四個。在其它實施態樣中，金屬件260的數量可以是相異於四個的其它數量，例如是單個、三個或四個以上。
本實施例半導體封裝件的其它元件相似於第一實施例的半導體封裝件100，在此不再重複繪示及贅述。
第三實施例
請參照第7圖，其繪示依照本發明第三實施例之半導體封裝件示意圖。第三實施例中與第一實施例相同之處沿用相同標號，在此不再贅述。第三實施例與第一實施例不同之處在於，第三實施例的半導體封裝件400更包括一連接層462。
連接層462形成於封膠104上，其材質可以是高分子聚合物。連接層462介於金屬防護層416與封膠104之間，可增加金屬防護層416與封膠104的結合性。
以下係介紹本發明第三實施例之半導體封裝件400的製造方法。請參照第8圖，其繪示依照本發明第三實施例之半導體封裝件的製造方法流程圖。
第8圖的步驟S402至S410係相似於第4圖之步驟S102至S110，在此不再贅述。以下從步驟S412開始說明。
於步驟S412中，形成連接層462於封膠104之封膠表面464。
然後，於步驟S414中，形成金屬防護層416於第二金屬表面122及連接層462。
接下來的步驟S416至S430係相似於第4圖之步驟S114至S128，在此不再贅述。
第四實施例
請參照第9圖，其繪示依照本發明第四實施例之半導體封裝件示意圖。第四實施例中與第一實施例相同之處沿用相同標號，在此不再贅述。第四實施例與第一實施例不同之處在於，第四實施例的半導體封裝件500露出金屬環繞部502之外側壁566。
半導體封裝件500包括一金屬環繞部502、一封膠504、晶片106、一第一介電層510、一圖案化導電層512、一第二介電層514、數個錫球518及一金屬防護層516。
第一介電層510、圖案化導電層512、第二介電層514及錫球518相似於第一實施例的第一介電層110、圖案化導電層112、第二介電層114及錫球118，在此不再贅述。
此外，金屬環繞部502之外側壁566、第一介電層510之外側壁546及第二介電層514之外側壁548係切齊。
以下係介紹本發明第四實施例之半導體封裝件500的製造方法。請同時參照第10圖及第11A至11M圖，第10圖繪示依照本發明第四實施例之半導體封裝件的製造方法流程圖，第11A至11M圖繪示第9圖之半導體封裝件的製造示意圖。
步驟S502相似於第4圖的步驟S102，在此不再贅述。以下從步驟S504開始說明。
於步驟S504中，如第11A及11B圖所示，本實施例的數個金屬環繞部彼此連接成為一連續金屬層558。連續金屬層558上具有數個凹部524，例如是貫孔。連續金屬層558設於第一載板150上的黏貼層152。
然後，於步驟S506中，如第11C圖所示，對應地設置晶片106於凹部524內。晶片106連接於第一載板150，每個晶片106包括數個接墊126，接墊126係面向第一載板150的黏貼層152。
然後，於步驟S508中，如第11D圖所示，以封膠104包覆晶片106的側面128及底面130，使封膠504、晶片106及連續金屬層558形成一封膠體554。其中，封膠504覆蓋第二金屬表面522及凹部124。
然後，於步驟S510中，如第11E圖所示，例如以化學機械研磨的方式，去除第二金屬表面522及凹部524上方的封膠504，以露出第二金屬表面522。
然後，於步驟S512中，如第11F圖所示，形成金屬防護層516於第二金屬表面522及封膠504。其中，金屬防護層516覆蓋凹部524之開口540。
此外，在另一實施態樣的半導體封裝件(未繪示)中亦可不形成金屬防護層516。
然後，於步驟S514中，如第11G圖所示，設置封膠體554於一第二載板156之黏貼層160上。其中金屬防護層116連接於黏貼層160，即晶片106的底面130朝向第二載板156。
然後，於步驟S516中，如第11H圖所示，移除第一載板150及黏貼層152，以露出接墊126。
然後，於步驟S516之後，倒置封膠體554如第11I圖所示，使接墊126朝上。為清楚表示，第11I圖僅繪示出局部的第11H圖。
然後，於步驟S518中，如第11I圖所示，形成第一介電層510於晶片106、封膠504及連續金屬層558。第一介電層510具有數個第一開孔532，該些第一開孔532對應定露出該些接墊126。
然後，於步驟S520中，如第11J圖所示，形成圖案化導電層512於第一介電層510。圖案化導電層512電性連接接墊126。
然後，於步驟S522中，如第11K圖所示，形成第二介電層514於圖案化導電層512。其中，第二介電層514具有數個第二開孔534，該些第二開孔534露出圖案化導電層512之一部份。
然後，於步驟S524中，如第11L圖所示，對應地形成數個錫球518於該些第二開孔534，以電性連接圖案化導電層512。
然後，於步驟S526中，移除第二載板156。
然後，於步驟S528中，如第11M圖所示，沿著一切割路徑P2切割出數個如第9圖所示之半導體封裝件500。其中，第一介電層510、第二介電層514及連續金屬層558係重疊。切割路徑P2通過重疊之第一介電層510、第二介電層514及連續金屬層558，使切割後之金屬環繞部502之外側壁566、第一介電層510之外側壁546及第二介電層514之外側壁548係切齊，如第9圖所示。
此外，在另一實施態樣中(未繪示)，第9圖的半導體封裝件500亦可形成如第7圖所示的連接層462。連接層462的形成方式相似於第8圖的步驟S412，在此不再贅述。
第五實施例
請參照第12圖，其繪示依照本發明第五實施例之半導體封裝件示意圖。第五實施例中與第四實施例相同之處沿用相同標號，在此不再贅述。第五實施例與第四實施例不同之處在於，第五實施例的半導體封裝件600省略第四實施例的金屬防護層516且封膠604覆蓋第二金屬表面622及金屬環繞部602的凹部624。
半導體封裝件600包括金屬環繞部602、一封膠604、晶片106、一第一介電層610、一圖案化導電層612、一第二介電層614及數個錫球618。
第一介電層610、圖案化導電層612、第二介電層614及錫球618相似於第四實施例的第一介電層510、圖案化導電層512、第二介電層514及錫球518，在此不再贅述。
此外，金屬環繞部602之外側壁666、第一介電層610之外側壁646及第二介電層614之外側壁648係切齊。
請參照第13圖，其繪示依照本發明第五實施例之半導體封裝件的製造方法流程圖。第13圖的步驟與第10圖的步驟不同之處在於，第13圖的步驟省略第10圖的步驟S510及S512。如此可使步驟S608中形成於第二金屬表面622(第二金屬表面622繪示於第12圖)的封膠保留至步驟S622。
步驟S602至S608相似於第10圖的步驟S502至S508，而步驟S610至S624相似於第10圖的步驟S514至S528，在此不再贅述。
此外，在另一製造方法中，請同時第13圖及第14圖，第14圖繪示第12圖之半導體封裝件之另一製造方法示意圖。於第13圖的步驟S608中，可形成數個貫穿部668於第二金屬表面622上之封膠604。貫穿部668提供一空間，以容納封膠體654於製造過程中因熱膨脹所造成的變形量，防止封膠體654互相擠壓受力而破壞。較佳但非限定地，貫穿部668的外形可以是一環繞晶片106環狀。
在切割步驟S624中，第14圖的貫穿部668可被切除，保留下來的結構即為半導體封裝件600。
第六實施例
請參照第15圖，其繪示依照本發明第六實施例之半導體封裝件示意圖。第六實施例中與第四實施例相同之處沿用相同標號，在此不再贅述。第六實施例與第四實施例不同之處在於，第六實施例的半導體封裝件700的凹部724為金屬環繞部702的凹槽。
凹部724可以利如雷射鑽孔或機械切削的方式製成。
半導體封裝件700包括金屬環繞部702、一封膠704、晶片106、一第一介電層710、一圖案化導電層712、一第二介電層714及數個錫球718。
第一介電層710、圖案化導電層712、第二介電層714及錫球718相似於第四實施例的第一介電層510、圖案化導電層512、第二介電層514及錫球518，在此不再贅述。
此外，金屬環繞部702之外側壁766、第一介電層710之外側壁746及第二介電層714之外側壁748係切齊。
晶片106之底面130設於凹部724的槽底面770。晶片106可透過晶片黏膠(Die Attach Film,DAF)772緊固於槽底面770。封膠704包覆晶片106之側面128。由於本實施例之凹部724係為凹槽，故晶片106的底面130及側面128皆被金屬環繞部702包覆，可有效防止電磁干擾。
以下係詳細介紹本發明第六實施例之半導體封裝件700的製造方法。請同時參照第16圖及第17A至17D圖，第16圖繪示依照本發明第六實施例之半導體封裝件的製造方法流程圖，第17A至17D圖繪示第15圖之半導體封裝件的製造示意圖。步驟S702相似於第四實施例的步驟S502，在此不再贅述，以下從步驟S704開始說明。
於步驟S704中，如第17A圖所示，設置連續金屬層758於第一載板150上的黏貼層152。
本實施例的數個金屬環繞部702彼此連接成為連續金屬層558，連續金屬層758並具有數個凹槽724。
然後，於步驟S706中，如第17B圖所示，對應地設置數個晶片106於該些凹槽724內。晶片106的底面130面向槽底面770。
然後，於步驟S708中，如第17C圖所示，以封膠704包覆晶片106之側面128。
在另一實施態樣中，封膠704在形成過程中可更覆蓋第一金屬表面720及晶片106的接墊126，之後，再以曝光顯影製程形成數個露出接墊126的開口後，再進入下個步驟S710。
然後，於步驟S710中，如第17D圖所示，形成第一介電層710於晶片106及連續金屬層758。為清楚表示，第17D圖僅繪示出局部的第17C圖。第一介電層710具有數個第一開孔732，該些第一開孔732對應地露出該些接墊126。
在其它實施態樣中，步驟S708中的封膠704可覆蓋第一金屬表面720及晶片106的接墊126。然後，於本步驟S710中，第一開孔732再貫穿接墊126上的封膠以露出接墊126。
接下來的步驟S712至S716相似於第四實施例的步驟S520至S524，在此不再贅述。以下從步驟S718開始說明。
然後，於步驟S718中，移除第一載板150及黏貼層152。
接下來的切割步驟S720相似於第四實施例的步驟S528，在此不再贅述。
第七實施例
請參照第18圖，其繪示依照本發明第七實施例之半導體封裝件示意圖。第七實施例中與第六實施例相同之處沿用相同標號，在此不再贅述。第七實施例與第六實施例不同之處在於，第七實施例的半導體封裝件800更包括一接地錫球872，其電性連接於金屬環繞部702。
半導體封裝件800包括金屬環繞部702、一封膠704、晶片106、一第一介電層810、一圖案化導電層812、一第二介電層814及錫球818及872。
第一介電層810形成於金屬環繞部702的第一金屬表面820。第一介電層810更具有第一接地開孔832，其露出金屬環繞部702之一部份。圖案化導電層812更包括一接地部874，對應地形成於第一接地開孔832，以電性連接金屬環繞部702。第二介電層814更具有一第二接地開孔834，其露出圖案化導電層812之接地部874，接地錫球872形成於第二接地開孔834，以電性連接金屬環繞部702。
本實施例的金屬環繞部702可電性連接一接地端(未繪示)，更可提升半導體封裝件防止電磁干擾的能力。舉例來說，接地錫球872可電性連接至一外部電路，例如是電路板上的接地端，使金屬環繞部702電性連接於該外部電路的接地端。
第18圖的半導體封裝件800的製造方式相似於第六實施例的半導體封裝件700，在此不再贅述。
當然，本技術領域的通常知識者應當明瞭，本實施例之金屬環繞部接地的技術特徵亦可應用至上述第一實施例至第七實施例的半導體封裝件，在此不再重複贅述。
第八實施例
請參照第19圖，其繪示依照本發明第八實施例之半導體封裝件示意圖。第八實施例中與第六實施例相同之處沿用相同標號，在此不再贅述。第八實施例與第六實施例不同之處在於，第八實施例的半導體封裝件900露出封膠904。
半導體封裝件900包括一金屬環繞部902、封膠904、晶片106、一第一介電層910、一圖案化導電層912、一第二介電層914及數個錫球918。
第一介電層910、圖案化導電層912、第二介電層914及錫球918相似於第六實施例的第一介電層710、圖案化導電層712、第二介電層714及錫球718，在此不再贅述。
封膠904包覆金屬環繞部902的外側壁942。封膠904的外側壁944、第一介電層910之外側壁946及第二介電層914之外側壁948係切齊。
當然，本技術領域的通常知識者應當明瞭，第七實施例之金屬環繞部接地的技術特徵亦可應用至本實施例，在此便不再贅述。
以下係以第16圖的流程步驟說明本實施之半導體封裝件的製造方法。此處僅就步驟S704、S708及S720作說明，其餘的製造步驟相似於第六實施例中所說明的步驟，在此不再重複贅述。以下就步驟S704、S708及S720作說明。
於步驟S704中，金屬環繞部902為數個分離設置的金屬件，凹部924為金屬件的凹槽。
於步驟S708中，封膠904更形成於該些金屬件之間的空間。
於步驟720中，沿著一切割路徑(未繪示)切割出數個如第19圖所示之半導體封裝件900。其中，切割路徑通過重疊之第一介電層910、第二介電層914及封膠904，使切割後之封膠904之外側壁944、第一介電層910之外側壁946及第二介電層914之外側壁948係切齊。
本發明上述實施例所揭露之半導體封裝件及其製造方法，金屬環繞部圍繞晶片，可有效防止電磁干擾。在一實施例中，金屬環繞部全部被包覆而與環境隔離，故金屬環繞部的材質可以是廉價的金屬或者是不具抗腐蝕性的金屬。
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10、100、400、500、600、700、800、900．．．半導體封裝件
12、116、416、516．．．金屬防護層
14、104、504、604、704、904．．．封膠
16、106．．．晶片
18．．．銲線
20．．．基板
102、202、502、602、702、902．．．金屬環繞部
110、510、610、710、810、910．．．第一介電層
112、512、612、712、812、912．．．圖案化導電層
114、514、614、714、814、914．．．第二介電層
118、518、618、718、818、918．．．錫球
120、720、820．．．第一金屬表面
122、522、622．．．第二金屬表面
124、224、524、624、724、924．．．凹部
126．．．接墊
128．．．側面
130．．．底面
132、532、732．．．第一開孔
134、534．．．第二開孔
136．．．保護層
138．．．主動表面
140、540．．．開口
142、144、146、148、544、546、548、566、646、648、666、746、748、766、942、944、946、948．．．外側壁
150．．．第一載板
152、160．．．黏貼層
154、554、654．．．封膠體
156．．．第二載板
558、758．．．連續金屬層
260．．．金屬件
462．．．連接層
464．．．封膠表面
668．．．貫穿部
770．．．槽底面
772．．．黏膠
832．．．第一接地開孔
834．．．第二接地開孔
872．．．接地錫球
874．．．接地部
P1、P2．．．切割路徑
S．．．空間
第1圖(習知技藝)繪示習知半導體封裝件的示意圖。
第2圖繪示依照本發明第一實施例之半導體封裝件之示意圖。
第3圖繪示第2圖之金屬環繞部的上視圖。
第4圖繪示依照本發明第一實施例之半導體封裝件的製造方法流程圖。
第5A至5M圖繪示第3圖之半導體封裝件的製造示意圖。
第6圖繪示依照本發明第二實施例之半導體封裝件之金屬環繞部的示意圖。
第7圖繪示依照本發明第三實施例之半導體封裝件示意圖。
第8圖繪示依照本發明第三實施例之半導體封裝件的製造方法流程圖。
第9圖繪示依照本發明第四實施例之半導體封裝件示意圖。
第10圖繪示依照本發明第四實施例之半導體封裝件的製造方法流程圖。
第11A至11M圖繪示第9圖之半導體封裝件的製造示意圖。
第12圖繪示依照本發明第五實施例之半導體封裝件示意圖。
第13圖繪示依照本發明第五實施例之半導體封裝件的製造方法流程圖。
第14圖繪示第12圖之半導體封裝件之另一製造方法示意圖。
第15圖繪示依照本發明第六實施例之半導體封裝件示意圖。
第16圖繪示依照本發明第六實施例之半導體封裝件的製造方法流程圖。
第17A至17D圖繪示第15圖之半導體封裝件的製造示意圖。
第18圖繪示依照本發明第七實施例之半導體封裝件示意圖。
第19圖繪示依照本發明第八實施例之半導體封裝件示意圖。
100‧‧‧半導體封裝件
102‧‧‧金屬環繞部
104‧‧‧封膠
106‧‧‧晶片
110‧‧‧第一介電層
112‧‧‧圖案化導電層
114‧‧‧第二介電層
116‧‧‧金屬防護層
118‧‧‧錫球
120‧‧‧第一金屬表面
122‧‧‧第二金屬表面
124‧‧‧凹部
126‧‧‧接墊
128‧‧‧側面
130‧‧‧底面
134‧‧‧第二開孔
136‧‧‧保護層
138‧‧‧主動表面
140‧‧‧開口
142、144、146、148‧‧‧外側壁

Claims (23)

  1. 一種半導體封裝件，包括：一金屬環繞部，環繞出一凹部，該金屬環繞部具有相對之一第一金屬表面與一第二金屬表面；一晶片，設於該凹部，該晶片包括複數個接墊；一封膠，形成於該凹部並包覆該晶片之一側面並露出該些接墊，該封膠具有相對之一第一表面與一第二表面，且該第一表面與該第一金屬表面共平面，該第二表面與該第二金屬表面共平面；一第一介電層，形成於該晶片並具有複數個第一開孔，該些第一開孔露出該些接墊；以及一圖案化導電層，形成於該第一介電層並電性連接該些接墊。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中該金屬環繞部包括複數個金屬件，該些金屬件彼此分離地設置並環繞出該凹部。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中該晶片具有相對應之一主動表面及一底面，該側面連接該底面，該些接墊設於該主動表面上；其中，該封膠更包覆該底面。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中該第一介電層更形成於該第一金屬表面，該半導體封裝件更包括：一金屬防護層，形成於該第二金屬表面並遮蓋該凹部之開口。
  5. 如申請專利範圍第4項所述之半導體封裝件，更包括：一連接層，形成於該封膠；其中，該金屬防護層更形成於該連接層。
  6. 如申請專利範圍第1項所述之半導體封裝件，更包括：一第二介電層，形成於該圖案化導電層；其中，該封膠更包覆該金屬環繞部，該金屬環繞部之外側壁、該第一介電層之外側壁及該第二介電層之外側壁係切齊。
  7. 如申請專利範圍第1項所述之半導體封裝件，其中該凹部為一凹槽，該晶片設於該凹槽的槽底面。
  8. 如申請專利範圍第7項所述之半導體封裝件，更包括：一第二介電層，形成於該圖案化導電層；其中，該金屬環繞部之外側壁、該第一介電層之外側壁及該第二介電層之外側壁係切齊。
  9. 如申請專利範圍第1項所述之半導體封裝件，其中該第一介電層更形成於該金屬環繞部，該第一介電層更具有一第一接地開孔，該第一接地開孔露出該金屬環繞部之一部份，該圖案化導電層更包括一接地部，形成於該第一接地開孔，以電性連接該金屬環繞部；其中，該半導體封裝件更包括一第二介電層，其形成於該圖案化導電層，該第二介電層具有一第二接地開孔，該第二接地開孔露出該接地部，該半導體封裝件更 包括一接地錫球，該接地錫球形成於該第二接地開孔，以電性連接該金屬環繞部。
  10. 一種半導體封裝件的製造方法，包括：提供一第一載板；設置複數個金屬環繞部於該第一載板，各該些金屬環繞部環繞出一凹部；對應地設置複數個晶片於該些凹部，該些晶片連接於該第一載板，各該些晶片包括複數個接墊，該些接墊係面向該第一載板；以一封膠，包覆該些晶片及該些金屬環繞部，以使該封膠、該些晶片及該些金屬環繞部形成一封膠體；設置該封膠體於一第二載板，該些接墊背向該第二載板；移除該第一載板，以露出該些接墊；形成一第一介電層於該些晶片，該第一介電層具有複數個第一開孔，該些第一開孔露出該些接墊；形成一圖案化導電層於該第一介電層，該圖案化導電層電性連接該些接墊；移除該第二載板；以及切割該封膠體，以形成複數個半導體封裝件。
  11. 如申請專利範圍第10項所述之製造方法，其中各該些金屬環繞部具有相對應之一第一金屬表面與一第二金屬表面，該第一金屬表面連接於該第一載板，於以該封膠包覆該些晶片之該步驟中，該封膠更覆蓋該第二金屬表面及該些凹部。
  12. 如申請專利範圍第11項所述之製造方法，其中於以該封膠包覆該些晶片之該步驟之後，該製造方法更包括：去除該第二金屬表面上之該封膠，以露出該第二金屬表面；形成一金屬防護層於該第二金屬表面及該封膠，其中該金屬防護層覆蓋各該些凹部之開口。
  13. 如申請專利範圍第11項所述之製造方法，其中於以該封膠包覆該些晶片之該步驟之後，該製造方法更包括：去除該第二金屬表面上之該封膠，以露出該第二金屬表面；形成一連接層於該封膠；以及形成一金屬防護層於該第二金屬表面及該連接層。
  14. 如申請專利範圍第11項所述之製造方法，其中於以該封膠包覆該些晶片之該步驟之後，該製造方法更包括：形成一貫穿部於該第二金屬表面上之該封膠。
  15. 如申請專利範圍第10項所述之製造方法，其中各該些環繞部的外形為封閉環狀體，該些環繞部彼此分離地設置，於以該封膠包覆該些晶片之該步驟中，該封膠更形成於該些環繞部中相鄰二者之間；該製造方法更包括：形成一第二介電層於該圖案化導電層；於該切割步驟中更包括： 沿著一切割路徑切割出複數個半導體封裝件；其中，該第一介電層、該第二介電層及該封膠係重疊，該切割路徑通過重疊之該第一介電層、該第二介電層及該封膠，使切割後之該封膠之外側壁、該第一介電層之外側壁及該第二介電層之外側壁係切齊。
  16. 如申請專利範圍第10項所述之製造方法，更包括：形成一第二介電層於該圖案化導電層；於該切割步驟中更包括：沿著一切割路徑切割出複數個半導體封裝件；其中，該些金屬環繞部彼此連接成為一連續金屬層，該第一介電層、該第二介電層及該連續金屬層係重疊，該切割路徑通過重疊之該第一介電層、該第二介電層及該連續金屬層，使切割後之該連續金屬層之外側壁、該第一介電層之外側壁及該第二介電層之外側壁係切齊。
  17. 如申請專利範圍第10項所述之製造方法，其中該金屬環繞部包括複數個金屬件，該些金屬件彼此分離地設置以圍繞出該凹部，於以該封膠包覆該些晶片之該步驟中，該封膠更形成於該些金屬件之間；該製造方法更包括：形成一第二介電層於該圖案化導電層；於該切割步驟中更包括：沿著一切割路徑切割出複數個半導體封裝件；其中，該第一介電層、該第二介電層及該封膠係重 疊，該切割路徑通過重疊之該第一介電層、該第二介電層及該封膠，使切割後之該封膠之外側壁、該第一介電層之外側壁及該第二介電層之外側壁係切齊。
  18. 如申請專利範圍第10項所述之製造方法，其中於形成該第一介電層之該步驟中，該第一介電層更形成於該些金屬環繞部，該第一介電層更具有複數個第一接地開孔，各該些第一接地開孔露出對應之該金屬環繞部之一部份；於形成該圖案化導電層之該步驟中，該圖案化導電層更包括複數接地部，對應地形成於該些第一接地開孔，以對應地電性連接該些金屬環繞部；該製造方法更包括：形成一第二介電層於該圖案化導電層，該第二介電層更具有複數個第二接地開孔，該些第二接地開孔對應地露出該些接地部；以及對應地形成複數個接地錫球於該些第二接地開孔，以對應地電性連接該些金屬環繞部。
  19. 如申請專利範圍第10項所述之製造方法，其中於形成該第一介電層之該步驟之前，該製造方法更包括：倒置(reverse)該封膠體。
  20. 一種半導體封裝件的製造方法，包括：提供一載板；設置複數個金屬環繞部於該載板，各該些金屬環繞部環繞出一凹槽；對應地設置複數個晶片於該些凹槽，各該些晶片具有相對應之一主動表面與一底面並包括複數個接墊，該 些接墊設於該主動表面，該底面係面向對應之該凹槽之一槽底面；以一封膠，包覆該些晶片之一側面並露出該些接墊，其中該側面係連接該主動表面與該底面；形成一第一介電層於該晶片，該第一介電層具有複數個第一開孔，該些第一開孔露出該些接墊；形成一圖案化導電層於該第一介電層，該圖案化導電層電性連接該些接墊；移除該載板；以及切割該封膠體，以形成複數個半導體封裝件。
  21. 如申請專利範圍第20項所述之製造方法，其中該些金屬環繞部彼此分離地設置，於以該封膠包覆該些晶片之該步驟中，該封膠更形成於該些金屬環繞部中相鄰二者之間；該製造方法更包括：形成一第二介電層於該圖案化導電層；於該切割步驟中更包括：沿著一切割路徑切割出複數個半導體封裝件；其中，該第一介電層、該第二介電層及該封膠係重疊，該切割路徑通過重疊之該第一介電層、該第二介電層及該封膠，使切割後之該封膠之外側壁、該第一介電層之外側壁及該第二介電層之外側壁係切齊。
  22. 如申請專利範圍第20項所述之製造方法，更包括：形成一第二介電層於該圖案化導電層； 於該切割步驟中更包括：沿著一切割路徑切割出複數個半導體封裝件；其中，該些金屬環繞部彼此連接成為一連續金屬層，該第一介電層、該第二介電層及該連續金屬層係重疊，該切割路徑通過重疊之該第一介電層、該第二介電層及該連續金屬層，使切割後之該連續金屬層之外側壁、該第一介電層之外側壁及該第二介電層之外側壁係切齊。
  23. 如申請專利範圍第20項所述之製造方法，其中於形成該第一介電層之該步驟中，該第一介電層更形成於該些金屬環繞部，該第一介電層更具有複數個第一接地開孔，各該些第一接地開孔露出對應之該金屬環繞部之一部份；於形成該圖案化導電層之該步驟中，該圖案化導電層更包括複數接地部，對應地形成於該些第一接地開孔，以對應地電性連接該些金屬環繞部；該製造方法更包括：形成一第二介電層於該圖案化導電層，該第二介電層更具有複數個第二接地開孔，該些第二接地開孔露出該些接地部；以及對應地形成複數個接地錫球於該些第二接地開孔，以對應地電性連接該些金屬環繞部。
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