TWI466259B - 半導體封裝件、其製造方法及重佈晶片封膠體的製造方法 - Google Patents
半導體封裝件、其製造方法及重佈晶片封膠體的製造方法 Download PDFInfo
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Description
本發明是有關於一種半導體封裝件、其製造方法及重佈晶片封膠體的製造方法,且特別是有關於一種具有對位結構的半導體封裝件、其製造方法及重佈晶片封膠體的製造方法。
近年來電子裝置蓬勃的應用於日常生活中,業界無不致力發展微型且多功能之電子產品,以符合市場需求。
有別於傳統以單一晶片為加工標的的封裝技術,重佈晶片之封膠體級封裝(Chip-redistribution Encapsulant Level Package)是以整片重佈晶片封膠體(Chip-redistribution Encapsulant)作為封裝處理的對象。換言之,相較於傳統之單一晶片封裝,重佈晶片封膠體級封裝是在尚未將個別的晶粒分離之前就對重佈晶片封膠體上之晶粒進行封裝。如此,將簡化晶片封裝之後段製程,同時可節省了封裝製程時間及成本。也就是說,在重佈晶片封膠體表面之元件、線路及其相關之前段製程完成後,即可直接對整片重佈晶片封膠體進行後段製程,接著再進行重佈晶片封膠體切割(saw)的步驟,以形成多個半導體封裝件。因此,重佈晶片之封膠體級封裝已然成為半導體封裝之趨勢。
在製作重佈晶片封膠體時,是將晶圓上的數個晶片
切割下來,然後重新佈置在一載板上。該些晶片中包括數個具有電路功能的半導體晶片及至少二對位晶片(alignment die),對位晶片上具有數個對位標記。在後續的曝光顯影製程中,曝光機台依據重佈晶片封膠體上對位晶片的對位標記將光罩定位於一曝光位置,以進行形成例如是第一介電層、圖案化導電層及第二介電層等結構的曝光製程。
然而,由於載板上的晶片是經過重新排列過,排列後的晶片會產生排列偏差。而光罩本身也會產生對位偏差,導致製作出來的圖案,例如是第一介電層、圖案化導電層及第二介電層的圖案產生嚴重的偏位。請參照第1圖,其繪示習知的對位晶片的排列偏差示意圖。對位晶片100於重佈後產生旋轉偏差,導致對位晶片100上的對位標記102與對位晶片104’上的對位標記106產生一偏差角度A。在後續的曝光製程中,曝光機台依據已偏差的對位標記102及對位標記106’來定位光罩,導致定位後的光罩也對應地產生旋轉偏差,因此使製作出的圖案發生嚴重偏位。
因此,如何提升光罩與載體上晶片的對位精度,以符合在半導體封裝件的尺寸日益縮小的趨勢,實為本產業努力目標。
本發明係有關於一種半導體封裝件、其製造方法及重佈晶片封膠體的製造方法。對位標記形成於晶片,例
如是對位晶片或半導體晶片的幾何中心,使對位標記之間的相對位置不易受到重佈後之晶片旋轉偏差的影響。如此,使後續曝光製程的光罩與對位標記準確地對位,提升所形成之結構圖案的尺寸精密度。
根據本發明之第一方面,提出一種半導體封裝件。半導體封裝件包括一半導體晶片、一封膠、一第一介電層、一圖案化導電層及一第二介電層。半導體晶片包括一接墊並具有一主動表面及一對位標記,對位標記位於半導體晶片之主動表面的幾何中心。封膠包覆半導體晶片之側面,以暴露出主動表面。第一介電層形成於封膠及主動表面之上方,第一介電層具有一第一開孔,第一開孔暴露出接墊。圖案化導電層形成於接墊之一部份及第一介電層。第二介電層形成於圖案化導電層之一部份。
根據本發明之第二方面,提出一種半導體封裝件之製造方法。製造方法包括以下步驟:提供一具有一黏貼層之載板;重佈數個半導體晶片於黏貼層上,半導體晶片包括一設有一接墊之主動表面,主動表面面向黏貼層,該些半導體晶片中至少二者具有一對位標記,對位標記位於對應的主動表面的幾何中心;以一封膠,包覆半導體晶片之側面,使封膠及半導體晶片形成一重佈晶片封膠體;移除載板及黏貼層,使重佈晶片封膠體露出主動表面;形成一第一介電層於封膠及主動表面之上方,第一介電層具有數個第一開孔,第一開孔暴露出接墊;形成一圖案化導電層於接墊之一部份及第一介電層;形成一第二介電層於圖案化導電層之一部份,第二
介電層具有數個第二開孔,第二開孔暴露出圖案化導電層之另一部份;形成數個銲球於該些第二開孔,以使銲球與圖案化導電層電性連接;以及,切割重佈晶片封膠體成為數個半導體封裝件。
根據本發明之第三方面,提出一種重佈晶片封膠體之製造方法。製造方法包括以下步驟:提供一具有一黏貼層之載板;重佈數個半導體晶片於黏貼層上,半導體晶片具有一主動表面,主動表面面向黏貼層,該些半導體晶片中至少二者具有一對位標記,對位標記位於對應的主動表面的幾何中心;以一封膠,包覆晶片的側面,使封膠及半導體晶片形成重佈晶片封膠體;以及,移除載板及黏貼層,使重佈晶片封膠體露出半導體晶片的主動表面。
根據本發明之第四方面,提出一種重佈晶片封膠體的製作方法。製造方法包括以下步驟:提供一晶圓,晶圓包括至少二對位晶片及數個半導體晶片,對位晶片具有一對位表面,半導體晶片包括一接墊並具有一主動表面;於對位表面形成一對位標記,對位標記位於對應的對位晶片的對位表面的幾何中心;提供一具有一黏貼層之載板;重佈半導體晶片及對位晶片於黏貼層上,其中主動表面及對位表面面向黏貼層;以一封膠,包覆對位晶片的側面及半導體晶片的側面,使封膠、對位晶片及半導體晶片形成重佈晶片封膠體;以及,移除載板及黏貼層,使重佈晶片封膠體露出半導體晶片之主動表面及對位晶片之對位表面。
為讓本發明之上述內容能更明顯易懂,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下:
以下係提出較佳實施例作為本發明之說明,然而實施例所提出的內容,僅為舉例說明之用,而繪製之圖式係為配合說明,並非作為限縮本發明保護範圍之用。再者,實施例之圖示亦省略不必要之元件,以利清楚顯示本發明之技術特點。
請參照第2A圖,其繪示依照本發明第一實施例之半導體封裝件之示意圖。半導體封裝件200包括一半導體晶片202、一封膠204、一第一介電層206、一圖案化導電層208及一第二介電層210。其中圖案化導電層208例如是重新佈線層(Redistribution layer,RDL)。
半導體晶片202包括一保護層224、一接墊212及一對位標記216並具有一主動表面214。接墊212及對位標記216形成於主動表面214上。保護層224形成於主動表面214並覆蓋對位標記216且具有一暴露出接墊212的保護層開孔(未標示)。其中保護層224的材質為一透明材質。
對位標記216位於半導體晶片202之主動表面214的幾何中心。封膠204包覆半導體晶片202之側面218,以暴露出主動表面214。
第一介電層206形成於封膠204及保護層224上,即主動表面214之上方。第一介電層206具有一第一開孔220及第一對位結構242,第一開孔220暴露出接墊212。
圖案化導電層208形成於接墊212之一部份及第一介電層206。圖案化導電層208具有一第二對位結構244。
請參照第2B圖,其繪示第2A圖中往方向V1觀看到的對位標記、第一對位結構及第二對位結構示意圖。對位標記216的外型為十字型,第一對位結構242及第二對位結構244的外型及位置可與對位標記216相對應。其中,第一對位結構242可為一凹槽,而第二對位結構244可圍繞於凹槽之開口的周緣。
第二介電層210形成於圖案化導電層208之一部份。第二介電層210具有數個第二開孔226,第二開孔226暴露出圖案化導電層208之另一部份。半導體封裝件200更包括數個銲球228,銲球228形成於第二開孔226上,以使銲球228與圖案化導電層208電性連接。其中,部份之第二開孔226重疊於封膠204,使銲球228可延伸至與封膠204重疊,以增加半導體封裝件200的輸出/輸入接點數目。
此外,第一介電層206之側面230、第二介電層210之側面232及封膠204之側面234係實質上齊平。
請同時參照第3圖,其繪示依照本發明第一實施例之半導體封裝件之製造方法流程圖。請同時參照第4A圖至第4I圖,其繪示第2A圖之半導體封裝件之製造示意
圖。
於步驟S302中,如第4A圖所示,提供一具有一黏貼層236之載板238。
然後,於步驟S304中,如第4B圖所示,重佈數個半導體晶片202於黏貼層236上。如第4B圖中局部B之放大示意圖所示,半導體晶片202包括保護層224並具有一設有一接墊212的主動表面214。主動表面214面向黏貼層236。
半導體晶片202原本形成於晶圓(未繪示)上,依據晶圓上的半導體晶片202的位置,將半導體晶片202切割下來後,重佈於載板238上。
半導體晶片202中至少二者具有對位標記216,對位標記216位於對應之主動表面214的幾何中心。請參照第5圖,其繪示第4B圖中半導體晶片的上視圖。為避免圖示過於複雜,第5圖僅繪示對位標記216。半導體晶片202的主動表面214例如是矩形,對位標記216位於矩形的幾何中心C1。如此,就算重佈後的半導體晶片202旋轉,例如是繞著矩形的幾何中心C1旋轉,不致使偏差角度過大而導致後續製作出的圖案產生嚴重偏位。
於本實施例中,對位標記216形成於具電路功能的半導體晶片202上而非形成於不具電路功能的對位晶片上。故,在晶圓製作階段中可將原本要形成對位晶片的空間,改以形成半導體晶片202,使本實施例最後所得到的半導體封裝件200的數量增多。
雖然第5圖中的對位標記216以十字型為例作說
明,然於其它實施態樣中,對位標記216也可以是其它外型。只要能夠讓光罩順利對位的外型即可,對位標記216的外型並不受本實施例所限制。
然後,於步驟S306中,如第4C圖所示,以一封膠204,包覆半導體晶片202之側面218,使封膠204及半導體晶片202形成一重佈晶片封膠體240。
然後,如第4D圖所示,於步驟S308中,移除載板238及黏貼層236,使重佈晶片封膠體240露出主動表面214。
第4D圖之主動表面214係朝下。然,透過倒置(invert)重佈晶片封膠體240的動作,可使主動表面214朝上,如第4E圖所示。
然後,於步驟S310中,如第4E圖所示,形成第一介電層206於封膠204及主動表面214上方的保護層224。第一介電層206具有數個第一開孔220,第一開孔220暴露出接墊212。
於形成第一介電層206的過程中,同時於第一介電層206形成一第一對位結構242。第一對位結構242為一凹槽,凹槽之開口範圍大於對位標記216的外輪廓,使對位標記216從凹槽露出。如此,下一道曝光製程之光罩可依據對位標記216或第一對位結構242來進行對位。
於形成第一介電層206的過程中,為了與對位標記216對位,光罩上的對位圖案(未繪示)的外型及位置與對位標記216相對應。例如,光罩上的對位圖案與對位標記216的外型同為十字型。並且,於第一介電層206
形成的過程中,第一介電層206上同時形成對應於對位圖案的第一對位結構242。因此,第一對位結構242的外型及位置分別對應於對位標記216的外型及位置,如第4E圖中局部C之放大上視圖所示。
由於第一對位結構242可為貫穿第一介電層206的凹槽,故可暴露出第一介電層206下方的結構,例如是保護層224。
然後,如第4F圖所示,於步驟S312中,形成圖案化導電層208於接墊212之一部份及第一介電層206。
於本步驟S312中,曝光機台可依據對位標記216或第一對位結構242,將光罩定位於一曝光位置,以進行形成圖案化導電層208的曝光製程。
於形成圖案化導電層208的過程中,為了與對位標記216或第一對位結構242對位,光罩上的對位圖案(未繪示)的外型及位置與對位標記216或第一對位結構242相對應。並且,於圖案化導電層208形成的過程中,圖案化導電層208上同時形成對應於光罩上的對位圖案的第二對位結構244。因此,第二對位結構244的外型及位置分別對應於對位標記216的外型及位置,如第4F圖中局部D之放大上視圖所示。
然後,於步驟S314中,如第4G圖所示,形成第二介電層210於圖案化導電層208之一部份。第二介電層210具有數個第二開孔226,第二開孔226暴露出圖案化導電層208之另一部份。至少部份之第二開孔226往外延伸至與封膠204重疊,以提高輸出/輸入接點數目。
於本步驟S314中,曝光機台可依據對位標記216、第一對位結構242或第二對位結構244,將光罩定位於一曝光位置,以進行形成第二介電層210的曝光製程。
此外,由於第二介電層210之至少一部份填入呈凹槽的第一對位結構242內,故第二介電層210的上表面具有一略微凹陷的凹陷區246,如第4G圖中局部E的放大示意圖所示。然此非用以限制本發明,當第二介電層210的厚度足夠厚時,從外觀上可能不會呈現凹陷外形。
然後,於步驟S316中,如第4H圖所示,形成數個銲球228於第二開孔226,以使銲球228與圖案化導電層208電性連接。
然後,於步驟S318,如第4I圖所示,沿著切割路徑P,切割形成有第一介電層206及第二介電層210的重佈晶片封膠體240,使其成為數個半導體封裝件200。
切割路徑P經過第一介電層206、第二介電層210及封膠204的重疊處,以使切割後之半導體封裝件200中第一介電層206之側面230、第二介電層210之側面232及封膠204之側面234實質上齊平。
請參照第6圖,其繪示依照本發明第二實施例之重佈晶片封膠體示意圖。於第二實施例中,與第一實施例相同之處沿用相同標號,在此不再贅述。第二實施例之重佈晶片封膠體340與第一實施例之重佈晶片封膠體240不同之處在於,重佈晶片封膠體340更包括二具有對位
標記216的對位晶片342,而重佈晶片封膠體340上的半導體晶片202可不包含對位標記216。
對位晶片342包括對位標記216,對位標記216位於對應之對位晶片342的對位表面344的幾何中心。如此,就算重佈後的對位晶片342旋轉,例如是繞著其幾何中心旋轉,仍不致使偏差角度過大而導致後續製作出的圖案產生嚴重偏位。
以下說明第6圖所示之重佈晶片封膠體340的製造方法。請同時參照第7圖及第8A至8D圖,第7圖繪示依照本發明第二實施例之重佈晶片封膠體的製造方法,第8A至8D圖繪示第二實施例之重佈晶片封膠體的製造示意圖。
於步驟S702中,如第8A圖所示,提供一晶圓346。晶圓包括二對位晶片342及數個半導體晶片202。
然後,於步驟S704中,如第8B圖所示,於對位晶片342的對位表面344,形成對位標記216。對位標記216位於對位表面344的幾何中心。
然後,於步驟S706中,提供如第4A圖所示之具有黏貼層236的載板238。
然後,於步驟S708中,依據晶圓346上半導體晶片202及對位晶片342的位置,切割晶圓346成為數個半導體晶片202及數個對位晶片342。之後,重佈半導體晶片202及對位晶片342於黏貼層236上,如第8C圖所示。其中,主動表面214及對位表面344面向黏貼層236。
然後,於步驟S710中,如第8D圖所示,以封膠204,
包覆對位晶片342的側面348及半導體晶片202的側面350,使封膠204、對位晶片342及半導體晶片202形成重佈晶片封膠體340。
然後,移除載板236及黏貼層238,使重佈晶片封膠體340露出主動表面214及對位表面342,如第6圖所示。第6圖所示之重佈晶片封膠體340的姿態為第8D圖所示的重佈晶片封膠體340倒置後的姿態。
對位標記216可作為後續製程的光罩對位用,此於第一實施例中揭露的技術內容中已說明,在此不再贅述。
如上述之第一及第二實施例可知,對位標記216可形成於晶圓346上的對位晶片342或半導體晶片202上,使對位標記216的設置形式具有多種實施態樣,增加製程的規劃彈性。
請參照第9圖,其繪示依照本發明第三實施例之半導體封裝件示意圖。於第三實施例中,與第一實施例相同之處沿用相同標號,在此不再贅述。第三實施例之半導體封裝件400與第一實施例之半導體封裝件200不同之處在於,半導體封裝件400的第一對位結構402沿著第一介電層406的延伸方向與對位標記216錯開,而第二對位結構404沿著圖案化導電層408的延伸方向與對位標記216錯開。
進一步地說,第一實施例的第一對位結構242及第二對位結構244的外型及位置可與對位標記216的外型
及位置相對應。然,第二實施例之第一對位結構404及第二對位結構402的位置亦可與對位標記216錯開。並且,第一對位結構404及第二對位結構402的外型亦可不同於對位標記216的外型。
詳細地說,於形成第一介電層406的過程中,第一對位結構404並非透過光罩上的對位圖案(未繪示)形成,而是透過光罩中其它的光罩圖案(未繪示)所形成。故,第一對位結構404的外型及位置可不對應於對位標記216的外型及位置。於此情況下所形成的第一對位結構404仍可提供下一道曝光製程的光罩進行對位用。如此,可增加用以形成第一對位結構404之光罩的設計彈性。
此外,本實施例之第一對位結構404以同時重疊於主動表面214及封膠204為例作說明。然此非用以限制本發明,於其它實施態樣中,第一對位結構404亦可僅重疊於主動表面214與封膠204之一者。
此外,於形成圖案化導電層408的過程中,第二對位結構402並非透過光罩上的對位圖案(未繪示)形成,而是透過光罩中其它的光罩圖案(未繪示)所形成。故,第二對位結構402的外型及位置可不對應於對位標記216的外型及位置。於此情況下所形成的第二對位結構402仍可提供下一道曝光製程的光罩進行對位用。如此,可增加用以形成第二對位結構402之光罩的設計彈性。
另外,本實施例的第二對位結構402以與封膠204重疊為例作說明。然此非用以限制本發明,於其它實施
態樣中,第二對位結構402亦可重疊於主動表面214或同時重疊於主動表面214及封膠204。
第一對位結構404及第二對位結構402的位置及外型是否要與對位標記216相對應,可視製程需求而定,本發明不作任何限制。舉例來說,在其它實施態樣中,第一對位結構404的位置及外型也可與對位標記216的位置及外型相對應,而第二對位結構402的位置及外型則不與對位標記216的位置及外型相對應。或者,第一對位結構404的位置及外型不與對位標記216的位置及外型相對應,而第二對位結構402的位置及外型則與對位標記216的位置及外型相對應。
第一對位結構404的形成步驟相似於第一實施例中的步驟S310,而第二對位結構402的形成步驟相似於第一實施例中步驟S312,在此不再贅述。
本發明上述實施例所揭露之半導體封裝件、其製造方法及重佈晶片封膠體的製造方法,具有多項優點,列舉部份優點說明如下:
(1).對位標記形成於晶片,例如是對位晶片或半導體晶片的幾何中心,使對位標記之間的相對位置不易受到重佈後的晶片旋轉偏差的影響。如此,使後續曝光製程的光罩與對位標記準確地對位,提升所形成之結構圖案的尺寸精密度。
(2).對位標記可形成於具電路功能的半導體晶片上而不形成於不具電路功能的對位晶片上。故,在晶圓製作階段中可將原本要形成對位晶片的空間,改以形成半
導體晶片後,使本實施例最後所得到的半導體封裝件的數量增多。
(3).第一介電層的第一對位結構的位置與外型及圖案化導電層的第二對位結構的位置與外型可與晶片上的對位標記相對應。或者,第一介電層的第一對位結構的位置與外型及圖案化導電層的第二對位結構的位置與外型亦可不與晶片上的對位標記相對應。如此,可增加形成第一對位結構及第二對位結構之光罩的設計彈性。
綜上所述,雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100、104’、342‧‧‧對位晶片
102、106’、216‧‧‧對位標記
200、400‧‧‧半導體封裝件
202‧‧‧半導體晶片
204‧‧‧封膠
206、406‧‧‧第一介電層
208、408‧‧‧圖案化導電層
210‧‧‧第二介電層
212‧‧‧接墊
214‧‧‧主動表面
218‧‧‧側面
220‧‧‧第一開孔
224‧‧‧保護層
226‧‧‧第二開孔
228‧‧‧銲球
230、232、234‧‧‧側面
236‧‧‧黏貼層
238‧‧‧載板
240、340‧‧‧重佈晶片封膠體
242、404‧‧‧第一對位結構
244、402‧‧‧第二對位結構
246‧‧‧凹陷區
346‧‧‧晶圓
A‧‧‧偏差角度
B、C、D、E‧‧‧局部
C1‧‧‧幾何中心
V1‧‧‧方向
第1圖繪示習知的對位晶片的排列偏差示意圖。
第2A圖繪示依照本發明第一實施例之半導體封裝件之示意圖。
第2B圖繪示第2A圖中往方向V1觀看到的對位標記、第一對位結構及第二對位結構示意圖。
第3圖繪示依照本發明第一實施例之半導體封裝件之製造方法流程圖。
第4A圖至第4I圖繪示第2A圖之半導體封裝件之製造示意圖。
第5圖繪示第4B圖中半導體晶片的上視圖。
第6圖繪示依照本發明第二實施例之重佈晶片封膠體示意圖。
第7圖繪示依照本發明第二實施例之重佈晶片封膠體的製造方法。
第8A至8D圖繪示第二實施例之重佈晶片封膠體的製造示意圖。
第9圖繪示依照本發明第三實施例之半導體封裝件示意圖。
216‧‧‧對位標記
200‧‧‧半導體封裝件
202‧‧‧半導體晶片
204‧‧‧封膠
206‧‧‧第一介電層
208‧‧‧圖案化導電層
210‧‧‧第二介電層
212‧‧‧接墊
214‧‧‧主動表面
218‧‧‧側面
220‧‧‧第一開孔
224‧‧‧保護層
226‧‧‧第二開孔
228‧‧‧銲球
230、232、234‧‧‧側面
242‧‧‧第一對位結構
244‧‧‧第二對位結構
V1‧‧‧方向
Claims (28)
- 一種半導體封裝件,至少包括:一半導體晶片,包括一接墊及一對位標記並具有一主動表面,該對位標記位於該半導體晶片之該主動表面的幾何中心;一封膠,係包覆該半導體晶片之側面,以暴露出該主動表面;一第一介電層,形成於該封膠及該主動表面之上方,該第一介電層具有一第一開孔及一第一對位結構,該第一對位結構的外型及位置分別對應於該對位標記的外型及位置,該第一開孔暴露出該接墊;一圖案化導電層,形成於該接墊之一部份及該第一介電層;以及一第二介電層,形成於該圖案化導電層之一部份。
- 如申請專利範圍第1項所述之半導體封裝件,其中該第一對位結構為一凹槽,該凹槽之開口範圍大於該對位標記之外輪廓,使該對位標記從該凹槽露出。
- 如申請專利範圍第1項所述之半導體封裝件,其中該第一對位結構為一凹槽,該凹槽係貫穿該第一介電層並裸露出該封膠。
- 如申請專利範圍第3項所述之半導體封裝件,其中該第二介電層之至少一部份係填入該凹槽。
- 如申請專利範圍第1項所述之半導體封裝件,其中該至少一對位結構為一凹槽,該第二介電層之至少一部份係填入該凹槽,該第二介電層具有一凹陷區,該凹 陷區位於該第二介電層中對應於該凹槽的上表面。
- 如申請專利範圍第1項所述之半導體封裝件,其中該第一介電層具有一第一對位結構,該第一對位結構沿著該第一介電層的延伸方向與該對位標記錯開。
- 如申請專利範圍第1項所述之半導體封裝件,其中該圖案化導電層具有一第二對位結構,該第二對位結構沿著該圖案化導電層的延伸方向與該對位標記錯開。
- 如申請專利範圍第1項所述之半導體封裝件,其中該圖案化導電層具有一第二對位結構,該第二對位結構的外型及位置分別對應於該對位標記的外型及位置。
- 如申請專利範圍第8項所述之半導體封裝件,其中該第一介電層具有一第一對位結構,該第一對位結構為一凹槽,該凹槽的外型及位置分別對應於該對位標記的外型及位置,且該凹槽之開口範圍大於該對位標記之外輪廓,使該對位標記從該凹槽露出;其中,該第二對位結構圍繞於該凹槽之開口的周緣。
- 如申請專利範圍第1項所述之半導體封裝件,其中該半導體晶片更包括:一保護層,形成於該晶片之該主動表面上並覆蓋該對位標記且具有一暴露出該接墊之保護層開孔;其中,該保護層之材質為一透明材質且該第一介電層形成於該保護層上。
- 如申請專利範圍第10項所述之半導體封裝件,其中該第一對位結構為一凹槽,其中該凹槽係貫穿該第一介電層並裸露出該保護層。
- 如申請專利範圍第10項所述之半導體封裝件,其中該第二介電層之至少一部份係填入該凹槽。
- 如申請專利範圍第1項所述之半導體封裝件,其中該第二介電層具有複數個第二開孔,該些第二開孔暴露出該圖案化導電層之另一部份,該半導體封裝件更包括複數個銲球,該些銲球形成於該些第二開孔上,以使該些銲球與該圖案化導電層電性連接;其中,至少部份之該些第二開孔重疊於該封膠。
- 一種半導體封裝件之製造方法,包括:提供一具有一黏貼層之載板;重佈複數個半導體晶片於該黏貼層上,各該些半導體晶片分別具有一設有一接墊的主動表面,各該些主動表面面向該黏貼層,該些半導體晶片中至少二者具有一對位標記,各該些對位標記位於對應之該主動表面的幾何中心;以一封膠,係包覆該些半導體晶片之側面,使該封膠及該些半導體晶片形成一重佈晶片封膠體;移除該載板及該黏貼層,使該重佈晶片封膠體露出該些主動表面;形成一第一介電層於該封膠及該些主動表面之上方,該第一介電層具有複數個第一開孔及一第一對位結構,該第一對位結構的外型及位置分別對應於該對位標記的外型及位置,該些第一開孔暴露出該些接墊;形成一圖案化導電層於該接墊之一部份及該第一介電層; 形成一第二介電層於該圖案化導電層之一部份,該第二介電層具有複數個第二開孔,該些第二開孔暴露出該圖案化導電層之另一部份;形成複數個銲球於該些第二開孔,以使該些銲球與該圖案化導電層電性連接;以及切割該重佈晶片封裝體成為複數個半導體封裝件。
- 如申請專利範圍第14項所述之製造方法,其中該第一對位結構為一凹槽,該凹槽之開口範圍大於該對位標記之外輪廓,使該對位標記從該凹槽露出。
- 如申請專利範圍第14項所述之製造方法,其中於形成該第一介電層之該步驟中包括:形成一第一對位結構於該第一介電層,該第一對位結構沿著該第一介電層的延伸方向與該對位標記錯開。
- 如申請專利範圍第14項所述之製造方法,其中形成該圖案化導電層之該步驟中包括:形成一第二對位結構於該圖案化導電層,該第二對位結構重疊於該封膠與該主動表面中至少一者。
- 如申請專利範圍第14項所述之製造方法,其中形成該圖案化導電層之該步驟中包括:形成一第二對位結構於該圖案化導電層,該第二對位結構的外型及位置分別對應於該對位標記的外型及位置。
- 如申請專利範圍第18項所述之製造方法,於形成該第一介電層之該步驟中包括:形成一第一對位結構於該第一介電層,該第一對位 結構為一凹槽,該凹槽的外型及位置分別對應於該對位標記的外型及位置,且該凹槽之開口範圍大於該對位標記之外輪廓,使該對位標記從該凹槽露出;其中,該第二對位結構圍繞於該凹槽之開口的周緣。
- 如申請專利範圍第14項所述之製造方法,其中形成該圖案化導電層之該步驟中包括:形成一第二對位結構於該圖案化導電層,該第二對位結構沿著該圖案化導電層的延伸方向與該對位標記錯開。
- 如申請專利範圍第14項所述之製造方法,其中該半導體晶片更包括:一保護層,形成於該主動表面並覆蓋該對位標記且具有一暴露出該接墊之保護層開孔;其中,該保護層之材質為一透明材質且該第一介電層位於該保護層上。
- 一種重佈晶片封膠體之製造方法,用以形成一重佈晶片封裝體,該製造方法包括:提供一具有一黏貼層之載板;重佈複數個半導體晶片於該黏貼層上,各該些半導體晶片分別具有一主動表面,各該些主動表面面向該黏貼層,該些半導體晶片中至少二者具有一對位標記,該對位標記位於對應之該主動表面的幾何中心;以一封膠,係包覆該些晶片之側面,使該封膠及該些半導體晶片形成該重佈晶片封膠體;移除該載板及該黏貼層,使該重佈晶片封膠體露出 各該些半導體晶片之該主動表面;形成一第一介電層於該封膠及該些主動表面之上方;以及形成一第一對位結構於該第一介電層,該第一對位結構的外型及位置分別對應於該對位標記的外型及位置。
- 如申請專利範圍第22項所述之製造方法,其中該第一對位結構為一凹槽,該凹槽之開口範圍大於該對位標記之外輪廓,使該對位標記從該凹槽露出。
- 如申請專利範圍第22項所述之製造方法,更包括:形成一第一介電層於該封膠及該些主動表面之上方;以及形成一第一對位結構於該第一介電層,該第一對位結構沿著該第一介電層的延伸方向與該對位標記錯開。
- 如申請專利範圍第22項所述之製造方法,更包括:形成一第一介電層於該封膠及該些主動表面之上方;形成一圖案化導電層於該第一介電層,該圖案化導電層形成於該接墊之一部份及該第一介電層;以及形成一第二對位結構於該圖案化導電層,該第二對位結構沿著該圖案化導電層的延伸方向與該對位標記錯開。
- 如申請專利範圍第22項所述之製造方法,更包括: 形成一第一介電層於該封膠及該些主動表面之上方;形成一圖案化導電層於該第一介電層;以及形成一第二對位結構於該圖案化導電層,該第二對位結構的外型及位置分別對應於該對位標記的外型及位置。
- 如申請專利範圍第26項所述之製造方法,更包括:形成一第一對位結構於該第一介電層,該第一對位結構為一凹槽,該凹槽的外型及位置分別對應於該對位標記的外型及位置,且該凹槽之開口範圍大於該對位標記之外輪廓,使該對位標記從該凹槽露出;其中,該第二對位結構圍繞於該凹槽之開口的周緣。
- 一種重佈晶片封膠體的製作方法,用以形成一重佈晶片封裝體,該製造方法包括:提供一晶圓,該晶圓包括至少二對位晶片及複數個半導體晶片,各該至少二對位晶片分別具有一對位表面,各該些半導體晶片分別具有一設有一接墊的主動表面;於各該些對位表面,形成一對位標記,各該些對位標記位於對應之該對位晶片之該對位表面的幾何中心;提供一具有一黏貼層之載板;重佈該些半導體晶片及該至少二對位晶片於該黏貼層上,該些主動表面及該至少二對位表面面向該黏貼層;以一封膠,包覆該至少二對位晶片之側面及該些半 導體晶片之側面,使該封膠、該至少二對位晶片及該些半導體晶片形成該重佈晶片封膠體;移除該載板及該黏貼層,使該重佈晶片封膠體露出各該些半導體晶片之該主動表面及各該至少二對位晶片之該對位表面;形成一第一介電層於該封膠及該些主動表面之上方;以及形成一第一對位結構於該第一介電層,該第一對位結構的外型及位置分別對應於該對位標記的外型及位置。
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