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Package carrier, semiconductor package, and process for fabricating same

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Publication number
US20110084372A1
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US
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Patent type
Prior art keywords
conductive
electrically
layer
fig
package
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US12904876
Inventor
Yuan-Chang Su
Shih-Fu Huang
Chia-Cheng Chen
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L2224/27011Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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Abstract

A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • [0001]
    This application claims the benefit of U.S. Provisional Application No. 61/251,396, filed on Oct. 14, 2009, U.S. Provisional Application No. 61/294,519, filed on Jan. 13, 2010, and Taiwan Application No. 99112317, filed on Apr. 20, 2010, the disclosures of which are incorporated herein by reference in their entirety.
  • FIELD OF THE INVENTION
  • [0002]
    The present invention relates to a semiconductor package. More particularly, the present invention relates to a package carrier, a package structure, and a process for fabricating a package carrier and a package structure.
  • BACKGROUND
  • [0003]
    A chip package serves to protect a bare chip, reduce a density of chip contacts, and provide a good heat dissipation effect for the chip. A common packaging process is to install the chip onto a package carrier, and contacts of the chip are electrically connected to the package carrier. Therefore, distribution of the contacts of the chip can be rearranged through the package carrier to cope with a contact distribution of a next stage external device.
  • [0004]
    As light weight, compactness, and high efficiency have become typical requirements of consumer electronic and communication products, chip packages should provide superior electrical properties, small overall volume, and a large number of I/O ports. Package carriers used in these chip packages often have multiple metal layers that can be electrically connected through interconnections. As the size of chip packages decreases, these interconnections can become smaller and more closely spaced, which can increase the cost and complexity of packaging processes.
  • [0005]
    It is against this background that a need arose to develop the package carriers, the package structures, and processes described herein.
  • SUMMARY
  • [0006]
    In an embodiment, a package carrier includes: (1) a dielectric layer having a plurality of openings; (2) a first conductive pattern, disposed adjacent to a first surface of the dielectric layer, the first conductive pattern including a plurality of first pads; and (3) a plurality of conductive vias disposed in respective ones of the openings, wherein each conductive via includes a first via segment, connected to at least one of the first pads, and a second via segment, connected to the first via segment, such that a lateral extent of the first via segment is different from a lateral extent of the second via segment.
  • [0007]
    In another embodiment, a semiconductor package includes: (1) a package carrier, including: a dielectric layer; a top conductive pattern, disposed adjacent to a top surface of the dielectric layer, and including a plurality of first pads; a bottom conductive pattern, disposed adjacent to a bottom surface of the dielectric layer, and including a plurality of second pads; a plurality of conductive vias, embedded in the dielectric layer and extending between the top conductive pattern and the bottom conductive pattern, wherein each conductive via includes a first segment, connected to at least one of the first pads, and a second segment, connected to at least one of the second pads; and (2) a chip, attached to the package carrier and connected to the first pads.
  • [0008]
    In a further embodiment, a semiconductor fabrication process includes: (1) forming a first conductive pattern including a plurality of first pads; (2) forming a plurality of first via segments on at least some of the first pads; (3) providing a dielectric layer having a plurality of first openings corresponding to the first via segments; (4) applying the dielectric layer to the first conductive pattern and the first via segments; (5) forming a plurality of second openings in the dielectric layer, such that the first via segments are exposed by the second openings; and (6) forming a plurality of second via segments on the first via segments and at least partially within the second openings, such that a diameter of the first via segment is different than a diameter of the second via segment.
  • [0009]
    Other aspects and embodiments of the invention are also contemplated. The foregoing summary and the following detailed description are not meant to restrict the invention to any particular embodiment but are merely meant to describe some embodiments of the invention.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0010]
    For a better understanding of the nature and objects of some embodiments of the invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings. In the drawings, like reference numbers denote like elements, unless the context clearly dictates otherwise.
  • [0011]
    FIG. 1A through FIG. 1H are cross-sectional views of semiconductor packages according to various embodiments of the invention.
  • [0012]
    FIG. 2-1 through FIG. 2-10 illustrate a process for fabricating a package carrier according to an embodiment of the invention.
  • [0013]
    FIG. 3-1 through FIG. 3-10 illustrate a process for fabricating a package carrier according to another embodiment of the invention.
  • DETAILED DESCRIPTION
  • [0014]
    FIG. 1A is a cross-sectional view of a semiconductor package 10 a according to an embodiment of the invention. Referring to FIG. 1A, the package 10 a includes a package carrier 100 a (or other substrate), a set of solder balls 102 (or other electrically conductive bumps), a chip 104 (or other active or passive semiconductor device), a set of bonding wires 106, and an encapsulant 108.
  • [0015]
    In particular, the package carrier 100 a includes a dielectric layer 110, a first electrically conductive pattern 120, a set of first electrically conductive vias, a second electrically conductive pattern 140, a first solder mask layer 150, and a second solder mask layer 160. In the illustrated embodiment, the first conductive vias correspond to first electrically conductive posts 130, although pillars and other hollow or solid structures can be used. The dielectric layer 110 includes a first surface 112 and a second surface 114 opposite to the first surface 112. The first electrically conductive pattern 120 is embedded within the dielectric layer 110 adjacent to the first surface 112 of the dielectric layer 110, and includes a set of first pads 122. Here, the first electrically conductive pattern 120 can be regarded as an embedded circuit, and an exposed surface (e.g., a top surface) of the first electrically conductive pattern 120 is aligned (e.g., substantially aligned) with the first surface 112 of the dielectric layer 110. The dielectric layer 110 can include a resin material, such as ammonium bifluoride, ajinomoto build-up film (ABF), bismaleimide triazine (BT), polyimide (PI), liquid crystal polymer (LCP), epoxy resin, or a combination thereof. These resin materials can be mixed with glass fibers, such as in the form of a fiber pad or other types of fibers to strengthen the dielectric layer 110. The first electrically conductive pattern 120 and the second electrically conductive pattern 140 can include a metal, a metal alloy, or other electrically conductive material.
  • [0016]
    The first electrically conductive posts 130 extend through the dielectric layer 110, wherein each of the first electrically conductive posts 130 includes a first electrically conductive post segment 132 (or, more generally, a first via segment) connected to a corresponding first pad 122 and a second electrically conductive post segment 134 (or, more generally, a second via segment) connected to the first electrically conductive post segment 132. In the present embodiment, a patterned etching stop layer 180 (or other barrier layer) is located between the first electrically conductive post segments 132 and the first pads 122, wherein the first electrically conductive posts 130 can be connected to the first electrically conductive pattern 120 through the patterned etching stop layer 180 that is formed of, for example, nickel, palladium, or another electrically conductive material. Also, a diameter (or other characteristic lateral extent) of the first electrically conductive post segment 132 is greater than that of the second electrically conductive post segment 134. This difference in diameter between the first electrically conductive post segment 132 and the second electrically conductive post segment 134 results in that each of the first electrically conductive posts 130 includes a larger top or head part. Advantageously, this difference in diameter and the patterned etching stop layer 180 enhance structural rigidity and reliability of the package carrier 100 a by, for example, serving as a locking mechanism for the first electrically conductive posts 130 with respect to the dielectric layer 110 and, thereby, increasing the degree of coupling for the first electrically conductive pattern 120 and the second electrically conductive pattern 140 with respect to one another and with respect to the dielectric layer 110. In addition, by forming the first electrically conductive posts 130 within the dielectric layer 110, the stress imparted by external forces, such as attributable to mechanical shock, is compensated for, and the reliability of the package 10 a is improved. The first electrically conductive posts 130 can include a metal (e.g., copper), a metal alloy, or other electrically conductive material.
  • [0017]
    The second electrically conductive pattern 140 is disposed adjacent to the second surface 114 of the dielectric layer 110, and includes a set of second pads 142 that are connected to respective ones of the second electrically conductive post segments 134. The first solder mask layer 150 is disposed adjacent to the first surface 112 of the dielectric layer 110, and defines apertures or openings to expose the first pads 122. The second solder mask layer 160 is disposed adjacent to the second surface 114 of the dielectric layer 110, and defines apertures or openings to expose the second pads 142.
  • [0018]
    The first solder balls 102 are respectively disposed adjacent to the second pads 142. The chip 104 is mounted adjacent to the package carrier 100 a, and is located adjacent to the first surface 112 of the dielectric layer 110. The bonding wires 106 are connected between the chip 104 and the first pads 122. The encapsulant 108 covers the chip 104, the bonding wires 106, and a part of the package carrier 100 a.
  • [0019]
    In the present embodiment, the package 10 a further includes an adhesion layer 109. The adhesion layer 109 is disposed between the chip 104 and the first solder mask layer 150 for adhering the chip 104 to the package carrier 100 a.
  • [0020]
    FIG. 1B is a cross-sectional view of a package 10 b according to another embodiment of the invention. Referring to FIG. 1A and FIG. 1B, the package 10 b of FIG. 1B is similar to the package 10 a of FIG. 1A, and at least one difference is that the adhesion layer 109 of the package 10 b of FIG. 1B is disposed between the chip 104 and the first electrically conductive pattern 120, which is exposed by the first solder mask layer 150 of a package carrier 100 b.
  • [0021]
    FIG. 1C is a cross-sectional view of a package 10 c according to another embodiment of the invention. Referring to FIG. 1A and FIG. 1C, the package 10 c of FIG. 1C is similar to the package 10 a of FIG. 1A, and at least one difference is that, in a package carrier 100 c of FIG. 1C, the diameter of the first electrically conductive post segment 132 a is smaller than the diameter of the second electrically conductive post segment 134 a.
  • [0022]
    FIG. 1D is a cross-sectional view of a package 10 d according to another embodiment of the invention. Referring to FIG. 1C and FIG. 1D, the package 10 d of FIG. 1D is similar to the package 10 c of FIG. 1C, and at least one difference is that the adhesion layer 109 of the package 10 d of FIG. 1D is disposed between the chip 104 and the first electrically conductive pattern 120, which is exposed by the first solder mask layer 150 of a package carrier 100 d.
  • [0023]
    FIG. 1E is a cross-sectional view of a package 10 e according to another embodiment of the invention. Referring to FIG. 1A and FIG. 1E, the package 10 e of FIG. 1E is similar to the package 10 a of FIG. 1A, and at least one difference is that a package carrier 100 e of the package 10 e of FIG. 1E further includes a chip pad support 170, which can include a metal (e.g., copper), a metal alloy, or other electrically conductive material. The chip pad support 170 extends through the dielectric layer 110, wherein the first electrically conductive pattern 120 includes a third pad 124 serving as a chip pad, and the chip 104 is mounted adjacent to the third pad 124. The chip pad support 170 includes a first support segment 172 connected to the third pad 124, and a second support segment 174 connected to the first support segment 172. The second electrically conductive pattern 140 includes a fourth pad 144 connected to the second support segment 174. The chip 104 can be connected to the third pad 124, such as by wire-bonding, and the third pad 124 and the chip pad support 170 can provide an electrically pathway between the chip 104 and the fourth pad 144.
  • [0024]
    In the present embodiment, a diameter of the first support segment 172 is greater than that of the second support segment 174. Moreover, the diameter of the first support segment 172 is greater than that of the first electrically conductive post segment 132, and the diameter of the second support segment 174 is greater than that of the second electrically conductive post segment 134. Moreover, the package 10 e of FIG. 1E further includes a set of second solder balls 103 (or other electrically conductive bumps) respectively disposed adjacent to the fourth pad 144.
  • [0025]
    FIG. 1F is a cross-sectional view of a package 10 f according to another embodiment of the invention. Referring to FIG. 1E and FIG. 1F, the package 10 f of FIG. 1F is similar to the package 10 e of FIG. 1E, and at least one difference is that the adhesion layer 109 of the package 10 f of FIG. 1F is disposed between the chip 104 and the first electrically conductive pattern 120, which is exposed by the first solder mask layer 150 of a package carrier 100 f. In the present embodiment, the adhesion layer 109 is directly connected to the third pad 124 of the first electrically conductive pattern 120.
  • [0026]
    FIG. 1G is a cross-sectional view of a package 10 g according to another embodiment of the invention. Referring to FIG. 1E and FIG. 1G, the package 10 g of FIG. 1G is similar to the package 10 e of FIG. 1E, and at least one difference is that, in a package carrier 100 g of FIG. 1G, the diameter of the first support segment 172 a is smaller than that of the second support segment 174 a.
  • [0027]
    FIG. 1H is a cross-sectional view of a package 10 h according to another embodiment of the invention. Referring to FIG. 1G and FIG. 1H, the package 10 h of FIG. 1H is similar to the package 10 g of FIG. 1G, and at least one difference is that the adhesion layer 109 of the package 10 h of FIG. 1H is disposed between the chip 104 and the first electrically conductive pattern 120, which is exposed by the first solder mask layer 150 of a package carrier 100 h. In the present embodiment, the adhesion layer 109 is directly connected to the third pad 124 of the first electrically conductive pattern 120.
  • [0028]
    In some embodiments, a surface finishing or passivation layer (not shown) can be disposed adjacent to an exposed surface of an electrically conductive pattern, which layer can include nickel/gold, nickel/cadmium/gold, nickel/silver, gold, tin, alloys thereof (e.g., a tin-lead alloy), silver, electroless nickel electroless palladium immersion gold (ENEPIG), or a combination thereof.
  • [0029]
    Although the chip 104 in the aforementioned embodiments is electrically connected to the first electrically conductive pattern 120 through a wire-bonding technique, the chip 104 can also be electrically connected to the first electrically conductive pattern 120 through a flip-chip bonding technique, such as by having an exposed surface of the first electrically conductive pattern 120 located below the chip 104. In particular, the chip 104 can be connected to the exposed surface of the first electrically conductive pattern 120 through conductive bumps, such as solder bumps, copper pillars, copper stud bumps, or golden stud bumps. Moreover, an underfill material can be disposed between the chip 104 and a package carrier for encapsulating or wrapping the conductive bumps.
  • [0030]
    Attention next turns to FIG. 2-1 to FIG. 2-10, which illustrate a process for fabricating a package carrier according to an embodiment of the invention. Referring to FIG. 2-1, a carrier 202, an initial electrically conductive layer 204, a first electrically conductive pattern 206, and a set of first electrically conductive post segments 208 a are provided, wherein the initial electrically conductive layer 204 is disposed adjacent to the carrier 202, the first electrically conductive pattern 206 is disposed adjacent to the initial electrically conductive layer 204 and includes a set of first pads 206 a, and the first electrically conductive post segments 208 a are respectively disposed adjacent to the first pads 206 a. As discussed above, a patterned etching stop layer (or other barrier layer) can be located between the first electrically conductive post segments 208 a and the first pads 206 a. In the present embodiment, a semi-additive process can be used to sequentially form the first electrically conductive pattern 206 and the first electrically conductive post segments 208 a adjacent to the initial electrically conductive layer 204.
  • [0031]
    In particular, a temporary mask of a dielectric material, a photoresist, or other suitable material is disposed adjacent to the initial electrically conductive layer 204, and then the mask is patterned to form openings at corresponding positions of the first electrically conductive pattern 206. The initial electrically conductive layer 204 is used as a plating layer, which provides a current pathway to form the first electrically conductive pattern 206 in the openings through electroplating. Then, the mask used for the electroplating is removed.
  • [0032]
    Then, a temporary mask of a dielectric material, a photoresist, or other suitable material is disposed adjacent to the first electrically conductive pattern 206 and the initial electrically conductive layer 204. Then, the mask is patterned to form openings at corresponding positions of the first electrically conductive post segments 208 a. The first electrically conductive pattern 206 and the initial electrically conductive layer 204 are used as plating layers, which provide a current pathway to form the first electrically conductive post segments 208 a in the openings through electroplating. Then, the mask used for the electroplating is removed.
  • [0033]
    Next, referring to FIG. 2-2, a dielectric layer 210 is provided, wherein the dielectric layer 210 is pre-formed with a set of first openings 210 a, and positions of the first openings 210 a respectively correspond to positions of the first electrically conductive post segments 208 a. In the present embodiment, the dielectric layer 210 can be a fiber-reinforced resin material, such as a prepreg material. While the openings 210 a are shown in FIG. 2-2 as fully extending through the dielectric layer 210, it is contemplated that the openings 210 a also can partially extend through the dielectric layer 210.
  • [0034]
    Then, referring to FIG. 2-3, the dielectric layer 210 is laminated to the initial electrically conductive layer 204, so that the first electrically conductive pattern 206 and the first electrically conductive post segments 208 a are embedded in the dielectric layer 210. In the case where the openings 210 a (shown in FIG. 2-2) fully extend through the dielectric layer 210, a thermal lamination process can be used, which can result in some dielectric material being displaced so as to cover top ends of the first electrically conductive post segments 208 a as shown in FIG. 2-3. It is also contemplated that the dielectric layer 210 can be formed in situ adjacent to the initial electrically conductive layer 204.
  • [0035]
    Then, referring to FIG. 2-4, an electrically conductive layer 211 (e.g., a metal film or foil) is laminated to the dielectric layer 210, so that the dielectric layer 210 is laminated between the electrically conductive layer 211 and the initial electrically conductive layer 204. In some embodiments, the dielectric layer 210 and the electrically conductive layer 211 can be simultaneously laminated to the initial electrically conductive layer 204 in a common process operation.
  • [0036]
    Next, referring to FIG. 2-5, a set of conformal openings 211 a are formed in the electrically conductive layer 211. The conformal openings 211 a respectively expose parts of the dielectric layer 210 at positions corresponding to the first electrically conductive post segments 208 a. In the present embodiment, a diameter of each of the conformal openings 211 a is smaller than a diameter of the corresponding first electrically conductive post segment 208 a.
  • [0037]
    Then, referring to FIG. 2-6, the parts of the dielectric layer 210 exposed by the conformal openings 211 a are removed to form a set of second openings 210 b in the dielectric layer 210, so that the first electrically conductive post segments 208 a are respectively exposed by the second openings 210 b. In the present embodiment, the electrically conductive layer 211 can be used as a conformal mask to selectively remove the parts of the dielectric layer 210 exposed by the conformal openings 211 a through plasma etching, so as to form the second openings 210 b. Alternatively, or in conjunction, the parts of the dielectric layer 210 exposed by the conformal openings 211 a can be removed by laser drilling or another material removal technique. In the present embodiment, a diameter of each of the second openings 210 b is smaller than the diameter of the corresponding first electrically conductive post segment 208 a.
  • [0038]
    Next, referring to FIG. 2-6 and FIG. 2-7, the electrically conductive layer 211 is removed to expose the dielectric layer 210.
  • [0039]
    Then, referring to FIG. 2-8, a second electrically conductive post segment 208 b is formed in each of the second openings 210 b, wherein each second electrically conductive post segment 208 b and the corresponding first electrically conductive post segment 208 a are connected together to form an electrically conductive post 208. In the present embodiment, the second electrically conductive post segments 208 b can be formed through electroplating. It should be noted that, since the diameter of the second opening 210 b is smaller than the diameter of the first electrically conductive post segment 208 a, the diameter of the second electrically conductive post segment 208 b is smaller than that of the first electrically conductive post segment 208 a.
  • [0040]
    Then, still referring to FIG. 2-8, a second electrically conductive pattern 212 is formed adjacent to the second electrically conductive post segments 208 b and the dielectric layer 210, wherein the second electrically conductive pattern 212 includes a set of second pads 212 a, and the second pads 212 a are respectively connected to the second electrically conductive post segments 208 b. In the present embodiment, a non-patterned electrically conductive layer (not shown) is first formed adjacent to the dielectric layer 210 and the second electrically conductive post segments 208 b through electroplating, and then the non-patterned electrically conductive layer is patterned to form the second electrically conductive pattern 212. During electroplating to form the non-patterned electrically conductive layer, the second electrically conductive post segments 208 b can also be formed in a common process operation.
  • [0041]
    Next, referring to FIG. 2-8 and FIG. 2-9, the carrier 202 and the initial electrically conductive layer 204 are removed. In the present embodiment, the carrier 202 and the initial electrically conductive layer 204 can have a release interface in between, so that the carrier 202 can be released from the initial electrically conductive layer 204. Moreover, the initial electrically conductive layer 204 can be removed by etching, and exposed surfaces (e.g., of the second electrically conductive pattern 212) can be protected from etching while the initial electrically conductive layer 204 is removed.
  • [0042]
    Next, referring to FIG. 2-10, a first solder mask layer 214 is formed adjacent to the first electrically conductive pattern 206, wherein the first solder mask layer 214 exposes the first pads 206 a. Moreover, a second solder mask layer 216 is formed adjacent to the second electrically conductive pattern 212, wherein the second solder mask layer 216 exposes the second pads 212 a. In some embodiments, a surface finishing or passivation layer (not shown) can be formed adjacent to either, or both, of the first pads 206 a and the second pads 212 a. The surface passivation layer can include, for example, nickel/gold, nickel/cadmium/gold, nickel/silver, gold, tin, alloys thereof (e.g., a tin-lead alloy), silver, electroless nickel electroless palladium immersion gold (ENEPIG), or a combination thereof.
  • [0043]
    Once a package carrier is fabricated in accordance with FIG. 2-1 through FIG. 2-10, a package according to an embodiment of the invention can be fabricated by disposing a chip (e.g., the chip 104 in FIG. 1A) adjacent to the package carrier, electrically connecting the chip to the first pads 206 a, and disposing solder balls (e.g., the first solder balls 102 of FIG. 1A) adjacent to respective ones of the second pads 212 a.
  • [0044]
    FIG. 3-1 to FIG. 3-10 illustrate a process for fabricating a package carrier according to another embodiment of the invention. Referring to FIG. 3-1, a carrier 302, an initial electrically conductive layer 304, a first electrically conductive pattern 306, and a set of first electrically conductive post segments 308 a are provided, wherein the initial electrically conductive layer 304 is disposed adjacent to the carrier 302, the first electrically conductive pattern 306 is disposed adjacent to the initial electrically conductive layer 304 and includes a set of first pads 306 a, and the first electrically conductive post segments 308 a are respectively disposed adjacent to the first pads 306 a. In the present embodiment, a semi-additive process can be used to sequentially form the first electrically conductive pattern 306 and the first electrically conductive post segments 308 a adjacent to the initial electrically conductive layer 304.
  • [0045]
    In particular, a temporary mask of a dielectric material, a photoresist, or other suitable material is disposed adjacent to the initial electrically conductive layer 304, and then the mask is patterned to form openings at corresponding positions of the first electrically conductive pattern 306. The initial electrically conductive layer 304 is used as a plating layer, which provides a current pathway to form the first electrically conductive pattern 306 in the openings through electroplating. Then, the mask used for the electroplating is removed.
  • [0046]
    Then, a temporary mask of a dielectric material, a photoresist, or other suitable material is disposed adjacent to the first electrically conductive pattern 306 and the initial electrically conductive layer 304. Then, the mask is patterned to form openings at corresponding positions of the first electrically conductive post segments 308 a. The first electrically conductive pattern 306 and the initial electrically conductive layer 304 are used as plating layers, which provide a current pathway to form the first electrically conductive post segments 308 a in the openings through electroplating. Then, the mask used for the electroplating is removed.
  • [0047]
    Next, referring to FIG. 3-2, a dielectric layer 310 is provided, wherein the dielectric layer 310 is pre-formed with a set of first openings 310 a, and positions of the first openings 310 a respectively correspond to positions of the first electrically conductive post segments 308 a. In the present embodiment, the dielectric layer 310 can be a fiber-reinforced resin material, such as a prepreg material. While the openings 310 a are shown in FIG. 3-2 as fully extending through the dielectric layer 310, it is contemplated that the openings 310 a also can partially extend through the dielectric layer 310.
  • [0048]
    Then, referring to FIG. 3-3, the dielectric layer 310 is laminated to the initial electrically conductive layer 304, so that the first electrically conductive pattern 306 and the first electrically conductive post segments 308 a are embedded in the dielectric layer 310. In the case where the openings 310 a (shown in FIG. 3-2) fully extend through the dielectric layer 310, a thermal lamination process can be used, which can result in some dielectric material being displaced so as to cover top ends of the first electrically conductive post segments 308 a as shown in FIG. 3-3. It is also contemplated that the dielectric layer 310 can be formed in situ adjacent to the initial electrically conductive layer 304.
  • [0049]
    Then, referring to FIG. 3-4, an electrically conductive layer 311 (e.g., a metal film or foil) is laminated to the dielectric layer 310, so that the dielectric layer 310 is laminated between the electrically conductive layer 311 and the initial electrically conductive layer 304. In some embodiments, the dielectric layer 310 and the electrically conductive layer 311 can be simultaneously laminated to the initial electrically conductive layer 304 in a common process operation.
  • [0050]
    Next, referring to FIG. 3-5, a set of conformal openings 311 a are formed in the electrically conductive layer 311. The conformal openings 311 a respectively expose parts of the dielectric layer 310 at positions corresponding to the first electrically conductive post segments 308 a. In the present embodiment, a diameter of each of the conformal openings 311 a is greater than a diameter of the corresponding first electrically conductive post segment 308 a.
  • [0051]
    Then, referring to FIG. 3-6, the parts of the dielectric layer 310 exposed by the conformal openings 311 a are removed to form a set of second openings 310 b in the dielectric layer 310, so that the first electrically conductive post segments 308 a are respectively exposed by the second openings 310 b. In the present embodiment, the electrically conductive layer 311 can be used as a conformal mask to selectively remove the parts of the dielectric layer 310 exposed by the conformal openings 311 a through plasma etching, so as to form the second openings 310 b. Alternatively, or in conjunction, the parts of the dielectric layer 310 exposed by the conformal openings 311 a can be removed by laser drilling or another material removal technique. In the present embodiment, a diameter of each of the second openings 310 b is greater than the diameter of the corresponding first electrically conductive post segment 308 a.
  • [0052]
    Next, referring to FIG. 3-6 and FIG. 3-7, the electrically conductive layer 311 is removed to expose the dielectric layer 310.
  • [0053]
    Then, referring to FIG. 3-8, a second electrically conductive post segment 308 b is formed in each of the second openings 310 b, wherein each second electrically conductive post segment 308 b and the corresponding first electrically conductive post segment 308 a are connected together to form an electrically conductive post 308. In the present embodiment, the second electrically conductive post segments 308 b can be formed through electroplating. It should be noted that, since the diameter of the second opening 310 b is greater than the diameter of the first electrically conductive post segment 308 a, the diameter of the second electrically conductive post segment 308 b is greater than that of the first electrically conductive post segment 308 a.
  • [0054]
    Then, still referring to FIG. 3-8, a second electrically conductive pattern 312 is formed adjacent to the second electrically conductive post segments 308 b and the dielectric layer 310, wherein the second electrically conductive pattern 312 includes a set of second pads 312 a, and the second pads 312 a are respectively connected to the second electrically conductive post segments 308 b. In the present embodiment, a non-patterned electrically conductive layer (not shown) is first formed adjacent to the dielectric layer 310 and the second electrically conductive post segments 308 b through electroplating, and then the non-patterned electrically conductive layer is patterned to form the second electrically conductive pattern 312. During electroplating to form the non-patterned electrically conductive layer, the second electrically conductive post segments 308 b can also be formed in a common process operation.
  • [0055]
    Next, referring to FIG. 3-8 and FIG. 3-9, the carrier 302 and the initial electrically conductive layer 304 are removed. In the present embodiment, the carrier 302 and the initial electrically conductive layer 304 can have a release interface in between, so that the carrier 302 can be released from the initial electrically conductive layer 304. Moreover, the initial electrically conductive layer 304 can be removed by etching, and exposed surfaces (e.g., of the second electrically conductive pattern 312) can be protected from etching while the initial electrically conductive layer 304 is removed.
  • [0056]
    Next, referring to FIG. 3-10, a first solder mask layer 314 is formed adjacent to the first electrically conductive pattern 306, wherein the first solder mask layer 314 exposes the first pads 306 a. Moreover, a second solder mask layer 316 is formed adjacent to the second electrically conductive pattern 312, wherein the second solder mask layer 316 exposes the second pads 312 a. In some embodiments, a surface finishing or passivation layer (not shown) can be formed adjacent to either, or both, of the first pads 306 a and the second pads 312 a. The surface passivation layer can include, for example, nickel/gold, nickel/cadmium/gold, nickel/silver, gold, tin, alloys thereof (e.g., a tin-lead alloy), silver, electroless nickel electroless palladium immersion gold (ENEPIG), or a combination thereof.
  • [0057]
    Once a package carrier is fabricated in accordance with FIG. 3-1 through FIG. 3-10, a package according to an embodiment of the invention can be fabricated by disposing a chip (e.g., the chip 104 in FIG. 1C) adjacent to the package carrier, electrically connecting the chip to the first pads 306 a, and disposing solder balls (e.g., the first solder balls 102 of FIG. 1C) adjacent to respective ones of the second pads 312 a.
  • [0058]
    It should be recognized that similar operations as discussed for FIG. 2-1 through FIG. 2-10 and FIG. 3-1 through FIG. 3-10 can be used to fabricate a package carrier and a package including a chip pad and a chip support pad that is connected to the chip pad (e.g., as illustrated in FIG. 1E through FIG. 1H).
  • [0059]
    In summary, in a package carrier of some embodiments of the invention, electrically conductive posts can be used so as to effectively reduce a package size and a package area, while controlling the cost and complexity of packaging processes.
  • [0060]
    While the invention has been described with reference to the specific embodiments thereof, it should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention. In addition, modifications may be made to adapt a particular situation, material, composition of matter, method, or process, within the scope of the claims, including variances or tolerances attributable to manufacturing processes and techniques. In particular, while the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method and resultant structure consistent with the teachings of the invention.

Claims (20)

1. A package carrier, comprising:
a dielectric layer having a plurality of openings;
a first conductive pattern, disposed adjacent to a first surface of the dielectric layer, the first conductive pattern including a plurality of first pads; and
a plurality of conductive vias disposed in respective ones of the openings, wherein each conductive via includes a first via segment, connected to at least one of the first pads, and a second via segment, connected to the first via segment, such that a lateral extent of the first via segment is different from a lateral extent of the second via segment.
2. The package carrier as claimed in claim 1, wherein the first conductive pattern is embedded in the dielectric layer.
3. The package carrier as claimed in claim 1, wherein the lateral extent of the first via segment is greater than the lateral extent of the second via segment.
4. The package carrier as claimed in claim 1, wherein the conductive vias provide a locking mechanism with respect to the dielectric layer.
5. The package carrier as claimed in claim 1, further comprising:
a second conductive pattern, disposed adjacent to a second surface of the dielectric layer and including a plurality of second pads, wherein the second via segment of each conductive via is connected to at least one of the second pads.
6. The package carrier as claimed in claim 5, further comprising:
a chip pad support, extending through the dielectric layer,
wherein the first conductive pattern includes a third pad corresponding to a chip pad, and the chip pad support includes a first support segment, connected to the chip pad, and a second support segment, connected to the first support segment.
7. The package carrier as claimed in claim 6, wherein the second conductive pattern includes a fourth pad connected to the second support segment, a lateral extent of the first support segment is greater than the lateral extent of the first via segment, and a lateral extent of the second support segment is greater than the lateral extent of the second via segment.
8. The package carrier as claimed in claim 7, wherein the lateral extent of the first support segment is greater than the lateral extent of the second support segment.
9. The package carrier as claimed in claim 1, further comprising:
a chip pad support, extending through the dielectric layer,
wherein the first conductive pattern includes a chip pad, and the chip pad support includes a first support segment, connected to the chip pad, and a second support segment, connected to the first support segment.
10. A semiconductor package, comprising:
a package carrier, including:
a dielectric layer;
a top conductive pattern, disposed adjacent to a top surface of the dielectric layer, and including a plurality of first pads;
a bottom conductive pattern, disposed adjacent to a bottom surface of the dielectric layer, and including a plurality of second pads; and
a plurality of conductive vias within the dielectric layer and extending between the top conductive pattern and the bottom conductive pattern, wherein each conductive via includes a first segment, connected to at least one of the first pads, and a second segment, connected to at least one of the second pads; and
a chip, attached to the package carrier and connected to the first pads.
11. The semiconductor package as claimed in claim 10, wherein the top conductive pattern is embedded in the dielectric layer.
12. The semiconductor package as claimed in claim 10, wherein a lateral extent of the first segment is greater than a lateral extent of the second segment.
13. The semiconductor package as claimed in claim 10, wherein the conductive vias provide a locking mechanism with respect to the dielectric layer.
14. The semiconductor package as claimed in claim 10, wherein a top surface of the top conductive pattern is aligned with the top surface of the dielectric layer.
15. The semiconductor package as claimed in claim 10, wherein the package carrier further includes:
a chip pad support, extending through the dielectric layer,
wherein the top conductive pattern includes a third pad corresponding to a chip pad, the chip is disposed adjacent to the chip pad, the chip pad support includes a third segment, connected to the chip pad, and a fourth segment, connected to the third segment, the bottom conductive pattern includes a fourth pad connected to the fourth segment, a lateral extent of the third segment is greater than a lateral extent of the first segment, and a lateral extent of the fourth segment is greater than a lateral extent of the second segment.
16. The semiconductor package as claimed in claim 15, further comprising:
at least one conductive bump, disposed adjacent to the fourth pad.
17. The semiconductor package as claimed in claim 10, wherein the package carrier further includes:
an etching stop layer, disposed between the conductive vias and the top conductive pattern.
18. The semiconductor package as claimed in claim 10, wherein the conductive vias correspond to conductive posts.
19. A semiconductor fabrication process, comprising:
forming a first conductive pattern including a plurality of first pads;
forming a plurality of first via segments on at least some of the first pads;
providing a dielectric layer having a plurality of first openings corresponding to the first via segments;
applying the dielectric layer to the first conductive pattern and the first via segments;
forming a plurality of second openings in the dielectric layer, such that the first via segments are exposed by the second openings; and
forming a plurality of second via segments on the first via segments and at least partially within the second openings, such that a diameter of the first via segment is different than a diameter of the second via segment.
20. The process as claimed in claim 19, further comprising:
forming a second conductive pattern including a plurality of second pads, wherein the second via segments are connected to at least some of the second pads.
US12904876 2009-10-14 2010-10-14 Package carrier, semiconductor package, and process for fabricating same Abandoned US20110084372A1 (en)

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US25139609 true 2009-10-14 2009-10-14
US29451910 true 2010-01-13 2010-01-13
TW99112317 2010-04-20
TW99112317 2010-04-20
US12904876 US20110084372A1 (en) 2009-10-14 2010-10-14 Package carrier, semiconductor package, and process for fabricating same

Applications Claiming Priority (2)

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US12904876 US20110084372A1 (en) 2009-10-14 2010-10-14 Package carrier, semiconductor package, and process for fabricating same
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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100288541A1 (en) * 2009-05-13 2010-11-18 Advanced Semiconductor Engineering, Inc. Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package
US20100289132A1 (en) * 2009-05-13 2010-11-18 Shih-Fu Huang Substrate having embedded single patterned metal layer, and package applied with the same, and methods of manufacturing of the substrate and package
US20100314744A1 (en) * 2009-05-13 2010-12-16 Shih-Fu Huang Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof
US20100320610A1 (en) * 2009-05-13 2010-12-23 Shih-Fu Huang Semiconductor package with substrate having single metal layer and manufacturing methods thereof
US20110057301A1 (en) * 2009-09-08 2011-03-10 Advanced Semiconductor Engineering, Inc. Semiconductor package
US20110084370A1 (en) * 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Semiconductor package and process for fabricating same
US20110169150A1 (en) * 2010-01-13 2011-07-14 Advanced Semiconductor Engineering, Inc. Semiconductor Package with Single Sided Substrate Design and Manufacturing Methods Thereof
CN102751203A (en) * 2011-04-22 2012-10-24 日月光半导体制造股份有限公司 Semiconductor encapsulation structure and manufacture method of semiconductor encapsulation structure
CN103426855A (en) * 2012-05-18 2013-12-04 矽品精密工业股份有限公司 Semiconductor package and fabrication method thereof
US9349611B2 (en) 2010-03-22 2016-05-24 Advanced Semiconductor Engineering, Inc. Stackable semiconductor package and manufacturing method thereof
US9355983B1 (en) 2014-06-27 2016-05-31 Stats Chippac Ltd. Integrated circuit packaging system with interposer structure and method of manufacture thereof
US9564346B2 (en) 2009-10-14 2017-02-07 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same

Citations (97)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2002003A (en) * 1930-09-20 1935-05-21 Ig Farbenindustrie Ag Production of acetylene and carbon black
US3959674A (en) * 1973-09-28 1976-05-25 Nicolas Kokinopoulos Pulse counters having a magnetic pole wheel
US5019535A (en) * 1989-03-28 1991-05-28 General Electric Company Die attachment method using nonconductive adhesive for use in high density interconnected assemblies
US5091769A (en) * 1991-03-27 1992-02-25 Eichelberger Charles W Configuration for testing and burn-in of integrated circuit chips
US5111278A (en) * 1991-03-27 1992-05-05 Eichelberger Charles W Three-dimensional multichip module systems
US5315486A (en) * 1991-12-16 1994-05-24 General Electric Company Hermetically packaged HDI electronic system
US5519936A (en) * 1994-01-28 1996-05-28 International Business Machines Corporation Method of making an electronic package with a thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto
US5710062A (en) * 1993-06-01 1998-01-20 Mitsubishi Denki Kabushiki Kaisha Plastic molded semiconductor package and method of manufacturing the same
US5745984A (en) * 1995-07-10 1998-05-05 Martin Marietta Corporation Method for making an electronic module
US5866952A (en) * 1995-11-30 1999-02-02 Lockheed Martin Corporation High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate
US5874784A (en) * 1995-10-25 1999-02-23 Sharp Kabushiki Kaisha Semiconductor device having external connection terminals provided on an interconnection plate and fabrication process therefor
US6177636B1 (en) * 1994-12-29 2001-01-23 Tessera, Inc. Connection components with posts
US6198165B1 (en) * 1998-05-29 2001-03-06 Sharp Kabushiki Kaisha Semiconductor device
US6232650B1 (en) * 1997-07-30 2001-05-15 Hitachi, Ltd. Semiconductor device having a chip mounted on a flexible substrate with separated insulation layers to prevent short-circuiting
US6232151B1 (en) * 1999-11-01 2001-05-15 General Electric Company Power electronic module packaging
US6239482B1 (en) * 1999-06-21 2001-05-29 General Electric Company Integrated circuit package including window frame
US20020056192A1 (en) * 2000-09-27 2002-05-16 Tokihito Suwa Method of producing multilayer printed wiring board and multilayer printed wiring board
US6396148B1 (en) * 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
US20030030137A1 (en) * 1998-09-09 2003-02-13 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
US20030034553A1 (en) * 2001-08-15 2003-02-20 Kazuaki Ano Low profile ball-grid array package for high power
US6556908B1 (en) * 2002-03-04 2003-04-29 Ford Global Technologies, Inc. Attitude sensing system for an automotive vehicle relative to the road
US20030090883A1 (en) * 2001-10-18 2003-05-15 Matsushita Electric Industrial Co., Ltd. Component built-in module and method for producing the same
US20030098502A1 (en) * 2001-05-17 2003-05-29 Sharp Kabushiki Kaisha Semiconductor package substrate, semiconductor package
US6663946B2 (en) * 2001-02-28 2003-12-16 Kyocera Corporation Multi-layer wiring substrate
US6680529B2 (en) * 2002-02-15 2004-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor build-up package
US20040012099A1 (en) * 2002-02-26 2004-01-22 Toshinori Nakayama Semiconductor device and manufacturing method for the same, circuit board, and electronic device
US6701614B2 (en) * 2002-02-15 2004-03-09 Advanced Semiconductor Engineering Inc. Method for making a build-up package of a semiconductor
US20040080054A1 (en) * 2000-12-19 2004-04-29 Hitachi Cable, Ltd. Wiring board, semiconductor device, and process for production of wiring board
US20040201101A1 (en) * 2003-04-10 2004-10-14 Kang Seung H. Aluminum pad power bus and signal routing for integrated circuit devices utilizing copper technology interconnect structures
US6838776B2 (en) * 2003-04-18 2005-01-04 Freescale Semiconductor, Inc. Circuit device with at least partial packaging and method for forming
US20050006752A1 (en) * 2002-07-03 2005-01-13 Tsuyoshi Ogawa Multi-layer interconnection circuit module and manufacturing method thereof
US6845554B2 (en) * 2001-11-22 2005-01-25 Infineon Technologies Ag Method for connection of circuit units
US6861757B2 (en) * 2001-09-03 2005-03-01 Nec Corporation Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device
US6977348B2 (en) * 2002-05-28 2005-12-20 Via Technologies, Inc. High density laminated substrate structure and manufacture method thereof
US7015075B2 (en) * 2004-02-09 2006-03-21 Freescale Semiconuctor, Inc. Die encapsulation using a porous carrier
US20060065387A1 (en) * 2004-09-28 2006-03-30 General Electric Company Electronic assemblies and methods of making the same
US20060071315A1 (en) * 2001-03-09 2006-04-06 Oh Kwang S Method of forming a stacked semiconductor package
US7045908B2 (en) * 2003-04-14 2006-05-16 Oki Electric Industry Co., Ltd. Semiconductor device and method for manufacturing the same
US7048450B2 (en) * 2003-07-14 2006-05-23 Infineon Technologies, Ag Optoelectronic module with transmitter chip and connecting piece for the module with respect to an optical fiber and with respect to a circuit board, and methods for producing the same
US7163843B2 (en) * 2003-07-24 2007-01-16 Infineon Technologies Ag Semiconductor component of semiconductor chip size with flip-chip-like external contacts, and method of producing the same
US7173330B2 (en) * 2002-08-27 2007-02-06 Micron Technology, Inc. Multiple chip semiconductor package
US20070052076A1 (en) * 2002-04-29 2007-03-08 Ramos Mary J Partially Patterned Lead Frames and Methods of Making and Using the Same in Semiconductor Packaging
US20070057364A1 (en) * 2005-09-01 2007-03-15 Wang Carl B Low temperature co-fired ceramic (LTCC) tape compositions, light emitting diode (LED) modules, lighting devices and method of forming thereof
US20070096311A1 (en) * 2003-09-26 2007-05-03 Tessera, Inc. Structure and method of making capped chips having vertical interconnects
US20070234563A1 (en) * 2006-04-11 2007-10-11 Shinko Electric Industries Co., Ltd. Method of forming solder connection portions, method of forming wiring substrate and method of producing semiconductor device
US7319049B2 (en) * 2004-05-10 2008-01-15 Shinko Electric Industries Co., Ltd. Method of manufacturing an electronic parts packaging structure
US7344917B2 (en) * 2005-11-30 2008-03-18 Freescale Semiconductor, Inc. Method for packaging a semiconductor device
US20080081161A1 (en) * 2006-09-28 2008-04-03 Matsushita Electric Industrial Co., Ltd. Wiring board and semiconductor device
US20080089048A1 (en) * 2006-10-11 2008-04-17 Shinko Electric Industries Co., Ltd. Substrate with built-in electronic component and method for manufacturing the same
US7361533B1 (en) * 2002-11-08 2008-04-22 Amkor Technology, Inc. Stacked embedded leadframe
US7361987B2 (en) * 2003-04-18 2008-04-22 Freescale Semiconductor, Inc. Circuit device with at least partial packaging and method for forming
US7364944B2 (en) * 2003-05-28 2008-04-29 Siliconware Precision Industries Co., Ltd. Method for fabricating thermally enhanced semiconductor package
US7371617B2 (en) * 2004-10-27 2008-05-13 Siliconware Precision Industries Co., Ltd. Method for fabricating semiconductor package with heat sink
US7476563B2 (en) * 2006-11-17 2009-01-13 Freescale Semiconductor, Inc. Method of packaging a device using a dielectric layer
US7482198B2 (en) * 2004-04-26 2009-01-27 Infineon Technologies Ag Method for producing through-contacts and a semiconductor component with through-contacts
US20090045512A1 (en) * 2007-08-15 2009-02-19 Harry Hedler Carrier substrate and integrated circuit
US20090047797A1 (en) * 2002-03-22 2009-02-19 Anderson Curtis W Method for producing shock and tamper resistant microelectronic devices
US7501310B2 (en) * 2004-04-28 2009-03-10 Advanced Chip Engineering Technology Inc. Structure of image sensor module and method for manufacturing of wafer level package
US20090075428A1 (en) * 2007-09-13 2009-03-19 Freescale Semiconductor, Inc. Electromagnetic shield formation for integrated circuit die package
US7511365B2 (en) * 2005-04-21 2009-03-31 Industrial Technology Research Institute Thermal enhanced low profile package structure
US7514767B2 (en) * 2003-12-03 2009-04-07 Advanced Chip Engineering Technology Inc. Fan out type wafer level package structure and method of the same
US20090102066A1 (en) * 2007-10-22 2009-04-23 Advanced Semiconductor Engineering, Inc. Chip package structure and method of manufacturing the same
US20090101400A1 (en) * 2007-06-19 2009-04-23 Murata Manufacturing Co., Ltd. Method for manufacturing component-embedded substrate and component-embedded substrate
US20090115072A1 (en) * 2007-11-01 2009-05-07 Texas Instruments Incorporated BGA Package with Traces for Plating Pads Under the Chip
US20090129037A1 (en) * 2006-01-13 2009-05-21 Yutaka Yoshino Printed wiring board with built-in semiconductor element, and process for producing the same
US20090127686A1 (en) * 2007-11-21 2009-05-21 Advanced Chip Engineering Technology Inc. Stacking die package structure for semiconductor devices and method of the same
US20090224391A1 (en) * 2008-03-04 2009-09-10 Stats Chippac, Ltd. Wafer Level Die Integration and Method Therefor
US20100006994A1 (en) * 2008-07-14 2010-01-14 Stats Chippac, Ltd. Embedded Semiconductor Die Package and Method of Making the Same Using Metal Frame Carrier
US20100006330A1 (en) * 2008-07-11 2010-01-14 Advanced Semiconductor Engineering, Inc. Structure and process of embedded chip package
US7656501B2 (en) * 2005-11-16 2010-02-02 Asml Netherlands B.V. Lithographic apparatus
US7662667B2 (en) * 2007-12-20 2010-02-16 Chipmos Technologies Inc Die rearrangement package structure using layout process to form a compliant configuration
US7667318B2 (en) * 2003-12-03 2010-02-23 Advanced Chip Engineering Technology Inc. Fan out type wafer level package structure and method of the same
US7675157B2 (en) * 2006-01-30 2010-03-09 Marvell World Trade Ltd. Thermal enhanced package
US7682972B2 (en) * 2006-06-01 2010-03-23 Amitec-Advanced Multilayer Interconnect Technoloiges Ltd. Advanced multilayer coreless support structures and method for their fabrication
US20100072599A1 (en) * 2008-09-22 2010-03-25 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a Wafer Level Package with Top and Bottom Solder Bump Interconnection
US20100072618A1 (en) * 2008-09-22 2010-03-25 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a Wafer Level Package with Bump Interconnection
US7692286B1 (en) * 2002-11-08 2010-04-06 Amkor Technology, Inc. Two-sided fan-out wafer escape package
US20100096739A1 (en) * 2005-10-27 2010-04-22 Panasonic Corporation Stacked semiconductor module
US20100109132A1 (en) * 2008-10-31 2010-05-06 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US20110018124A1 (en) * 2009-07-23 2011-01-27 Advanced Semiconductor Engineering, Inc. Semiconductor Device Packages, Redistribution Structures, and Manufacturing Methods Thereof
US20110018118A1 (en) * 2009-07-21 2011-01-27 Advanced Semiconductor Engineering, Inc. Semiconductor Device Packages, Redistribution Structures, and Manufacturing Methods Thereof
US20110037169A1 (en) * 2009-08-12 2011-02-17 Stats Chippac, Ltd. Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structures
US20110057301A1 (en) * 2009-09-08 2011-03-10 Advanced Semiconductor Engineering, Inc. Semiconductor package
US20110068453A1 (en) * 2009-09-21 2011-03-24 Cho Namju Integrated circuit packaging system with encapsulated via and method of manufacture thereof
US20110068459A1 (en) * 2009-09-23 2011-03-24 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Interposer with Opening to Contain Semiconductor Die
US20110074008A1 (en) * 2009-09-25 2011-03-31 Tung-Hsien Hsieh Semiconductor flip chip package
US20110084370A1 (en) * 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Semiconductor package and process for fabricating same
US20110115060A1 (en) * 2009-11-19 2011-05-19 Advanced Semiconductor Engineering, Inc. Wafer-Level Semiconductor Device Packages with Electromagnetic Interference Shielding
US20110115082A1 (en) * 2009-11-16 2011-05-19 International Business Machines Corporation Configurable interposer
US8110916B2 (en) * 2009-06-19 2012-02-07 Advanced Semiconductor Engineering, Inc. Chip package structure and manufacturing methods thereof
US20120038053A1 (en) * 2010-08-16 2012-02-16 Stats Chippac, Ltd. Semiconductor Device and Method of Forming FO-WLCSP Having Conductive Layers and Conductive Vias Separated by Polymer Layers
US20120056321A1 (en) * 2010-09-07 2012-03-08 Stats Chippac, Ltd. Semiconductor Device and Method of Forming WLP With Semiconductor Die Embedded Within Penetrable Encapsulant Between TSV Interposers
US20120077311A1 (en) * 2007-08-10 2012-03-29 Pyoung-Wan Kim Semiconductor package having buried post in encapsulant and method of manufacturing the same
US8367473B2 (en) * 2009-05-13 2013-02-05 Advanced Semiconductor Engineering, Inc. Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof
US8372689B2 (en) * 2010-01-21 2013-02-12 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof
US8399776B2 (en) * 2009-05-13 2013-03-19 Advanced Semiconductor Engineering, Inc. Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package
US8405213B2 (en) * 2010-03-22 2013-03-26 Advanced Semiconductor Engineering, Inc. Semiconductor package including a stacking element

Family Cites Families (124)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3959874A (en) 1974-12-20 1976-06-01 Western Electric Company, Inc. Method of forming an integrated circuit assembly
US4783695A (en) 1986-09-26 1988-11-08 General Electric Company Multichip integrated circuit packaging configuration and method
US5225023A (en) 1989-02-21 1993-07-06 General Electric Company High density interconnect thermoplastic die attach material and solvent die attach processing
US5151776A (en) 1989-03-28 1992-09-29 General Electric Company Die attachment method for use in high density interconnected assemblies
US5241456A (en) 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
US5157589A (en) 1990-07-02 1992-10-20 General Electric Company Mutliple lamination high density interconnect process and structure employing thermoplastic adhesives having sequentially decreasing TG 's
US5120678A (en) 1990-11-05 1992-06-09 Motorola Inc. Electrical component package comprising polymer-reinforced solder bump interconnection
US5250843A (en) 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US5149662A (en) 1991-03-27 1992-09-22 Integrated System Assemblies Corporation Methods for testing and burn-in of integrated circuit chips
US5592025A (en) 1992-08-06 1997-01-07 Motorola, Inc. Pad array semiconductor device
US5324687A (en) 1992-10-16 1994-06-28 General Electric Company Method for thinning of integrated circuit chips for lightweight packaged electronic systems
US5422513A (en) 1992-10-16 1995-06-06 Martin Marietta Corporation Integrated circuit chip placement in a high density interconnect structure
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5353195A (en) 1993-07-09 1994-10-04 General Electric Company Integral power and ground structure for multi-chip modules
KR970002140B1 (en) 1993-12-27 1997-02-24 Lg Semicon Co Ltd Semiconductor device, packaging method and lead tape
US5976912A (en) 1994-03-18 1999-11-02 Hitachi Chemical Company, Ltd. Fabrication process of semiconductor package and semiconductor package
US5688716A (en) 1994-07-07 1997-11-18 Tessera, Inc. Fan-out semiconductor chip assembly
US5546654A (en) 1994-08-29 1996-08-20 General Electric Company Vacuum fixture and method for fabricating electronic assemblies
US5527741A (en) 1994-10-11 1996-06-18 Martin Marietta Corporation Fabrication and structures of circuit modules with flexible interconnect layers
US6826827B1 (en) 1994-12-29 2004-12-07 Tessera, Inc. Forming conductive posts by selective removal of conductive material
US5583376A (en) 1995-01-03 1996-12-10 Motorola, Inc. High performance semiconductor device with resin substrate and method for making the same
US5567657A (en) 1995-12-04 1996-10-22 General Electric Company Fabrication and structures of two-sided molded circuit modules with flexible interconnect layers
JP3080579B2 (en) 1996-03-06 2000-08-28 富士機工電子株式会社 Method for producing Earia grid array package
US5841193A (en) 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
JP2755252B2 (en) 1996-05-30 1998-05-20 日本電気株式会社 Semiconductor device package and a semiconductor device
JP3679199B2 (en) 1996-07-30 2005-08-03 日本テキサス・インスツルメンツ株式会社 Semiconductor packaging device
JPH1174651A (en) 1997-03-13 1999-03-16 Ibiden Co Ltd Printed wiring board and its manufacture
JPH10270592A (en) 1997-03-24 1998-10-09 Texas Instr Japan Ltd Semiconductor device and manufacture thereof
US6300686B1 (en) 1997-10-02 2001-10-09 Matsushita Electric Industrial Co., Ltd. Semiconductor chip bonded to a thermal conductive sheet having a filled through hole for electrical connection
JPH11307689A (en) 1998-02-17 1999-11-05 Seiko Epson Corp Semiconductor device, semiconductor device board, manufacture of them, and electronic equipment
US6080932A (en) 1998-04-14 2000-06-27 Tessera, Inc. Semiconductor package assemblies with moisture vents
JP3844032B2 (en) 1998-07-14 2006-11-08 日本テキサス・インスツルメンツ株式会社 Semiconductor device and manufacturing method thereof
US6472749B1 (en) 1999-02-15 2002-10-29 Hitachi, Ltd. Semiconductor device having a shortened wiring length to reduce the size of a chip
US6306680B1 (en) 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
US6889433B1 (en) * 1999-07-12 2005-05-10 Ibiden Co., Ltd. Method of manufacturing printed-circuit board
US6428942B1 (en) 1999-10-28 2002-08-06 Fujitsu Limited Multilayer circuit structure build up method
US6580159B1 (en) 1999-11-05 2003-06-17 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
US6331451B1 (en) 1999-11-05 2001-12-18 Amkor Technology, Inc. Methods of making thin integrated circuit device packages with improved thermal performance and substrates for making the packages
US6271057B1 (en) 1999-11-19 2001-08-07 Advanced Semiconductor Engineering, Inc. Method of making semiconductor chip package
US6242815B1 (en) 1999-12-07 2001-06-05 Advanced Semiconductor Engineering, Inc. Flexible substrate based ball grid array (BGA) package
US6630630B1 (en) 1999-12-14 2003-10-07 Matsushita Electric Industrial Co., Ltd. Multilayer printed wiring board and its manufacturing method
JP2001217354A (en) 2000-02-07 2001-08-10 Rohm Co Ltd Mounting structure for semiconductor chip, and semiconductor device
US6426545B1 (en) 2000-02-10 2002-07-30 Epic Technologies, Inc. Integrated circuit structures and methods employing a low modulus high elongation photodielectric
US6555908B1 (en) 2000-02-10 2003-04-29 Epic Technologies, Inc. Compliant, solderable input/output bump structures
US6586822B1 (en) 2000-09-08 2003-07-01 Intel Corporation Integrated core microelectronic package
JP3651413B2 (en) 2001-05-21 2005-05-25 日立電線株式会社 The semiconductor device using the tape carrier and it semiconductor device, a manufacturing method of a method of manufacturing a semiconductor device and a tape carrier semiconductor device
US6504111B2 (en) * 2001-05-29 2003-01-07 International Business Machines Corporation Solid via layer to layer interconnect
JP2003023250A (en) 2001-07-06 2003-01-24 Denso Corp Multilayered substrate and its manufacturing method
US7087991B2 (en) 2002-01-16 2006-08-08 Via Technologies, Inc. Integrated circuit package and method of manufacture
US6552430B1 (en) 2002-01-30 2003-04-22 Texas Instruments Incorporated Ball grid array substrate with improved traces formed from copper based metal
JP3888439B2 (en) 2002-02-25 2007-03-07 セイコーエプソン株式会社 A method of manufacturing a semiconductor device
US6593185B1 (en) 2002-05-17 2003-07-15 United Microelectronics Corp. Method of forming embedded capacitor structure applied to logic integrated circuit
US7138711B2 (en) 2002-06-17 2006-11-21 Micron Technology, Inc. Intrinsic thermal enhancement for FBGA package
DE10239866B3 (en) 2002-08-29 2004-04-08 Infineon Technologies Ag Production of a semiconductor component used in circuit boards comprises forming electrical contact surfaces together within a smaller contacting region as the whole surface of the front side of the chip and further processing
US7423340B2 (en) 2003-01-21 2008-09-09 Siliconware Precision Industries Co., Ltd. Semiconductor package free of substrate and fabrication method thereof
US7187060B2 (en) 2003-03-13 2007-03-06 Sanyo Electric Co., Ltd. Semiconductor device with shield
US6946325B2 (en) 2003-03-14 2005-09-20 Micron Technology, Inc. Methods for packaging microelectronic devices
JP4016340B2 (en) 2003-06-13 2007-12-05 ソニー株式会社 The semiconductor device and its mounting structure, and manufacturing method thereof
US7919787B2 (en) 2003-06-27 2011-04-05 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Semiconductor device with a light emitting semiconductor die
US7141884B2 (en) 2003-07-03 2006-11-28 Matsushita Electric Industrial Co., Ltd. Module with a built-in semiconductor and method for producing the same
DE10334576B4 (en) 2003-07-28 2007-04-05 Infineon Technologies Ag A method of manufacturing a semiconductor device with a plastic housing
DE10334578A1 (en) 2003-07-28 2005-03-10 Infineon Technologies Ag Smart card, the smart card module and to methods for producing a chip card module
JP3904541B2 (en) 2003-09-26 2007-04-11 沖電気工業株式会社 The method of manufacturing a semiconductor device embedded substrate
DE10352946B4 (en) 2003-11-11 2007-04-05 Infineon Technologies Ag of the same semiconductor device having semiconductor chip and the wiring layer and processes for preparing
JP2005277356A (en) 2004-03-26 2005-10-06 Sanyo Electric Co Ltd Circuit device
US7170162B2 (en) 2004-05-11 2007-01-30 Via Technologies, Inc. Chip embedded package structure
US7294791B2 (en) 2004-09-29 2007-11-13 Endicott Interconnect Technologies, Inc. Circuitized substrate with improved impedance control circuitry, method of making same, electrical assembly and information handling system utilizing same
US7371676B2 (en) 2005-04-08 2008-05-13 Micron Technology, Inc. Method for fabricating semiconductor components with through wire interconnects
US7335588B2 (en) 2005-04-15 2008-02-26 International Business Machines Corporation Interconnect structure and method of fabrication of same
US20060231944A1 (en) 2005-04-15 2006-10-19 Siliconware Precision Industries Co., Ltd. Thermally enhanced semiconductor package and fabrication method thereof
DE102005026098B3 (en) 2005-06-01 2007-01-04 Infineon Technologies Ag Benefits and semiconductor device of a composite plate with semiconductor chips and the plastic housing composition and methods of making the same
US7635641B2 (en) 2005-10-11 2009-12-22 Amitec-Advanced Multilayer Interconnect Technologies Ltd. Integrated circuit support structures and their fabrication
US20080136041A1 (en) 2006-01-24 2008-06-12 Tessera Interconnect Materials, Inc. Structure and method of making interconnect element having metal traces embedded in surface of dielectric
US20070176281A1 (en) 2006-01-27 2007-08-02 Advanced Semiconductor Engineering, Inc. Semiconductor package
US8704349B2 (en) 2006-02-14 2014-04-22 Stats Chippac Ltd. Integrated circuit package system with exposed interconnects
DE102006009789B3 (en) 2006-03-01 2007-10-04 Infineon Technologies Ag A process for producing a semiconductor device of a composite plate with semiconductor chips and the plastic housing composition
US7425464B2 (en) 2006-03-10 2008-09-16 Freescale Semiconductor, Inc. Semiconductor device packaging
US8072059B2 (en) 2006-04-19 2011-12-06 Stats Chippac, Ltd. Semiconductor device and method of forming UBM fixed relative to interconnect structure for alignment of semiconductor die
US7665862B2 (en) 2006-09-12 2010-02-23 Cree, Inc. LED lighting fixture
US7830004B2 (en) 2006-10-27 2010-11-09 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with base layers comprising alloy 42
US7595553B2 (en) 2006-11-08 2009-09-29 Sanyo Electric Co., Ltd. Packaging board and manufacturing method therefor, semiconductor module and mobile apparatus
US8193034B2 (en) 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
US7588951B2 (en) 2006-11-17 2009-09-15 Freescale Semiconductor, Inc. Method of packaging a semiconductor device and a prefabricated connector
US7808797B2 (en) 2006-12-11 2010-10-05 Intel Corporation Microelectronic substrate including embedded components and spacer layer and method of forming same
US20080142946A1 (en) 2006-12-13 2008-06-19 Advanced Chip Engineering Technology Inc. Wafer level package with good cte performance
US7453148B2 (en) 2006-12-20 2008-11-18 Advanced Chip Engineering Technology Inc. Structure of dielectric layers in built-up layers of wafer level package
US7812434B2 (en) 2007-01-03 2010-10-12 Advanced Chip Engineering Technology Inc Wafer level package with die receiving through-hole and method of the same
KR20080102022A (en) 2007-05-17 2008-11-24 삼성전자주식회사 Methods of fabricating circuit board and semiconductor package, and circuit board and semiconductor package fabricated by the methods
US7868445B2 (en) 2007-06-25 2011-01-11 Epic Technologies, Inc. Integrated structures and methods of fabrication thereof with fan-out metallization on a chips-first chip layer
US7781877B2 (en) 2007-08-07 2010-08-24 Micron Technology, Inc. Packaged integrated circuit devices with through-body conductive vias, and methods of making same
US7595226B2 (en) 2007-08-29 2009-09-29 Freescale Semiconductor, Inc. Method of packaging an integrated circuit die
US7834464B2 (en) 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
KR101501739B1 (en) 2008-03-21 2015-03-11 삼성전자주식회사 A semiconductor package-producing
US7759163B2 (en) 2008-04-18 2010-07-20 Infineon Technologies Ag Semiconductor module
JP2009290135A (en) 2008-05-30 2009-12-10 Fujitsu Ltd Manufacturing method of printed wiring board, and conductive cement
US8039303B2 (en) 2008-06-11 2011-10-18 Stats Chippac, Ltd. Method of forming stress relief layer between die and interconnect structure
US7767495B2 (en) 2008-08-25 2010-08-03 Infineon Technologies Ag Method for the fabrication of semiconductor devices including attaching chips to each other with a dielectric material
US7842541B1 (en) 2008-09-24 2010-11-30 Amkor Technology, Inc. Ultra thin package and fabrication method
US7763976B2 (en) 2008-09-30 2010-07-27 Freescale Semiconductor, Inc. Integrated circuit module with integrated passive device
US7741151B2 (en) 2008-11-06 2010-06-22 Freescale Semiconductor, Inc. Integrated circuit package formation
US7858441B2 (en) 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
US8017515B2 (en) 2008-12-10 2011-09-13 Stats Chippac, Ltd. Semiconductor device and method of forming compliant polymer layer between UBM and conformal dielectric layer/RDL for stress relief
US7799602B2 (en) 2008-12-10 2010-09-21 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer over a semiconductor die after forming a build-up interconnect structure
US20100224983A1 (en) 2009-03-03 2010-09-09 Min-Lung Huang Semiconductor package structure and manufacturing method thereof
US8133762B2 (en) 2009-03-17 2012-03-13 Stats Chippac, Ltd. Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core
US8378383B2 (en) 2009-03-25 2013-02-19 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer between stacked semiconductor die
US20100289132A1 (en) 2009-05-13 2010-11-18 Shih-Fu Huang Substrate having embedded single patterned metal layer, and package applied with the same, and methods of manufacturing of the substrate and package
US8288869B2 (en) 2009-05-13 2012-10-16 Advanced Semiconductor Engineering, Inc. Semiconductor package with substrate having single metal layer and manufacturing methods thereof
US20100308449A1 (en) 2009-06-03 2010-12-09 Hung-Jen Yang Semiconductor packages and manufacturing method thereof
US20100314746A1 (en) 2009-06-11 2010-12-16 Chueh-An Hsieh Semiconductor package and manufacturing method thereof
US8021930B2 (en) 2009-08-12 2011-09-20 Stats Chippac, Ltd. Semiconductor device and method of forming dam material around periphery of die to reduce warpage
US20110084372A1 (en) 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same
US8334594B2 (en) 2009-10-14 2012-12-18 Advanced Semiconductor Engineering, Inc. Chip having a metal pillar structure
US20110127654A1 (en) 2009-11-27 2011-06-02 Advanced Semiconductor Engineering, Inc.., Semiconductor Package and Manufacturing Methods Thereof
GB0921634D0 (en) 2009-12-10 2010-01-27 Artificial Lift Co Ltd Seal,assembly and method,particularly for downhole electric cable terminations
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8320134B2 (en) 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
US8264089B2 (en) 2010-03-17 2012-09-11 Maxim Integrated Products, Inc. Enhanced WLP for superior temp cycling, drop test and high current applications
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US20110241194A1 (en) 2010-04-02 2011-10-06 Advanced Semiconductor Engineering, Inc. Stacked Semiconductor Device Package Assemblies with Reduced Wire Sweep and Manufacturing Methods Thereof
US8558392B2 (en) 2010-05-14 2013-10-15 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof

Patent Citations (104)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2002003A (en) * 1930-09-20 1935-05-21 Ig Farbenindustrie Ag Production of acetylene and carbon black
US3959674A (en) * 1973-09-28 1976-05-25 Nicolas Kokinopoulos Pulse counters having a magnetic pole wheel
US5019535A (en) * 1989-03-28 1991-05-28 General Electric Company Die attachment method using nonconductive adhesive for use in high density interconnected assemblies
US5091769A (en) * 1991-03-27 1992-02-25 Eichelberger Charles W Configuration for testing and burn-in of integrated circuit chips
US5111278A (en) * 1991-03-27 1992-05-05 Eichelberger Charles W Three-dimensional multichip module systems
US5315486A (en) * 1991-12-16 1994-05-24 General Electric Company Hermetically packaged HDI electronic system
US6046071A (en) * 1993-06-01 2000-04-04 Mitsubishi Denki Kabushiki Kaisha Plastic molded semiconductor package and method of manufacturing the same
US5710062A (en) * 1993-06-01 1998-01-20 Mitsubishi Denki Kabushiki Kaisha Plastic molded semiconductor package and method of manufacturing the same
US5519936A (en) * 1994-01-28 1996-05-28 International Business Machines Corporation Method of making an electronic package with a thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto
US6177636B1 (en) * 1994-12-29 2001-01-23 Tessera, Inc. Connection components with posts
US5745984A (en) * 1995-07-10 1998-05-05 Martin Marietta Corporation Method for making an electronic module
US5874784A (en) * 1995-10-25 1999-02-23 Sharp Kabushiki Kaisha Semiconductor device having external connection terminals provided on an interconnection plate and fabrication process therefor
US5866952A (en) * 1995-11-30 1999-02-02 Lockheed Martin Corporation High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate
US6232650B1 (en) * 1997-07-30 2001-05-15 Hitachi, Ltd. Semiconductor device having a chip mounted on a flexible substrate with separated insulation layers to prevent short-circuiting
US6198165B1 (en) * 1998-05-29 2001-03-06 Sharp Kabushiki Kaisha Semiconductor device
US20030030137A1 (en) * 1998-09-09 2003-02-13 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
US6239482B1 (en) * 1999-06-21 2001-05-29 General Electric Company Integrated circuit package including window frame
US6232151B1 (en) * 1999-11-01 2001-05-15 General Electric Company Power electronic module packaging
US6377461B1 (en) * 1999-11-01 2002-04-23 General Electric Company Power electronic module packaging
US6396148B1 (en) * 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
US20020056192A1 (en) * 2000-09-27 2002-05-16 Tokihito Suwa Method of producing multilayer printed wiring board and multilayer printed wiring board
US20040080054A1 (en) * 2000-12-19 2004-04-29 Hitachi Cable, Ltd. Wiring board, semiconductor device, and process for production of wiring board
US6663946B2 (en) * 2001-02-28 2003-12-16 Kyocera Corporation Multi-layer wiring substrate
US20060071315A1 (en) * 2001-03-09 2006-04-06 Oh Kwang S Method of forming a stacked semiconductor package
US20030098502A1 (en) * 2001-05-17 2003-05-29 Sharp Kabushiki Kaisha Semiconductor package substrate, semiconductor package
US20030034553A1 (en) * 2001-08-15 2003-02-20 Kazuaki Ano Low profile ball-grid array package for high power
US6861757B2 (en) * 2001-09-03 2005-03-01 Nec Corporation Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device
US20030090883A1 (en) * 2001-10-18 2003-05-15 Matsushita Electric Industrial Co., Ltd. Component built-in module and method for producing the same
US6845554B2 (en) * 2001-11-22 2005-01-25 Infineon Technologies Ag Method for connection of circuit units
US6701614B2 (en) * 2002-02-15 2004-03-09 Advanced Semiconductor Engineering Inc. Method for making a build-up package of a semiconductor
US6680529B2 (en) * 2002-02-15 2004-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor build-up package
US20040012099A1 (en) * 2002-02-26 2004-01-22 Toshinori Nakayama Semiconductor device and manufacturing method for the same, circuit board, and electronic device
US6556908B1 (en) * 2002-03-04 2003-04-29 Ford Global Technologies, Inc. Attitude sensing system for an automotive vehicle relative to the road
US20090047797A1 (en) * 2002-03-22 2009-02-19 Anderson Curtis W Method for producing shock and tamper resistant microelectronic devices
US20070052076A1 (en) * 2002-04-29 2007-03-08 Ramos Mary J Partially Patterned Lead Frames and Methods of Making and Using the Same in Semiconductor Packaging
US6977348B2 (en) * 2002-05-28 2005-12-20 Via Technologies, Inc. High density laminated substrate structure and manufacture method thereof
US20050006752A1 (en) * 2002-07-03 2005-01-13 Tsuyoshi Ogawa Multi-layer interconnection circuit module and manufacturing method thereof
US7173330B2 (en) * 2002-08-27 2007-02-06 Micron Technology, Inc. Multiple chip semiconductor package
US7692286B1 (en) * 2002-11-08 2010-04-06 Amkor Technology, Inc. Two-sided fan-out wafer escape package
US7361533B1 (en) * 2002-11-08 2008-04-22 Amkor Technology, Inc. Stacked embedded leadframe
US7714431B1 (en) * 2002-11-08 2010-05-11 Amkor Technology, Inc. Electronic component package comprising fan-out and fan-in traces
US20040201101A1 (en) * 2003-04-10 2004-10-14 Kang Seung H. Aluminum pad power bus and signal routing for integrated circuit devices utilizing copper technology interconnect structures
US7045908B2 (en) * 2003-04-14 2006-05-16 Oki Electric Industry Co., Ltd. Semiconductor device and method for manufacturing the same
US6838776B2 (en) * 2003-04-18 2005-01-04 Freescale Semiconductor, Inc. Circuit device with at least partial packaging and method for forming
US7361987B2 (en) * 2003-04-18 2008-04-22 Freescale Semiconductor, Inc. Circuit device with at least partial packaging and method for forming
US7364944B2 (en) * 2003-05-28 2008-04-29 Siliconware Precision Industries Co., Ltd. Method for fabricating thermally enhanced semiconductor package
US7048450B2 (en) * 2003-07-14 2006-05-23 Infineon Technologies, Ag Optoelectronic module with transmitter chip and connecting piece for the module with respect to an optical fiber and with respect to a circuit board, and methods for producing the same
US7932599B2 (en) * 2003-07-24 2011-04-26 Sony Corporation Semiconductor component of semiconductor chip size with flip-chip-like external contacts
US7163843B2 (en) * 2003-07-24 2007-01-16 Infineon Technologies Ag Semiconductor component of semiconductor chip size with flip-chip-like external contacts, and method of producing the same
US20070096311A1 (en) * 2003-09-26 2007-05-03 Tessera, Inc. Structure and method of making capped chips having vertical interconnects
US7514767B2 (en) * 2003-12-03 2009-04-07 Advanced Chip Engineering Technology Inc. Fan out type wafer level package structure and method of the same
US7667318B2 (en) * 2003-12-03 2010-02-23 Advanced Chip Engineering Technology Inc. Fan out type wafer level package structure and method of the same
US7015075B2 (en) * 2004-02-09 2006-03-21 Freescale Semiconuctor, Inc. Die encapsulation using a porous carrier
US7482198B2 (en) * 2004-04-26 2009-01-27 Infineon Technologies Ag Method for producing through-contacts and a semiconductor component with through-contacts
US7501310B2 (en) * 2004-04-28 2009-03-10 Advanced Chip Engineering Technology Inc. Structure of image sensor module and method for manufacturing of wafer level package
US7319049B2 (en) * 2004-05-10 2008-01-15 Shinko Electric Industries Co., Ltd. Method of manufacturing an electronic parts packaging structure
US20060065387A1 (en) * 2004-09-28 2006-03-30 General Electric Company Electronic assemblies and methods of making the same
US7371617B2 (en) * 2004-10-27 2008-05-13 Siliconware Precision Industries Co., Ltd. Method for fabricating semiconductor package with heat sink
US7511365B2 (en) * 2005-04-21 2009-03-31 Industrial Technology Research Institute Thermal enhanced low profile package structure
US20070057364A1 (en) * 2005-09-01 2007-03-15 Wang Carl B Low temperature co-fired ceramic (LTCC) tape compositions, light emitting diode (LED) modules, lighting devices and method of forming thereof
US20100096739A1 (en) * 2005-10-27 2010-04-22 Panasonic Corporation Stacked semiconductor module
US7656501B2 (en) * 2005-11-16 2010-02-02 Asml Netherlands B.V. Lithographic apparatus
US7344917B2 (en) * 2005-11-30 2008-03-18 Freescale Semiconductor, Inc. Method for packaging a semiconductor device
US20090129037A1 (en) * 2006-01-13 2009-05-21 Yutaka Yoshino Printed wiring board with built-in semiconductor element, and process for producing the same
US7675157B2 (en) * 2006-01-30 2010-03-09 Marvell World Trade Ltd. Thermal enhanced package
US20070234563A1 (en) * 2006-04-11 2007-10-11 Shinko Electric Industries Co., Ltd. Method of forming solder connection portions, method of forming wiring substrate and method of producing semiconductor device
US7682972B2 (en) * 2006-06-01 2010-03-23 Amitec-Advanced Multilayer Interconnect Technoloiges Ltd. Advanced multilayer coreless support structures and method for their fabrication
US20080081161A1 (en) * 2006-09-28 2008-04-03 Matsushita Electric Industrial Co., Ltd. Wiring board and semiconductor device
US20080089048A1 (en) * 2006-10-11 2008-04-17 Shinko Electric Industries Co., Ltd. Substrate with built-in electronic component and method for manufacturing the same
US7476563B2 (en) * 2006-11-17 2009-01-13 Freescale Semiconductor, Inc. Method of packaging a device using a dielectric layer
US20090101400A1 (en) * 2007-06-19 2009-04-23 Murata Manufacturing Co., Ltd. Method for manufacturing component-embedded substrate and component-embedded substrate
US20120077311A1 (en) * 2007-08-10 2012-03-29 Pyoung-Wan Kim Semiconductor package having buried post in encapsulant and method of manufacturing the same
US20090045512A1 (en) * 2007-08-15 2009-02-19 Harry Hedler Carrier substrate and integrated circuit
US20090075428A1 (en) * 2007-09-13 2009-03-19 Freescale Semiconductor, Inc. Electromagnetic shield formation for integrated circuit die package
US20090102066A1 (en) * 2007-10-22 2009-04-23 Advanced Semiconductor Engineering, Inc. Chip package structure and method of manufacturing the same
US20090115072A1 (en) * 2007-11-01 2009-05-07 Texas Instruments Incorporated BGA Package with Traces for Plating Pads Under the Chip
US20090127686A1 (en) * 2007-11-21 2009-05-21 Advanced Chip Engineering Technology Inc. Stacking die package structure for semiconductor devices and method of the same
US20100084759A1 (en) * 2007-12-20 2010-04-08 Geng-Shin Shen Die Rearrangement Package Structure Using Layout Process to Form a Compliant Configuration
US7662667B2 (en) * 2007-12-20 2010-02-16 Chipmos Technologies Inc Die rearrangement package structure using layout process to form a compliant configuration
US20090224391A1 (en) * 2008-03-04 2009-09-10 Stats Chippac, Ltd. Wafer Level Die Integration and Method Therefor
US20100006330A1 (en) * 2008-07-11 2010-01-14 Advanced Semiconductor Engineering, Inc. Structure and process of embedded chip package
US20100006994A1 (en) * 2008-07-14 2010-01-14 Stats Chippac, Ltd. Embedded Semiconductor Die Package and Method of Making the Same Using Metal Frame Carrier
US20100072618A1 (en) * 2008-09-22 2010-03-25 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a Wafer Level Package with Bump Interconnection
US20100072599A1 (en) * 2008-09-22 2010-03-25 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a Wafer Level Package with Top and Bottom Solder Bump Interconnection
US20100109132A1 (en) * 2008-10-31 2010-05-06 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US8399776B2 (en) * 2009-05-13 2013-03-19 Advanced Semiconductor Engineering, Inc. Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package
US8367473B2 (en) * 2009-05-13 2013-02-05 Advanced Semiconductor Engineering, Inc. Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof
US8110916B2 (en) * 2009-06-19 2012-02-07 Advanced Semiconductor Engineering, Inc. Chip package structure and manufacturing methods thereof
US20110018118A1 (en) * 2009-07-21 2011-01-27 Advanced Semiconductor Engineering, Inc. Semiconductor Device Packages, Redistribution Structures, and Manufacturing Methods Thereof
US8358001B2 (en) * 2009-07-23 2013-01-22 Advanced Semiconductor Engineering, Inc. Semiconductor device packages, redistribution structures, and manufacturing methods thereof
US20110018124A1 (en) * 2009-07-23 2011-01-27 Advanced Semiconductor Engineering, Inc. Semiconductor Device Packages, Redistribution Structures, and Manufacturing Methods Thereof
US20110037169A1 (en) * 2009-08-12 2011-02-17 Stats Chippac, Ltd. Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structures
US20110057301A1 (en) * 2009-09-08 2011-03-10 Advanced Semiconductor Engineering, Inc. Semiconductor package
US20110068453A1 (en) * 2009-09-21 2011-03-24 Cho Namju Integrated circuit packaging system with encapsulated via and method of manufacture thereof
US20110068459A1 (en) * 2009-09-23 2011-03-24 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Interposer with Opening to Contain Semiconductor Die
US20110074008A1 (en) * 2009-09-25 2011-03-31 Tung-Hsien Hsieh Semiconductor flip chip package
US20110084370A1 (en) * 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Semiconductor package and process for fabricating same
US20110115082A1 (en) * 2009-11-16 2011-05-19 International Business Machines Corporation Configurable interposer
US20110115060A1 (en) * 2009-11-19 2011-05-19 Advanced Semiconductor Engineering, Inc. Wafer-Level Semiconductor Device Packages with Electromagnetic Interference Shielding
US8378466B2 (en) * 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
US8372689B2 (en) * 2010-01-21 2013-02-12 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof
US8405213B2 (en) * 2010-03-22 2013-03-26 Advanced Semiconductor Engineering, Inc. Semiconductor package including a stacking element
US20120038053A1 (en) * 2010-08-16 2012-02-16 Stats Chippac, Ltd. Semiconductor Device and Method of Forming FO-WLCSP Having Conductive Layers and Conductive Vias Separated by Polymer Layers
US20120056321A1 (en) * 2010-09-07 2012-03-08 Stats Chippac, Ltd. Semiconductor Device and Method of Forming WLP With Semiconductor Die Embedded Within Penetrable Encapsulant Between TSV Interposers

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8288869B2 (en) 2009-05-13 2012-10-16 Advanced Semiconductor Engineering, Inc. Semiconductor package with substrate having single metal layer and manufacturing methods thereof
US20100289132A1 (en) * 2009-05-13 2010-11-18 Shih-Fu Huang Substrate having embedded single patterned metal layer, and package applied with the same, and methods of manufacturing of the substrate and package
US20100314744A1 (en) * 2009-05-13 2010-12-16 Shih-Fu Huang Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof
US20100320610A1 (en) * 2009-05-13 2010-12-23 Shih-Fu Huang Semiconductor package with substrate having single metal layer and manufacturing methods thereof
US8399776B2 (en) 2009-05-13 2013-03-19 Advanced Semiconductor Engineering, Inc. Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package
US8367473B2 (en) 2009-05-13 2013-02-05 Advanced Semiconductor Engineering, Inc. Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof
US20100288541A1 (en) * 2009-05-13 2010-11-18 Advanced Semiconductor Engineering, Inc. Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package
US8330267B2 (en) 2009-09-08 2012-12-11 Advanced Semiconductor Engineering, Inc. Semiconductor package
US20110057301A1 (en) * 2009-09-08 2011-03-10 Advanced Semiconductor Engineering, Inc. Semiconductor package
US9165900B2 (en) 2009-10-14 2015-10-20 Advanced Semiconductor Engineering, Inc. Semiconductor package and process for fabricating same
US9564346B2 (en) 2009-10-14 2017-02-07 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same
US20110084370A1 (en) * 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Semiconductor package and process for fabricating same
US8786062B2 (en) 2009-10-14 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package and process for fabricating same
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US9196597B2 (en) 2010-01-13 2015-11-24 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8884424B2 (en) 2010-01-13 2014-11-11 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US20110169150A1 (en) * 2010-01-13 2011-07-14 Advanced Semiconductor Engineering, Inc. Semiconductor Package with Single Sided Substrate Design and Manufacturing Methods Thereof
US9349611B2 (en) 2010-03-22 2016-05-24 Advanced Semiconductor Engineering, Inc. Stackable semiconductor package and manufacturing method thereof
CN102751203A (en) * 2011-04-22 2012-10-24 日月光半导体制造股份有限公司 Semiconductor encapsulation structure and manufacture method of semiconductor encapsulation structure
CN103426855A (en) * 2012-05-18 2013-12-04 矽品精密工业股份有限公司 Semiconductor package and fabrication method thereof
US9355983B1 (en) 2014-06-27 2016-05-31 Stats Chippac Ltd. Integrated circuit packaging system with interposer structure and method of manufacture thereof
US9659897B1 (en) 2014-06-27 2017-05-23 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with interposer structure and method of manufacture thereof

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