DE102004020497B8 - Verfahren zur Herstellung von Durchkontaktierungen und Halbleiterbauteil mit derartigen Durchkontaktierungen - Google Patents
Verfahren zur Herstellung von Durchkontaktierungen und Halbleiterbauteil mit derartigen Durchkontaktierungen Download PDFInfo
- Publication number
- DE102004020497B8 DE102004020497B8 DE102004020497A DE102004020497A DE102004020497B8 DE 102004020497 B8 DE102004020497 B8 DE 102004020497B8 DE 102004020497 A DE102004020497 A DE 102004020497A DE 102004020497 A DE102004020497 A DE 102004020497A DE 102004020497 B8 DE102004020497 B8 DE 102004020497B8
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- semiconductor
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- 239000004065 semiconductor Substances 0.000 title 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/0373—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement containing additives, e.g. fillers
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
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- H05K2201/0206—Materials
- H05K2201/0215—Metallic fillers
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0242—Shape of an individual particle
- H05K2201/0257—Nanoparticles
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
- H05K2203/105—Using an electrical field; Special methods of applying an electric potential
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Non-Insulated Conductors (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Electroplating Methods And Accessories (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102004020497A DE102004020497B8 (de) | 2004-04-26 | 2004-04-26 | Verfahren zur Herstellung von Durchkontaktierungen und Halbleiterbauteil mit derartigen Durchkontaktierungen |
PCT/DE2005/000754 WO2005104226A2 (de) | 2004-04-26 | 2005-04-25 | Verfahren zur herstellung von durchkontaktierungen durch eine kunststoffmasse und halbleiterbauteil mit derartigen durchkontaktierungen |
US11/586,740 US7482198B2 (en) | 2004-04-26 | 2006-10-26 | Method for producing through-contacts and a semiconductor component with through-contacts |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102004020497A DE102004020497B8 (de) | 2004-04-26 | 2004-04-26 | Verfahren zur Herstellung von Durchkontaktierungen und Halbleiterbauteil mit derartigen Durchkontaktierungen |
Publications (2)
Publication Number | Publication Date |
---|---|
DE102004020497B3 DE102004020497B3 (de) | 2006-01-19 |
DE102004020497B8 true DE102004020497B8 (de) | 2006-06-14 |
Family
ID=35197629
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE102004020497A Expired - Fee Related DE102004020497B8 (de) | 2004-04-26 | 2004-04-26 | Verfahren zur Herstellung von Durchkontaktierungen und Halbleiterbauteil mit derartigen Durchkontaktierungen |
Country Status (3)
Country | Link |
---|---|
US (1) | US7482198B2 (de) |
DE (1) | DE102004020497B8 (de) |
WO (1) | WO2005104226A2 (de) |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5636188B2 (ja) | 2006-07-21 | 2014-12-03 | ヴァルティオン テクニリネン ツッツキムスケスクス | 導体および半導体の製造方法 |
FI122011B (fi) | 2007-06-08 | 2011-07-15 | Teknologian Tutkimuskeskus Vtt | Menetelmä elektroniikkamoduulin tuottamiseksi, välituote elektroniikkamoduulin valmistamiseksi, muistielementti, painettu elektroniikkatuote, anturilaite sekä RFID-tunniste |
FI122644B (fi) | 2007-06-08 | 2012-04-30 | Teknologian Tutkimuskeskus Vtt | Menetelmä sähköisesti johtavien tai puolijohtavien reittien muodostamiseksi substraatille sekä menetelmän käyttö transistorien tuottamiseen ja anturien valmistukseen |
FI122014B (fi) | 2007-06-08 | 2011-07-15 | Teknologian Tutkimuskeskus Vtt | Menetelmä ja laite nanopartikkelijärjestelmien toiminnallistamiseksi |
KR100842921B1 (ko) * | 2007-06-18 | 2008-07-02 | 주식회사 하이닉스반도체 | 반도체 패키지의 제조 방법 |
US7781877B2 (en) | 2007-08-07 | 2010-08-24 | Micron Technology, Inc. | Packaged integrated circuit devices with through-body conductive vias, and methods of making same |
KR100885924B1 (ko) | 2007-08-10 | 2009-02-26 | 삼성전자주식회사 | 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법 |
TWI360207B (en) * | 2007-10-22 | 2012-03-11 | Advanced Semiconductor Eng | Chip package structure and method of manufacturing |
FR2923081B1 (fr) * | 2007-10-26 | 2009-12-11 | 3D Plus | Procede d'interconnexion verticale de modules electroniques 3d par des vias. |
JP2012510721A (ja) * | 2008-12-02 | 2012-05-10 | ピコドリル・エス・アー | 基板内への構造の導入方法 |
TWI456715B (zh) * | 2009-06-19 | 2014-10-11 | Advanced Semiconductor Eng | 晶片封裝結構及其製造方法 |
US8310835B2 (en) * | 2009-07-14 | 2012-11-13 | Apple Inc. | Systems and methods for providing vias through a modular component |
TWI466259B (zh) * | 2009-07-21 | 2014-12-21 | Advanced Semiconductor Eng | 半導體封裝件、其製造方法及重佈晶片封膠體的製造方法 |
TWI405306B (zh) * | 2009-07-23 | 2013-08-11 | Advanced Semiconductor Eng | 半導體封裝件、其製造方法及重佈晶片封膠體 |
WO2011020563A1 (en) * | 2009-08-19 | 2011-02-24 | Picodrill Sa | A method of producing an electrically conducting via in a substrate |
US8242543B2 (en) * | 2009-08-26 | 2012-08-14 | Qualcomm Incorporated | Semiconductor wafer-to-wafer bonding for dissimilar semiconductor dies and/or wafers |
US20110084372A1 (en) | 2009-10-14 | 2011-04-14 | Advanced Semiconductor Engineering, Inc. | Package carrier, semiconductor package, and process for fabricating same |
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-
2004
- 2004-04-26 DE DE102004020497A patent/DE102004020497B8/de not_active Expired - Fee Related
-
2005
- 2005-04-25 WO PCT/DE2005/000754 patent/WO2005104226A2/de active Application Filing
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2006
- 2006-10-26 US US11/586,740 patent/US7482198B2/en not_active Expired - Fee Related
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DE2902002A1 (de) * | 1979-01-19 | 1980-07-31 | Gerhard Krause | Dreidimensional integrierte elektronische schaltungen |
EP0611129A2 (de) * | 1993-02-08 | 1994-08-17 | General Electric Company | Eingebettetes Substrat für integrierte Schaltungsmodule |
US6190509B1 (en) * | 1997-03-04 | 2001-02-20 | Tessera, Inc. | Methods of making anisotropic conductive elements for use in microelectronic packaging |
DE10153609C2 (de) * | 2001-11-02 | 2003-10-16 | Infineon Technologies Ag | Verfahren zur Herstellung eines elektronischen Bauelements mit mehreren übereinander gestapelten und miteinander kontaktierten Chips |
Also Published As
Publication number | Publication date |
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WO2005104226A2 (de) | 2005-11-03 |
WO2005104226A3 (de) | 2006-06-08 |
US7482198B2 (en) | 2009-01-27 |
US20070099345A1 (en) | 2007-05-03 |
DE102004020497B3 (de) | 2006-01-19 |
WO2005104226A8 (de) | 2007-03-01 |
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