WO2017124671A1 - Procédé d'encapsulation et structure d'encapsulation pour puce de sortance - Google Patents

Procédé d'encapsulation et structure d'encapsulation pour puce de sortance Download PDF

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Publication number
WO2017124671A1
WO2017124671A1 PCT/CN2016/082832 CN2016082832W WO2017124671A1 WO 2017124671 A1 WO2017124671 A1 WO 2017124671A1 CN 2016082832 W CN2016082832 W CN 2016082832W WO 2017124671 A1 WO2017124671 A1 WO 2017124671A1
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Prior art keywords
fan
packaging
out type
bumps
type chip
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PCT/CN2016/082832
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English (en)
Chinese (zh)
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仇月东
林正忠
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中芯长电半导体（江阴）有限公司
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Publication of WO2017124671A1 publication Critical patent/WO2017124671A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Definitions

  • the present invention relates to a semiconductor chip packaging method and package structure, and more particularly to a fan-out type chip packaging method and package structure.
  • the existing packaging technologies include ball grid array package (BGA), chip size package (CSP), and wafer level package (WLP). ), three-dimensional packaging (3D) and system packaging (SiP).
  • BGA ball grid array package
  • CSP chip size package
  • WLP wafer level package
  • 3D three-dimensional packaging
  • SiP system packaging
  • the wafer-level package (WLP) is gradually adopted by most semiconductor manufacturers due to its excellent advantages. All or most of the process steps are completed on the silicon wafer that has completed the pre-process, and finally the wafer is finished. Cut directly into separate, independent devices.
  • Wafer-level package has its unique advantages: 1 package processing efficiency, can be processed simultaneously with multiple wafers; 2 with the advantages of flip chip packaging, namely light, thin, short, small; 3 and the previous process Than, just added two steps of pin rewiring (RDL) and bump fabrication, the rest are all traditional processes; 4 reduces the number of tests in traditional packages. Therefore, the world's major IC packaging companies have invested in the research, development and production of such WLP.
  • the semiconductor chip 203 in which the initial bumps 104 are formed in advance is generally pasted on the film 102 of the carrier 101, as shown in FIG. 1a, and then the molding material is used.
  • 105 is molded, as shown in Fig. 1b, after the plastic sealing, the carrier 101 and the film 102 are removed, as shown in Fig. 1c, after which the rewiring layer 106 is formed and the bumps 107 are formed, as shown in Fig. 1d.
  • the molding material has a large thermal expansion coefficient, which causes deformation and bending of the metal bumps, especially the breakage of the initial bumps. , which greatly affects the performance of the packaged product.
  • an object of the present invention is to provide a method for packaging a fan-out type chip for solving the problem of low package quality of a semiconductor chip with an initial bump in the prior art.
  • the present invention provides a method of packaging a fan-out type chip, the fan-out type
  • the packaging method comprises: step 1), providing a chip with bumps, forming a dielectric layer on the surface of the chip, the surface of the dielectric layer exposing each bump; and step 2) providing a carrier having an adhesive layer formed on the surface And bonding each of the bumped chips to the adhesive layer; step 3), packaging each of the bumped chips; and step 4) forming a rewiring layer on each of the bumped chips to An interconnection between the chips is implemented; and in step 5), an under bump metal layer and micro bumps are formed on the rewiring layer.
  • the method further includes the step of removing the carrier and the adhesive layer.
  • the carrier comprises one of glass, a transparent semiconductor material, and a transparent polymer.
  • the adhesive layer comprises a UV adhesive, and in the step 6), the UV adhesive is reduced in viscosity by an exposure method to achieve separation from the molding material.
  • the dielectric layer includes one of silicon dioxide, phosphosilicate glass, silicon oxycarbide, silicon carbide, and a polymer.
  • a dielectric layer is formed on the surface of the chip by spin coating, chemical vapor deposition or plasma enhanced chemical vapor deposition.
  • the height of the molding material after packaging each of the bump-equipped chips does not exceed the height of each of the bumps, so that the bumps are exposed to the plastic package.
  • the surface of the material is not limited to the surface of the material.
  • the molding material used for packaging each of the bump-equipped chips includes one of polyimide, silica gel and epoxy resin. .
  • the process of packaging each of the bump-equipped chips includes: an injection molding process, a compression molding process, a printing process, and a transfer molding process.
  • an injection molding process a compression molding process, a printing process, and a transfer molding process.
  • the step 4) comprises: step 4-1), forming an insulating medium on each of the bumped chips; and step 4-2) using a photolithography process And forming an via hole corresponding to the electrical extraction of the chip in the insulating medium; and filling the metal conductor into each of the through holes to form a connection via hole; step 4-4)
  • the surface of the insulating medium forms a metal wiring layer correspondingly connected to the connection via.
  • the metal wiring layer is formed by an evaporation process, a sputtering process, an electroplating process, or an electroless plating process.
  • the material of the metal wiring layer includes one of aluminum, copper, tin, nickel, gold, and silver.
  • the micro bumps include gold solder balls, silver tin One of a solder ball or a copper solder ball, or the micro bump includes a copper pillar, a nickel layer formed on the copper pillar, and a solder ball formed on the nickel layer.
  • the invention further provides a package structure of a fan-out type chip, comprising: a chip with a bump, a surface of the chip is formed with a dielectric layer, the surface of the dielectric layer is exposed with each bump; a plastic sealing material is filled in each strip Between the chips of the bumps, the height of the molding material does not exceed the bumps so that the bumps are exposed on the surface of the molding material; and the rewiring layer is formed on the surface of each of the bumped chips to realize the chips. Inter-connector; and under-bump metal layers and micro-bumps are formed over the re-wiring layer.
  • the dielectric layer includes one of silicon dioxide, phosphosilicate glass, silicon oxycarbide, silicon carbide, and a polymer.
  • the molding material includes one of polyimide, silica gel, and epoxy resin.
  • the rewiring layer includes: an insulating medium formed on each of the bump-equipped chips; formed in the insulating medium and the chip electrical lead-out a corresponding through hole; a metal conductor filled in the through hole; and a metal wiring layer formed on the surface of the insulating medium and correspondingly connected to the connection via.
  • the material of the metal wiring layer includes one of aluminum, copper, tin, nickel, gold, and silver.
  • the micro bumps comprise one of a gold solder ball, a silver solder ball, and a copper solder ball.
  • the microbumps comprise a copper pillar, a nickel layer formed on the copper pillar, and a solder ball formed on the nickel layer.
  • the package method and package structure of the fan-out type chip of the present invention have the following advantageous effects: the present invention forms a dielectric layer on the surface of the chip with bumps, and the bumps are exposed on the surface of the dielectric layer. Not only can each bump be protected, but also interconnection between subsequent chips can be realized. Selecting a dielectric layer with a lower thermal expansion coefficient can avoid the breakage or breakage of the bump due to thermal expansion during the subsequent fabrication of the rewiring layer or the solder microbump, thereby greatly improving the performance of the package while improving the yield. .
  • the structure method of the invention is simple and has broad application prospects in the field of semiconductor packaging.
  • FIG. 1a to FIG. 1d are schematic diagrams showing the steps of the steps of the packaging method of a fan-out type chip in the prior art.
  • FIGS. 2 to 9 are schematic diagrams showing the steps of the steps of the package method of the fan-out type chip of the present invention.
  • the embodiment provides a method for packaging a fan-out type chip, and the fan-out type packaging method includes:
  • step 1) is performed to provide a chip 201 with bumps 203, and a dielectric layer 204 is formed on the surface of the chip, and the bumps 203 are exposed on the surface of the dielectric layer 204.
  • step 1-1) is performed to provide a wafer of the chip 201 with the bumps 203, and a dielectric layer 204 is formed on the surface of the wafer, and the surface of the dielectric layer 204 is exposed. Bump 203.
  • the dielectric layer 204 includes one of silicon dioxide, phosphosilicate glass, silicon oxycarbide, silicon carbide, and a polymer.
  • the dielectric layer 204 is selected as a material having a low coefficient of thermal expansion, which can avoid the damage or breakage of the bumps 203 due to thermal expansion during the subsequent fabrication of the rewiring layer 208 or the solder microbumps 211. The performance of the package while improving the yield.
  • the dielectric layer 204 may be formed on the surface of the chip by spin coating, chemical vapor deposition, or plasma enhanced chemical vapor deposition.
  • the dielectric layer 204 is a silicon dioxide layer formed by ion-enhanced chemical vapor deposition.
  • step 1-2 is then performed to split the wafer to obtain a separate chip with bumps 203 and dielectric layer 204.
  • the bumps 203 are fabricated on the metal pads 202 of the chip.
  • step 2) is then performed to provide a carrier 205 having an adhesive layer 206 formed on its surface, and the chips 201 of each bump 203 are bonded to the adhesive layer 206.
  • the adhesive layer 206 may be a material such as a tape, a UV adhesive formed by spin coating, or an epoxy resin.
  • the adhesive layer 206 is a UV adhesive formed by spin coating. In combination with the glue, the UV adhesive is less viscous under ultraviolet light.
  • the carrier 205 may be a glass, a ceramic, a metal, a polymer, or the like.
  • the carrier 205 includes one of glass, a transparent semiconductor material, and a transparent polymer, so that Exposure of the UV adhesive described above from the back side of the carrier 205 greatly simplifies the subsequent stripping process.
  • step 3 is followed to package the chips 201 with the bumps 203.
  • the height of the molding material 207 after the package 201 of each of the bumps 203 is not higher than the bumps 203 so that the bumps 203 are exposed on the surface of the molding material 207.
  • the molding material 207 used for encapsulating the chips 201 each having the bumps 203 includes one of polyimide, silica gel, and epoxy resin. Wherein, the molding material 207 is added by an additive to form an opaque material.
  • the processes for packaging the chips 201 with the bumps 203 include: an injection molding process, a compression molding process, a printing process, a transfer molding process, a liquid sealant curing process, a vacuum lamination process, and a spin coating process.
  • an injection molding process a compression molding process
  • a printing process a transfer molding process
  • a liquid sealant curing process a vacuum lamination process
  • a spin coating process a spin coating process.
  • the chips 201 with the bumps 203 are encapsulated by an injection molding process
  • the molding material 207 is an opaque silica gel.
  • step 4) is then performed to form a rewiring layer 208 on each of the chips 201 with bumps 203 to achieve interconnection between the chips.
  • step 4) includes:
  • Step 4-1) forming an insulating medium on each of the chips 201 with the bumps 203;
  • Step 4-2) forming a through hole corresponding to the electrical extraction of the chip in the insulating medium by using a photolithography process and an etching process;
  • Step 4-3) filling each of the through holes with a metal conductor to form a connection through hole
  • Step 4-4) forming a metal wiring layer 209 corresponding to the connection via hole on the surface of the insulating medium.
  • the metal wiring layer 209 is formed by an evaporation process, a sputtering process, an electroplating process, or an electroless plating process.
  • the metal wiring layer 209 is formed by a sputtering process.
  • the material of the metal wiring layer 209 includes one of aluminum, copper, tin, nickel, gold, and silver. In the embodiment, the material of the metal wiring layer 209 is copper.
  • step 5 is followed to form the under bump metal layer 210 and the micro bumps 211 on the rewiring layer 208.
  • the micro bumps 211 include one of a gold solder ball, a silver solder ball, and a copper solder ball, or the micro bumps 211 include a copper pillar, a nickel layer formed on the copper pillar, And a solder ball formed on the nickel layer.
  • the micro bumps 211 are gold solder balls, and the manufacturing process includes the steps of: first forming a gold tin layer on the surface of the under bump metal layer 210, and then using a high temperature reflow process to make the gold tin layer It is reflowed into a spherical shape, and after cooling, a gold solder ball is formed.
  • step 6 is performed to remove the carrier 205 and the adhesive layer 206.
  • the carrier 205 includes one of glass, a transparent semiconductor material, and a transparent polymer.
  • the adhesive layer 206 includes a UV adhesive, and in the step 6), the UV adhesive is reduced in viscosity by an exposure method to achieve separation from the molding material 207.
  • the embodiment further provides a package structure of a fan-out type chip, comprising: a chip 201 with a bump 203, a surface of the chip is formed with a dielectric layer 204, and a surface of the dielectric layer 204 is exposed.
  • each of the bumps 203; the molding material 207 is filled between the chips 201 of each of the bumps 203, the height of the molding material 207 does not exceed the bumps 203, so that the bumps 203 are exposed on the surface of the molding material 207;
  • a rewiring layer 208 is formed on the surface of each of the chips 201 with bumps 203 to realize interconnection between the chips; and a under bump metal layer 210 and micro bumps 211 are formed on the rewiring layer 208 .
  • the dielectric layer 204 includes one of silicon dioxide, phosphosilicate glass, silicon oxycarbide, silicon carbide, and a polymer.
  • the molding material 207 includes one of polyimide, silica gel, and epoxy resin.
  • the re-wiring layer 208 includes: an insulating medium formed on each of the chips 201 with the bumps 203; a through hole formed in the insulating medium corresponding to the electrical extraction of the chip; filling the through holes a metal conductor inside; and a metal wiring layer 209 formed on the surface of the insulating medium and correspondingly connected to the connection via.
  • the material of the metal wiring layer 209 includes one of aluminum, copper, tin, nickel, gold, and silver.
  • the microbumps 211 include one of a gold solder ball, a silver solder ball, and a copper solder ball.
  • the microbumps 211 include copper pillars, a nickel layer formed on the copper pillars, and solder balls formed on the nickel layers.
  • the package method and package structure of the fan-out type chip of the present invention have the following advantageous effects: the present invention forms the dielectric layer 204 on the surface of the chip 201 with the bumps 203, and the surface of the dielectric layer 204 is exposed. Each bump 203 can not only protect each bump 203, but also realize interconnection between subsequent chips. Selecting the dielectric layer 204 having a lower coefficient of thermal expansion can avoid the damage or breakage of the bumps 203 due to thermal expansion during the subsequent fabrication of the rewiring layer 208 or the solder microbumps 211, thereby greatly improving the performance of the package. At the same time improve the yield.
  • the structure method of the invention is simple and has broad application prospects in the field of semiconductor packaging. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un procédé d'encapsulation et une structure d'encapsulation pour une puce de sortance. La structure d'encapsulation comprend : des puces (201) pourvues de blocs saillants (203), une couche diélectrique (204) étant formée sur les surfaces des puces (201), et les blocs saillants (203) étant apparents sur les surfaces ; une matière plastique d'encapsulation (207) remplissant l'espace entre les puces (201) pourvues des blocs saillants (203), la hauteur de la matière plastique d'encapsulation (207) étant inférieure ou égale à celle des blocs saillants de façon à permettre aux blocs saillants (203) d'être apparents à la surface de la matière plastique d'encapsulation (207) ; une couche de recâblage (208) formée sur les surfaces des puces (201) pourvues des blocs saillants (203), de manière à mettre en œuvre une interconnexion entre les puces (201) ; et des couches métalliques inférieures de bloc saillant (210) ; et des micro-pointes saillantes (211). La couche diélectrique (204) laissant apparaître les blocs saillants (203) est formée sur les surfaces des puces (201) pourvues des blocs saillants (203), les blocs saillants (203) sont protégés, l'interconnexion subséquente entre les puces (201) est mise en œuvre, et un état endommagé ou cassé des blocs saillants (203) causé par une dilatation thermique dans les processus ultérieurs de fabrication de la couche de recâblage (208) ou de brasage des micro-pointes saillantes (211) est évité, si bien que les performances d'encapsulation sont sensiblement améliorées, et le taux de produits finis est amélioré.
PCT/CN2016/082832 2016-01-22 2016-05-20 Procédé d'encapsulation et structure d'encapsulation pour puce de sortance WO2017124671A1 (fr)

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CN201610046689.0 2016-01-22
CN201610046689.0A CN105489516A (zh) 2016-01-22 2016-01-22 一种扇出型芯片的封装方法及封装结构

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CN113380637A (zh) * 2021-05-20 2021-09-10 苏州通富超威半导体有限公司 扇出型封装方法及扇出型封装器件

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CN105489516A (zh) * 2016-01-22 2016-04-13 中芯长电半导体（江阴）有限公司 一种扇出型芯片的封装方法及封装结构
CN106684066B (zh) 2016-12-30 2020-03-10 华为技术有限公司 一种封装芯片及基于封装芯片的信号传输方法
CN106920784A (zh) * 2017-03-31 2017-07-04 华进半导体封装先导技术研发中心有限公司 一种电力电子器件的扇出型封装结构及封装方法
US10325868B2 (en) 2017-04-24 2019-06-18 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
CN109686716A (zh) * 2018-11-28 2019-04-26 中国电子科技集团公司第五十八研究所 晶圆级扇出封装的圆片结构及采用该圆片结构的晶圆级扇出封装工艺
CN109755376A (zh) * 2019-03-20 2019-05-14 中芯长电半导体（江阴）有限公司 扇出型led的封装结构及封装方法
CN109755375A (zh) * 2019-03-20 2019-05-14 中芯长电半导体（江阴）有限公司 扇出型led的封装结构及封装方法
CN112180128B (zh) * 2020-09-29 2023-08-01 珠海天成先进半导体科技有限公司 一种带弹性导电微凸点的互连基板和基于其的kgd插座
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